1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/gpio/gpio.h>
11 #include "mt7622.dtsi"
12 #include "mt6380.dtsi"
15 model = "Bananapi BPI-R64";
16 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
19 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
24 proc-supply = <&mt6380_vcpu_reg>;
25 sram-supply = <&mt6380_vm_reg>;
29 proc-supply = <&mt6380_vcpu_reg>;
30 sram-supply = <&mt6380_vm_reg>;
35 compatible = "gpio-keys";
40 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
45 linux,code = <KEY_WPS_BUTTON>;
46 gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
51 compatible = "mediatek,mt753x";
52 mediatek,ethsys = <ðsys>;
58 compatible = "gpio-leds";
61 label = "bpi-r64:pio:green";
62 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
63 default-state = "off";
67 label = "bpi-r64:pio:red";
68 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
69 default-state = "off";
74 reg = <0 0x40000000 0 0x40000000>;
77 reg_1p8v: regulator-1p8v {
78 compatible = "regulator-fixed";
79 regulator-name = "fixed-1.8V";
80 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <1800000>;
85 reg_3p3v: regulator-3p3v {
86 compatible = "regulator-fixed";
87 regulator-name = "fixed-3.3V";
88 regulator-min-microvolt = <3300000>;
89 regulator-max-microvolt = <3300000>;
94 reg_5v: regulator-5v {
95 compatible = "regulator-fixed";
96 regulator-name = "fixed-5V";
97 regulator-min-microvolt = <5000000>;
98 regulator-max-microvolt = <5000000>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&irrx_pins>;
122 compatible = "mediatek,eth-mac";
132 compatible = "mediatek,eth-mac";
142 #address-cells = <1>;
148 mediatek,mdio = <&mdio>;
149 mediatek,portmap = "wllll";
150 mediatek,mdio_master_pinmux = <0>;
151 reset-gpios = <&pio 54 0>;
152 interrupt-parent = <&pio>;
153 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
157 compatible = "mediatek,mt753x-port";
167 compatible = "mediatek,mt753x-port";
178 pinctrl-names = "default";
179 pinctrl-0 = <&i2c1_pins>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&i2c2_pins>;
190 pinctrl-names = "default", "state_uhs";
191 pinctrl-0 = <&emmc_pins_default>;
192 pinctrl-1 = <&emmc_pins_uhs>;
195 max-frequency = <50000000>;
198 vmmc-supply = <®_3p3v>;
199 vqmmc-supply = <®_1p8v>;
200 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
201 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
206 pinctrl-names = "default", "state_uhs";
207 pinctrl-0 = <&sd0_pins_default>;
208 pinctrl-1 = <&sd0_pins_uhs>;
211 max-frequency = <50000000>;
214 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
215 vmmc-supply = <®_3p3v>;
216 vqmmc-supply = <®_3p3v>;
217 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
218 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
222 pinctrl-names = "default";
223 pinctrl-0 = <¶llel_nand_pins>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&spi_nor_pins>;
233 compatible = "jedec,spi-nor";
239 pinctrl-names = "default";
240 pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
253 /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
254 * SATA functions. i.e. output-high: PCIe, output-low: SATA
258 gpios = <90 GPIO_ACTIVE_HIGH>;
262 /* eMMC is shared pin with parallel NAND */
263 emmc_pins_default: emmc-pins-default {
265 function = "emmc", "emmc_rst";
269 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
270 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
271 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
274 pins = "NDL0", "NDL1", "NDL2",
275 "NDL3", "NDL4", "NDL5",
276 "NDL6", "NDL7", "NRB";
287 emmc_pins_uhs: emmc-pins-uhs {
294 pins = "NDL0", "NDL1", "NDL2",
295 "NDL3", "NDL4", "NDL5",
296 "NDL6", "NDL7", "NRB";
298 drive-strength = <4>;
304 drive-strength = <4>;
312 groups = "mdc_mdio", "rgmii_via_gmac2";
316 i2c1_pins: i2c1-pins {
323 i2c2_pins: i2c2-pins {
330 i2s1_pins: i2s1-pins {
333 groups = "i2s_out_mclk_bclk_ws",
339 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
340 "I2S_WS", "I2S_MCLK";
341 drive-strength = <12>;
346 irrx_pins: irrx-pins {
353 irtx_pins: irtx-pins {
360 /* Parallel nand is shared pin with eMMC */
361 parallel_nand_pins: parallel-nand-pins {
368 pcie0_pins: pcie0-pins {
371 groups = "pcie0_pad_perst",
377 pcie1_pins: pcie1-pins {
380 groups = "pcie1_pad_perst",
386 pmic_bus_pins: pmic-bus-pins {
393 pwm7_pins: pwm1-2-pins {
396 groups = "pwm_ch7_2";
400 wled_pins: wled-pins {
407 sd0_pins_default: sd0-pins-default {
413 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
414 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
415 * DAT2, DAT3, CMD, CLK for SD respectively.
418 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
419 "I2S2_IN","I2S4_OUT";
421 drive-strength = <8>;
426 drive-strength = <12>;
435 sd0_pins_uhs: sd0-pins-uhs {
442 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
443 "I2S2_IN","I2S4_OUT";
454 /* Serial NAND is shared pin with SPI-NOR */
455 serial_nand_pins: serial-nand-pins {
462 spic0_pins: spic0-pins {
469 spic1_pins: spic1-pins {
476 /* SPI-NOR is shared pin with serial NAND */
477 spi_nor_pins: spi-nor-pins {
484 /* serial NAND is shared pin with SPI-NOR */
485 serial_nand_pins: serial-nand-pins {
492 uart0_pins: uart0-pins {
495 groups = "uart0_0_tx_rx" ;
499 uart2_pins: uart2-pins {
502 groups = "uart2_1_tx_rx" ;
506 watchdog_pins: watchdog-pins {
508 function = "watchdog";
515 pinctrl-names = "default";
516 pinctrl-0 = <&pwm7_pins>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&pmic_bus_pins>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&spic0_pins>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&spic1_pins>;
548 vusb33-supply = <®_3p3v>;
549 vbus-supply = <®_5v>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&uart0_pins>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&uart2_pins>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&watchdog_pins>;