2 * Copyright (C) 2013 Realtek Semiconductor Corp.
5 * Unless you and Realtek execute a separate written software license
6 * agreement governing use of this software, this software is licensed
7 * to you under the terms of the GNU General Public License version 2,
8 * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
11 * $Date: 2017-03-09 10:41:21 +0800 (ι±ε, 09 δΈζ 2017) $
13 * Purpose : RTK switch high-level API
14 * Feature : Here is a list of all functions and variables in this module.
17 #include <rtk_switch.h>
18 #include <rtk_error.h>
22 #include <rtl8367c_asicdrv.h>
23 #include <rtl8367c_asicdrv_misc.h>
24 #include <rtl8367c_asicdrv_green.h>
25 #include <rtl8367c_asicdrv_lut.h>
26 #include <rtl8367c_asicdrv_rma.h>
27 #include <rtl8367c_asicdrv_mirror.h>
29 #if defined(FORCE_PROBE_RTL8367C)
30 static init_state_t init_state
= INIT_COMPLETED
;
31 #elif defined(FORCE_PROBE_RTL8370B)
32 static init_state_t init_state
= INIT_COMPLETED
;
33 #elif defined(FORCE_PROBE_RTL8364B)
34 static init_state_t init_state
= INIT_COMPLETED
;
35 #elif defined(FORCE_PROBE_RTL8363SC_VB)
36 static init_state_t init_state
= INIT_COMPLETED
;
38 static init_state_t init_state
= INIT_NOT_COMPLETED
;
41 #define AUTO_PROBE (!defined(FORCE_PROBE_RTL8367C) && !defined(FORCE_PROBE_RTL8370B) && !defined(FORCE_PROBE_RTL8364B) && !defined(FORCE_PROBE_RTL8363SC_VB))
43 #if (AUTO_PROBE || defined(FORCE_PROBE_RTL8367C))
44 static rtk_switch_halCtrl_t rtl8367c_hal_Ctrl
=
49 /* Logical to Physical */
50 {0, 1, 2, 3, 4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
51 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
53 /* Physical to Logical */
54 {UTP_PORT0
, UTP_PORT1
, UTP_PORT2
, UTP_PORT3
, UTP_PORT4
, UNDEFINE_PORT
, EXT_PORT0
, EXT_PORT1
,
55 UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
,
56 UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
,
57 UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
},
60 {UTP_PORT
, UTP_PORT
, UTP_PORT
, UTP_PORT
, UTP_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
,
61 UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
,
62 EXT_PORT
, EXT_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
,
63 UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
},
66 {1, 1, 1, 1, 1, 0, 0, 0,
67 0, 0, 0, 0, 0, 0, 0, 0,
68 0, 0, 0, 0, 0, 0, 0, 0,
69 0, 0, 0, 0, 0, 0, 0, 0 },
72 ( (0x1 << UTP_PORT0
) | (0x1 << UTP_PORT1
) | (0x1 << UTP_PORT2
) | (0x1 << UTP_PORT3
) | (0x1 << UTP_PORT4
) | (0x1 << EXT_PORT0
) | (0x1 << EXT_PORT1
) ),
74 /* Valid UTP port mask */
75 ( (0x1 << UTP_PORT0
) | (0x1 << UTP_PORT1
) | (0x1 << UTP_PORT2
) | (0x1 << UTP_PORT3
) | (0x1 << UTP_PORT4
) ),
77 /* Valid EXT port mask */
78 ( (0x1 << EXT_PORT0
) | (0x1 << EXT_PORT1
) ),
80 /* Valid CPU port mask */
83 /* Minimum physical port number */
86 /* Maxmum physical port number */
89 /* Physical port mask */
92 /* Combo Logical port ID */
95 /* HSG Logical port ID */
98 /* SGMII Logical portmask */
104 /* MAX LUT Address Number */
107 /* Trunk Group Mask */
112 #if (AUTO_PROBE || defined(FORCE_PROBE_RTL8370B))
113 static rtk_switch_halCtrl_t rtl8370b_hal_Ctrl
=
118 /* Logical to Physical */
119 {0, 1, 2, 3, 4, 5, 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
120 8, 9, 10, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
122 /* Physical to Logical */
123 {UTP_PORT0
, UTP_PORT1
, UTP_PORT2
, UTP_PORT3
, UTP_PORT4
, UTP_PORT5
, UTP_PORT6
, UTP_PORT7
,
124 EXT_PORT0
, EXT_PORT1
, EXT_PORT2
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
,
125 UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
,
126 UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
},
129 {UTP_PORT
, UTP_PORT
, UTP_PORT
, UTP_PORT
, UTP_PORT
, UTP_PORT
, UTP_PORT
, UTP_PORT
,
130 UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
,
131 EXT_PORT
, EXT_PORT
, EXT_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
,
132 UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
},
135 {1, 1, 1, 1, 1, 1, 1, 1,
136 0, 0, 0, 0, 0, 0, 0, 0,
137 1, 1, 0, 0, 0, 0, 0, 0,
138 0, 0, 0, 0, 0, 0, 0, 0 },
140 /* Valid port mask */
141 ( (0x1 << UTP_PORT0
) | (0x1 << UTP_PORT1
) | (0x1 << UTP_PORT2
) | (0x1 << UTP_PORT3
) | (0x1 << UTP_PORT4
) | (0x1 << UTP_PORT5
) | (0x1 << UTP_PORT6
) | (0x1 << UTP_PORT7
) | (0x1 << EXT_PORT0
) | (0x1 << EXT_PORT1
) | (0x1 << EXT_PORT2
) ),
143 /* Valid UTP port mask */
144 ( (0x1 << UTP_PORT0
) | (0x1 << UTP_PORT1
) | (0x1 << UTP_PORT2
) | (0x1 << UTP_PORT3
) | (0x1 << UTP_PORT4
) | (0x1 << UTP_PORT5
) | (0x1 << UTP_PORT6
) | (0x1 << UTP_PORT7
) ),
146 /* Valid EXT port mask */
147 ( (0x1 << EXT_PORT0
) | (0x1 << EXT_PORT1
) | (0x1 << EXT_PORT2
) ),
149 /* Valid CPU port mask */
152 /* Minimum physical port number */
155 /* Maxmum physical port number */
158 /* Physical port mask */
161 /* Combo Logical port ID */
164 /* HSG Logical port ID */
167 /* SGMII Logical portmask */
168 ( (0x1 << EXT_PORT0
) | (0x1 << EXT_PORT1
) ),
173 /* MAX LUT Address Number 4096 + 64*/
176 /* Trunk Group Mask */
181 #if (AUTO_PROBE || defined(FORCE_PROBE_RTL8364B))
182 static rtk_switch_halCtrl_t rtl8364b_hal_Ctrl
=
187 /* Logical to Physical */
188 {0xFF, 1, 0xFF, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
189 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
191 /* Physical to Logical */
192 {UNDEFINE_PORT
, UTP_PORT1
, UNDEFINE_PORT
, UTP_PORT3
, UNDEFINE_PORT
, UNDEFINE_PORT
, EXT_PORT0
, EXT_PORT1
,
193 UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
,
194 UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
,
195 UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
},
198 {UNKNOWN_PORT
, UTP_PORT
, UNKNOWN_PORT
, UTP_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
,
199 UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
,
200 EXT_PORT
, EXT_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
,
201 UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
},
204 {0, 0, 0, 0, 0, 0, 0, 0,
205 0, 0, 0, 0, 0, 0, 0, 0,
206 0, 0, 0, 0, 0, 0, 0, 0,
207 0, 0, 0, 0, 0, 0, 0, 0 },
209 /* Valid port mask */
210 ( (0x1 << UTP_PORT1
) | (0x1 << UTP_PORT3
) | (0x1 << EXT_PORT0
) | (0x1 << EXT_PORT1
) ),
212 /* Valid UTP port mask */
213 ( (0x1 << UTP_PORT1
) | (0x1 << UTP_PORT3
) ),
215 /* Valid EXT port mask */
216 ( (0x1 << EXT_PORT0
) | (0x1 << EXT_PORT1
) ),
218 /* Valid CPU port mask */
221 /* Minimum physical port number */
224 /* Maxmum physical port number */
227 /* Physical port mask */
230 /* Combo Logical port ID */
233 /* HSG Logical port ID */
236 /* SGMII Logical portmask */
237 ( (0x1 << EXT_PORT0
) | (0x1 << EXT_PORT1
) ),
242 /* MAX LUT Address Number */
245 /* Trunk Group Mask */
250 #if (AUTO_PROBE || defined(FORCE_PROBE_RTL8363SC_VB))
251 static rtk_switch_halCtrl_t rtl8363sc_vb_hal_Ctrl
=
256 /* Logical to Physical */
257 {0xFF, 0xFF, 1, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
258 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
260 /* Physical to Logical */
261 {UNDEFINE_PORT
, UTP_PORT2
, UNDEFINE_PORT
, UTP_PORT3
, UNDEFINE_PORT
, UNDEFINE_PORT
, EXT_PORT0
, EXT_PORT1
,
262 UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
,
263 UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
,
264 UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
, UNDEFINE_PORT
},
267 {UNKNOWN_PORT
, UNKNOWN_PORT
, UTP_PORT
, UTP_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
,
268 UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
,
269 EXT_PORT
, EXT_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
,
270 UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
, UNKNOWN_PORT
},
273 {0, 0, 0, 0, 0, 0, 0, 0,
274 0, 0, 0, 0, 0, 0, 0, 0,
275 0, 0, 0, 0, 0, 0, 0, 0,
276 0, 0, 0, 0, 0, 0, 0, 0 },
278 /* Valid port mask */
279 ( (0x1 << UTP_PORT2
) | (0x1 << UTP_PORT3
) | (0x1 << EXT_PORT0
) | (0x1 << EXT_PORT1
) ),
281 /* Valid UTP port mask */
282 ( (0x1 << UTP_PORT2
) | (0x1 << UTP_PORT3
) ),
284 /* Valid EXT port mask */
285 ( (0x1 << EXT_PORT0
) | (0x1 << EXT_PORT1
) ),
287 /* Valid CPU port mask */
290 /* Minimum physical port number */
293 /* Maxmum physical port number */
296 /* Physical port mask */
299 /* Combo Logical port ID */
302 /* HSG Logical port ID */
305 /* SGMII Logical portmask */
306 ( (0x1 << EXT_PORT0
) | (0x1 << EXT_PORT1
) ),
311 /* MAX LUT Address Number */
314 /* Trunk Group Mask */
319 #if defined(FORCE_PROBE_RTL8367C)
320 static rtk_switch_halCtrl_t
*halCtrl
= &rtl8367c_hal_Ctrl
;
321 #elif defined(FORCE_PROBE_RTL8370B)
322 static rtk_switch_halCtrl_t
*halCtrl
= &rtl8370b_hal_Ctrl
;
323 #elif defined(FORCE_PROBE_RTL8364B)
324 static rtk_switch_halCtrl_t
*halCtrl
= &rtl8364b_hal_Ctrl
;
325 #elif defined(FORCE_PROBE_RTL8363SC_VB)
326 static rtk_switch_halCtrl_t
*halCtrl
= &rtl8363sc_vb_hal_Ctrl
;
328 static rtk_switch_halCtrl_t
*halCtrl
= NULL
;
331 static rtk_uint32 PatchChipData
[210][2] =
333 {0xa436, 0x8028}, {0xa438, 0x6800}, {0xb82e, 0x0001}, {0xa436, 0xb820}, {0xa438, 0x0090}, {0xa436, 0xa012}, {0xa438, 0x0000}, {0xa436, 0xa014}, {0xa438, 0x2c04}, {0xa438, 0x2c6c},
334 {0xa438, 0x2c75}, {0xa438, 0x2c77}, {0xa438, 0x1414}, {0xa438, 0x1579}, {0xa438, 0x1536}, {0xa438, 0xc432}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5}, {0xa438, 0x003e},
335 {0xa438, 0x614c}, {0xa438, 0x1569}, {0xa438, 0xd705}, {0xa438, 0x318c}, {0xa438, 0x42d6}, {0xa438, 0xd702}, {0xa438, 0x31ef}, {0xa438, 0x42d6}, {0xa438, 0x629c}, {0xa438, 0x2c04},
336 {0xa438, 0x653c}, {0xa438, 0x422a}, {0xa438, 0x5d83}, {0xa438, 0xd06a}, {0xa438, 0xd1b0}, {0xa438, 0x1536}, {0xa438, 0xc43a}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5},
337 {0xa438, 0x003e}, {0xa438, 0x314a}, {0xa438, 0x42fe}, {0xa438, 0x337b}, {0xa438, 0x02d6}, {0xa438, 0x3063}, {0xa438, 0x0c1b}, {0xa438, 0x22fe}, {0xa438, 0xc435}, {0xa438, 0xd0be},
338 {0xa438, 0xd1f7}, {0xa438, 0xe0f0}, {0xa438, 0x1a40}, {0xa438, 0xa320}, {0xa438, 0xd702}, {0xa438, 0x154a}, {0xa438, 0xc434}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5},
339 {0xa438, 0x003e}, {0xa438, 0x60ec}, {0xa438, 0x1569}, {0xa438, 0xd705}, {0xa438, 0x619f}, {0xa438, 0xd702}, {0xa438, 0x414f}, {0xa438, 0x2c2e}, {0xa438, 0x610a}, {0xa438, 0xd705},
340 {0xa438, 0x5e1f}, {0xa438, 0xc43f}, {0xa438, 0xc88b}, {0xa438, 0xd702}, {0xa438, 0x7fe0}, {0xa438, 0x22f3}, {0xa438, 0xd0a0}, {0xa438, 0xd1b2}, {0xa438, 0xd0c3}, {0xa438, 0xd1c3},
341 {0xa438, 0x8d01}, {0xa438, 0x1536}, {0xa438, 0xc438}, {0xa438, 0xe0f0}, {0xa438, 0x1a80}, {0xa438, 0xd706}, {0xa438, 0x60c0}, {0xa438, 0xd710}, {0xa438, 0x409e}, {0xa438, 0xa804},
342 {0xa438, 0xad01}, {0xa438, 0x8804}, {0xa438, 0xd702}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5}, {0xa438, 0x003e}, {0xa438, 0x405b}, {0xa438, 0x1576}, {0xa438, 0x7c9c},
343 {0xa438, 0x60ec}, {0xa438, 0x1569}, {0xa438, 0xd702}, {0xa438, 0x5d43}, {0xa438, 0x31ef}, {0xa438, 0x02fe}, {0xa438, 0x22d6}, {0xa438, 0x590a}, {0xa438, 0xd706}, {0xa438, 0x5c80},
344 {0xa438, 0xd702}, {0xa438, 0x5c44}, {0xa438, 0x3063}, {0xa438, 0x02d6}, {0xa438, 0x5be2}, {0xa438, 0x22fb}, {0xa438, 0xa240}, {0xa438, 0xa104}, {0xa438, 0x8c03}, {0xa438, 0x8178},
345 {0xa438, 0xd701}, {0xa438, 0x31ad}, {0xa438, 0x4917}, {0xa438, 0x8102}, {0xa438, 0x2917}, {0xa438, 0xc302}, {0xa438, 0x268a}, {0xa436, 0xA01A}, {0xa438, 0x0000}, {0xa436, 0xA006},
346 {0xa438, 0x0fff}, {0xa436, 0xA004}, {0xa438, 0x0689}, {0xa436, 0xA002}, {0xa438, 0x0911}, {0xa436, 0xA000}, {0xa438, 0x7302}, {0xa436, 0xB820}, {0xa438, 0x0010}, {0xa436, 0x8412},
347 {0xa438, 0xaf84}, {0xa438, 0x1eaf}, {0xa438, 0x8427}, {0xa438, 0xaf84}, {0xa438, 0x27af}, {0xa438, 0x8427}, {0xa438, 0x0251}, {0xa438, 0x6802}, {0xa438, 0x8427}, {0xa438, 0xaf04},
348 {0xa438, 0x0af8}, {0xa438, 0xf9bf}, {0xa438, 0x5581}, {0xa438, 0x0255}, {0xa438, 0x27ef}, {0xa438, 0x310d}, {0xa438, 0x345b}, {0xa438, 0x0fa3}, {0xa438, 0x032a}, {0xa438, 0xe087},
349 {0xa438, 0xffac}, {0xa438, 0x2040}, {0xa438, 0xbf56}, {0xa438, 0x7402}, {0xa438, 0x5527}, {0xa438, 0xef31}, {0xa438, 0xef20}, {0xa438, 0xe787}, {0xa438, 0xfee6}, {0xa438, 0x87fd},
350 {0xa438, 0xd488}, {0xa438, 0x88bf}, {0xa438, 0x5674}, {0xa438, 0x0254}, {0xa438, 0xe3e0}, {0xa438, 0x87ff}, {0xa438, 0xf720}, {0xa438, 0xe487}, {0xa438, 0xffaf}, {0xa438, 0x847e},
351 {0xa438, 0xe087}, {0xa438, 0xffad}, {0xa438, 0x2016}, {0xa438, 0xe387}, {0xa438, 0xfee2}, {0xa438, 0x87fd}, {0xa438, 0xef45}, {0xa438, 0xbf56}, {0xa438, 0x7402}, {0xa438, 0x54e3},
352 {0xa438, 0xe087}, {0xa438, 0xfff6}, {0xa438, 0x20e4}, {0xa438, 0x87ff}, {0xa438, 0xfdfc}, {0xa438, 0x0400}, {0xa436, 0xb818}, {0xa438, 0x0407}, {0xa436, 0xb81a}, {0xa438, 0xfffd},
353 {0xa436, 0xb81c}, {0xa438, 0xfffd}, {0xa436, 0xb81e}, {0xa438, 0xfffd}, {0xa436, 0xb832}, {0xa438, 0x0001}, {0xb820, 0x0000}, {0xb82e, 0x0000}, {0xa436, 0x8028}, {0xa438, 0x0000}
356 static rtk_api_ret_t
_rtk_switch_init_8367c(void)
363 if( (retVal
= rtl8367c_setAsicReg(0x13c2, 0x0249)) != RT_ERR_OK
)
366 if( (retVal
= rtl8367c_getAsicReg(0x1301, ®Value
)) != RT_ERR_OK
)
369 if( (retVal
= rtl8367c_setAsicReg(0x13c2, 0x0000)) != RT_ERR_OK
)
372 RTK_SCAN_ALL_LOG_PORT(port
)
374 if(rtk_switch_isUtpPort(port
) == RT_ERR_OK
)
376 if((retVal
= rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG
+ (0x20 * port
), RTL8367C_PORT0_EEECFG_EEE_100M_OFFSET
, 1)) != RT_ERR_OK
)
379 if((retVal
= rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG
+ (0x20 * port
), RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_OFFSET
, 1)) != RT_ERR_OK
)
382 if((retVal
= rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG
+ (0x20 * port
), RTL8367C_PORT0_EEECFG_EEE_TX_OFFSET
, 1)) != RT_ERR_OK
)
385 if((retVal
= rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG
+ (0x20 * port
), RTL8367C_PORT0_EEECFG_EEE_RX_OFFSET
, 1)) != RT_ERR_OK
)
388 if((retVal
= rtl8367c_getAsicPHYOCPReg(port
, 0xA428, ®Data
)) != RT_ERR_OK
)
391 regData
&= ~(0x0200);
392 if((retVal
= rtl8367c_setAsicPHYOCPReg(port
, 0xA428, regData
)) != RT_ERR_OK
)
395 if((regValue
& 0x00F0) == 0x00A0)
397 if((retVal
= rtl8367c_getAsicPHYOCPReg(port
, 0xA5D0, ®Data
)) != RT_ERR_OK
)
401 if((retVal
= rtl8367c_setAsicPHYOCPReg(port
, 0xA5D0, regData
)) != RT_ERR_OK
)
407 if((retVal
= rtl8367c_setAsicReg(RTL8367C_REG_UTP_FIB_DET
, 0x15BB)) != RT_ERR_OK
)
410 if((retVal
= rtl8367c_setAsicReg(0x1303, 0x06D6)) != RT_ERR_OK
)
413 if((retVal
= rtl8367c_setAsicReg(0x1304, 0x0700)) != RT_ERR_OK
)
416 if((retVal
= rtl8367c_setAsicReg(0x13E2, 0x003F)) != RT_ERR_OK
)
419 if((retVal
= rtl8367c_setAsicReg(0x13F9, 0x0090)) != RT_ERR_OK
)
422 if((retVal
= rtl8367c_setAsicReg(0x121e, 0x03CA)) != RT_ERR_OK
)
425 if((retVal
= rtl8367c_setAsicReg(0x1233, 0x0352)) != RT_ERR_OK
)
428 if((retVal
= rtl8367c_setAsicReg(0x1237, 0x00a0)) != RT_ERR_OK
)
431 if((retVal
= rtl8367c_setAsicReg(0x123a, 0x0030)) != RT_ERR_OK
)
434 if((retVal
= rtl8367c_setAsicReg(0x1239, 0x0084)) != RT_ERR_OK
)
437 if((retVal
= rtl8367c_setAsicReg(0x0301, 0x1000)) != RT_ERR_OK
)
440 if((retVal
= rtl8367c_setAsicReg(0x1349, 0x001F)) != RT_ERR_OK
)
443 if((retVal
= rtl8367c_setAsicRegBit(0x18e0, 0, 0)) != RT_ERR_OK
)
446 if((retVal
= rtl8367c_setAsicRegBit(0x122b, 14, 1)) != RT_ERR_OK
)
449 if((retVal
= rtl8367c_setAsicRegBits(0x1305, 0xC000, 3)) != RT_ERR_OK
)
455 static rtk_api_ret_t
_rtk_switch_init_8370b(void)
458 rtk_uint32 regData
, tmp
= 0;
459 rtk_uint32 i
, prf
, counter
;
460 rtk_uint32 long_link
[8] = {0x0210, 0x03e8, 0x0218, 0x03f0, 0x0220, 0x03f8, 0x0208, 0x03e0 };
462 if((retVal
= rtl8367c_setAsicRegBits(0x1205, 0x0300, 3)) != RT_ERR_OK
)
468 if ((retVal
= rtl8367c_getAsicPHYOCPReg(i
, 0xa420, ®Data
)) != RT_ERR_OK
)
470 tmp
= regData
& 0x7 ;
474 if((retVal
= rtl8367c_setAsicPHYOCPReg(i
, 0xb83e, 0x6fa9)) != RT_ERR_OK
)
476 if((retVal
= rtl8367c_setAsicPHYOCPReg(i
, 0xb840, 0xa9)) != RT_ERR_OK
)
478 for(counter
= 0; counter
< 10000; counter
++); //delay
480 if ((retVal
= rtl8367c_getAsicPHYOCPReg(i
, 0xb820, ®Data
)) != RT_ERR_OK
)
482 tmp
= regData
| 0x10;
483 if ((retVal
= rtl8367c_setAsicPHYOCPReg(i
, 0xb820, tmp
)) != RT_ERR_OK
)
485 for(counter
= 0; counter
< 10000; counter
++); //delay
488 counter
= counter
+ 1;
489 if ((retVal
= rtl8367c_getAsicPHYOCPReg(i
, 0xb800, ®Data
)) != RT_ERR_OK
)
491 tmp
= regData
& 0x40;
494 } while (counter
< 20); //Wait for patch ready = 1...
497 if ((retVal
= rtl8367c_getAsicReg(0x1d01, ®Data
)) != RT_ERR_OK
)
500 tmp
= tmp
| 0x3BE0; /*Broadcast port enable*/
501 tmp
= tmp
& 0xFFE0; /*Phy_id = 0 */
502 if((retVal
= rtl8367c_setAsicReg(0x1d01, tmp
)) != RT_ERR_OK
)
505 for(i
=0;i
< 210; i
++)
507 if((retVal
= rtl8367c_setAsicPHYOCPReg(0, PatchChipData
[i
][0], PatchChipData
[i
][1])) != RT_ERR_OK
)
511 if((retVal
= rtl8367c_setAsicReg(0x1d01, regData
)) != RT_ERR_OK
)
516 if((retVal
= rtl8367c_setAsicPHYOCPReg(i
, 0xa4b4, long_link
[i
])) != RT_ERR_OK
)
524 if ((retVal
= rtl8367c_getAsicPHYOCPReg(i
, 0xb820, ®Data
)) != RT_ERR_OK
)
526 tmp
= regData
& 0xFFEF;
527 if ((retVal
= rtl8367c_setAsicPHYOCPReg(i
, 0xb820, tmp
)) != RT_ERR_OK
)
530 for(counter
= 0; counter
< 10000; counter
++); //delay
534 counter
= counter
+ 1;
535 if ((retVal
= rtl8367c_getAsicPHYOCPReg(i
, 0xb800, ®Data
)) != RT_ERR_OK
)
537 tmp
= regData
& 0x40;
540 } while (counter
< 20); //Wait for patch ready = 1...
541 if ((retVal
= rtl8367c_setAsicPHYOCPReg(i
, 0xb83e, 0x6f48)) != RT_ERR_OK
)
543 if ((retVal
= rtl8367c_setAsicPHYOCPReg(i
, 0xb840, 0xfa)) != RT_ERR_OK
)
548 /*Check phy link status*/
551 if ((retVal
= rtl8367c_getAsicPHYOCPReg(i
, 0xa400, ®Data
)) != RT_ERR_OK
)
553 tmp
= regData
& 0x800;
556 tmp
= regData
| 0x200;
557 if ((retVal
= rtl8367c_setAsicPHYOCPReg(i
, 0xa400, tmp
)) != RT_ERR_OK
)
562 for(counter
= 0; counter
< 10000; counter
++); //delay
567 static rtk_api_ret_t
_rtk_switch_init_8364b(void)
572 /*enable EEE, include mac & phy*/
574 if ((retVal
= rtl8367c_setAsicRegBits(0x38, 0x300, 3)) != RT_ERR_OK
)
576 if ((retVal
= rtl8367c_setAsicRegBits(0x78, 0x300, 3)) != RT_ERR_OK
)
578 if ((retVal
= rtl8367c_setAsicRegBits(0xd8, 0x300, 0)) != RT_ERR_OK
)
580 if ((retVal
= rtl8367c_setAsicRegBits(0xf8, 0x300, 0)) != RT_ERR_OK
)
583 if ((retVal
= rtl8367c_setAsicPHYOCPReg(1, 0xa5d0, 6)) != RT_ERR_OK
)
585 if ((retVal
= rtl8367c_setAsicPHYOCPReg(3, 0xa5d0, 6)) != RT_ERR_OK
)
591 if ((retVal
= rtl8367c_getAsicReg(0x1303, ®Data
)) != RT_ERR_OK
)
593 regData
&= 0xFFFFFFFE;
595 if((retVal
= rtl8367c_setAsicReg(0x1303, regData
)) != RT_ERR_OK
)
598 if ((retVal
= rtl8367c_setAsicRegBits(0x1304, 0x7000, 0)) != RT_ERR_OK
)
600 if ((retVal
= rtl8367c_setAsicRegBits(0x1304, 0x700, 7)) != RT_ERR_OK
)
602 if ((retVal
= rtl8367c_setAsicRegBits(0x13f9, 0x38, 0)) != RT_ERR_OK
)
606 if ((retVal
= rtl8367c_setAsicRegBit(0x1303, 10, 1)) != RT_ERR_OK
)
608 if ((retVal
= rtl8367c_setAsicRegBits(0x13E2, 0x1ff, 0x26)) != RT_ERR_OK
)
610 if ((retVal
= rtl8367c_setAsicRegBits(0x13f9, 0x1c0, 0)) != RT_ERR_OK
)
615 /*SP_CFG_EN_LINK_FIB1G*/
616 if((retVal
= rtl8367c_getAsicSdsReg(0, 4, 0, ®Data
)) != RT_ERR_OK
)
619 if((retVal
= rtl8367c_setAsicSdsReg(0,4,0, regData
)) != RT_ERR_OK
)
622 /*FIB100 Down-speed*/
623 if((retVal
= rtl8367c_getAsicSdsReg(0, 1, 0, ®Data
)) != RT_ERR_OK
)
626 if((retVal
= rtl8367c_setAsicSdsReg(0,1,0, regData
)) != RT_ERR_OK
)
632 static rtk_api_ret_t
_rtk_switch_init_8363sc_vb(void)
638 /*enable EEE, include mac & phy*/
640 if ((retVal
= rtl8367c_setAsicRegBits(0x38, 0x300, 3)) != RT_ERR_OK
)
642 if ((retVal
= rtl8367c_setAsicRegBits(0x78, 0x300, 3)) != RT_ERR_OK
)
644 if ((retVal
= rtl8367c_setAsicRegBits(0xd8, 0x300, 0)) != RT_ERR_OK
)
646 if ((retVal
= rtl8367c_setAsicRegBits(0xf8, 0x300, 0)) != RT_ERR_OK
)
649 if ((retVal
= rtl8367c_setAsicPHYOCPReg(1, 0xa5d0, 6)) != RT_ERR_OK
)
651 if ((retVal
= rtl8367c_setAsicPHYOCPReg(3, 0xa5d0, 6)) != RT_ERR_OK
)
657 if ((retVal
= rtl8367c_getAsicReg(0x1303, ®Data
)) != RT_ERR_OK
)
659 regData
&= 0xFFFFFFFE;
661 if((retVal
= rtl8367c_setAsicReg(0x1303, regData
)) != RT_ERR_OK
)
664 if ((retVal
= rtl8367c_setAsicRegBits(0x1304, 0x7000, 0)) != RT_ERR_OK
)
666 if ((retVal
= rtl8367c_setAsicRegBits(0x1304, 0x700, 7)) != RT_ERR_OK
)
668 if ((retVal
= rtl8367c_setAsicRegBits(0x13f9, 0x38, 0)) != RT_ERR_OK
)
672 if ((retVal
= rtl8367c_setAsicRegBit(0x1303, 10, 1)) != RT_ERR_OK
)
674 if ((retVal
= rtl8367c_setAsicRegBits(0x13E2, 0x1ff, 0x26)) != RT_ERR_OK
)
676 if ((retVal
= rtl8367c_setAsicRegBits(0x13f9, 0x1c0, 0)) != RT_ERR_OK
)
681 /*SP_CFG_EN_LINK_FIB1G*/
682 if((retVal
= rtl8367c_getAsicSdsReg(0, 4, 0, ®Data
)) != RT_ERR_OK
)
685 if((retVal
= rtl8367c_setAsicSdsReg(0,4,0, regData
)) != RT_ERR_OK
)
688 /*FIB100 Down-speed*/
689 if((retVal
= rtl8367c_getAsicSdsReg(0, 1, 0, ®Data
)) != RT_ERR_OK
)
692 if((retVal
= rtl8367c_setAsicSdsReg(0,1,0, regData
)) != RT_ERR_OK
)
707 * RT_ERR_OK - Switch probed
708 * RT_ERR_FAILED - Switch Unprobed.
712 rtk_api_ret_t
rtk_switch_probe(switch_chip_t
*pSwitchChip
)
714 #if defined(FORCE_PROBE_RTL8367C)
716 *pSwitchChip
= CHIP_RTL8367C
;
717 halCtrl
= &rtl8367c_hal_Ctrl
;
719 #elif defined(FORCE_PROBE_RTL8370B)
721 *pSwitchChip
= CHIP_RTL8370B
;
722 halCtrl
= &rtl8370b_hal_Ctrl
;
724 #elif defined(FORCE_PROBE_RTL8364B)
726 *pSwitchChip
= CHIP_RTL8364B
;
727 halCtrl
= &rtl8364b_hal_Ctrl
;
729 #elif defined(FORCE_PROBE_RTL8363SC_VB)
731 *pSwitchChip
= CHIP_RTL8363SC_VB
;
732 halCtrl
= &rtl8363sc_vb_hal_Ctrl
;
736 rtk_uint32 data
, regValue
;
738 if((retVal
= rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK
)
741 if((retVal
= rtl8367c_getAsicReg(0x1300, &data
)) != RT_ERR_OK
)
744 if((retVal
= rtl8367c_getAsicReg(0x1301, ®Value
)) != RT_ERR_OK
)
747 if((retVal
= rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK
)
755 *pSwitchChip
= CHIP_RTL8367C
;
756 halCtrl
= &rtl8367c_hal_Ctrl
;
760 *pSwitchChip
= CHIP_RTL8370B
;
761 halCtrl
= &rtl8370b_hal_Ctrl
;
765 if( (regValue
& 0x00F0) == 0x0080)
767 *pSwitchChip
= CHIP_RTL8363SC_VB
;
768 halCtrl
= &rtl8363sc_vb_hal_Ctrl
;
772 *pSwitchChip
= CHIP_RTL8364B
;
773 halCtrl
= &rtl8364b_hal_Ctrl
;
777 return RT_ERR_FAILED
;
785 * rtk_switch_initialState_set
789 * state - Initial state;
793 * RT_ERR_OK - Initialized
794 * RT_ERR_FAILED - Uninitialized
798 rtk_api_ret_t
rtk_switch_initialState_set(init_state_t state
)
800 if(state
>= INIT_STATE_END
)
801 return RT_ERR_FAILED
;
808 * rtk_switch_initialState_get
816 * INIT_COMPLETED - Initialized
817 * INIT_NOT_COMPLETED - Uninitialized
821 init_state_t
rtk_switch_initialState_get(void)
827 * rtk_switch_logicalPortCheck
829 * Check logical port ID.
831 * logicalPort - logical port ID
835 * RT_ERR_OK - Port ID is correct
836 * RT_ERR_FAILED - Port ID is not correct
837 * RT_ERR_NOT_INIT - Not Initialize
841 rtk_api_ret_t
rtk_switch_logicalPortCheck(rtk_port_t logicalPort
)
843 if(init_state
!= INIT_COMPLETED
)
844 return RT_ERR_NOT_INIT
;
846 if(logicalPort
>= RTK_SWITCH_PORT_NUM
)
847 return RT_ERR_FAILED
;
849 if(halCtrl
->l2p_port
[logicalPort
] == 0xFF)
850 return RT_ERR_FAILED
;
856 * rtk_switch_isUtpPort
858 * Check is logical port a UTP port
860 * logicalPort - logical port ID
864 * RT_ERR_OK - Port ID is a UTP port
865 * RT_ERR_FAILED - Port ID is not a UTP port
866 * RT_ERR_NOT_INIT - Not Initialize
870 rtk_api_ret_t
rtk_switch_isUtpPort(rtk_port_t logicalPort
)
872 if(init_state
!= INIT_COMPLETED
)
873 return RT_ERR_NOT_INIT
;
875 if(logicalPort
>= RTK_SWITCH_PORT_NUM
)
876 return RT_ERR_FAILED
;
878 if(halCtrl
->log_port_type
[logicalPort
] == UTP_PORT
)
881 return RT_ERR_FAILED
;
885 * rtk_switch_isExtPort
887 * Check is logical port a Extension port
889 * logicalPort - logical port ID
893 * RT_ERR_OK - Port ID is a EXT port
894 * RT_ERR_FAILED - Port ID is not a EXT port
895 * RT_ERR_NOT_INIT - Not Initialize
899 rtk_api_ret_t
rtk_switch_isExtPort(rtk_port_t logicalPort
)
901 if(init_state
!= INIT_COMPLETED
)
902 return RT_ERR_NOT_INIT
;
904 if(logicalPort
>= RTK_SWITCH_PORT_NUM
)
905 return RT_ERR_FAILED
;
907 if(halCtrl
->log_port_type
[logicalPort
] == EXT_PORT
)
910 return RT_ERR_FAILED
;
915 * rtk_switch_isHsgPort
917 * Check is logical port a HSG port
919 * logicalPort - logical port ID
923 * RT_ERR_OK - Port ID is a HSG port
924 * RT_ERR_FAILED - Port ID is not a HSG port
925 * RT_ERR_NOT_INIT - Not Initialize
929 rtk_api_ret_t
rtk_switch_isHsgPort(rtk_port_t logicalPort
)
931 if(init_state
!= INIT_COMPLETED
)
932 return RT_ERR_NOT_INIT
;
934 if(logicalPort
>= RTK_SWITCH_PORT_NUM
)
935 return RT_ERR_FAILED
;
937 if(logicalPort
== halCtrl
->hsg_logical_port
)
940 return RT_ERR_FAILED
;
944 * rtk_switch_isSgmiiPort
946 * Check is logical port a SGMII port
948 * logicalPort - logical port ID
952 * RT_ERR_OK - Port ID is a SGMII port
953 * RT_ERR_FAILED - Port ID is not a SGMII port
954 * RT_ERR_NOT_INIT - Not Initialize
958 rtk_api_ret_t
rtk_switch_isSgmiiPort(rtk_port_t logicalPort
)
960 if(init_state
!= INIT_COMPLETED
)
961 return RT_ERR_NOT_INIT
;
963 if(logicalPort
>= RTK_SWITCH_PORT_NUM
)
964 return RT_ERR_FAILED
;
966 if( ((0x01 << logicalPort
) & halCtrl
->sg_logical_portmask
) != 0)
969 return RT_ERR_FAILED
;
973 * rtk_switch_isCPUPort
975 * Check is logical port a CPU port
977 * logicalPort - logical port ID
981 * RT_ERR_OK - Port ID is a CPU port
982 * RT_ERR_FAILED - Port ID is not a CPU port
983 * RT_ERR_NOT_INIT - Not Initialize
987 rtk_api_ret_t
rtk_switch_isCPUPort(rtk_port_t logicalPort
)
989 if(init_state
!= INIT_COMPLETED
)
990 return RT_ERR_NOT_INIT
;
992 if(logicalPort
>= RTK_SWITCH_PORT_NUM
)
993 return RT_ERR_FAILED
;
995 if( ((0x01 << logicalPort
) & halCtrl
->valid_cpu_portmask
) != 0)
998 return RT_ERR_FAILED
;
1002 * rtk_switch_isComboPort
1004 * Check is logical port a Combo port
1006 * logicalPort - logical port ID
1010 * RT_ERR_OK - Port ID is a combo port
1011 * RT_ERR_FAILED - Port ID is not a combo port
1012 * RT_ERR_NOT_INIT - Not Initialize
1016 rtk_api_ret_t
rtk_switch_isComboPort(rtk_port_t logicalPort
)
1018 if(init_state
!= INIT_COMPLETED
)
1019 return RT_ERR_NOT_INIT
;
1021 if(logicalPort
>= RTK_SWITCH_PORT_NUM
)
1022 return RT_ERR_FAILED
;
1024 if(halCtrl
->combo_logical_port
== logicalPort
)
1027 return RT_ERR_FAILED
;
1031 * rtk_switch_ComboPort_get
1039 * Port ID of combo port
1043 rtk_uint32
rtk_switch_ComboPort_get(void)
1045 return halCtrl
->combo_logical_port
;
1049 * rtk_switch_isPtpPort
1051 * Check is logical port a PTP port
1053 * logicalPort - logical port ID
1057 * RT_ERR_OK - Port ID is a PTP port
1058 * RT_ERR_FAILED - Port ID is not a PTP port
1059 * RT_ERR_NOT_INIT - Not Initialize
1063 rtk_api_ret_t
rtk_switch_isPtpPort(rtk_port_t logicalPort
)
1065 if(init_state
!= INIT_COMPLETED
)
1066 return RT_ERR_NOT_INIT
;
1068 if(logicalPort
>= RTK_SWITCH_PORT_NUM
)
1069 return RT_ERR_FAILED
;
1071 if(halCtrl
->ptp_port
[logicalPort
] == 1)
1074 return RT_ERR_FAILED
;
1078 * rtk_switch_port_L2P_get
1080 * Get physical port ID
1082 * logicalPort - logical port ID
1090 rtk_uint32
rtk_switch_port_L2P_get(rtk_port_t logicalPort
)
1092 if(init_state
!= INIT_COMPLETED
)
1093 return UNDEFINE_PHY_PORT
;
1095 if(logicalPort
>= RTK_SWITCH_PORT_NUM
)
1096 return UNDEFINE_PHY_PORT
;
1098 return (halCtrl
->l2p_port
[logicalPort
]);
1102 * rtk_switch_port_P2L_get
1104 * Get logical port ID
1106 * physicalPort - physical port ID
1114 rtk_port_t
rtk_switch_port_P2L_get(rtk_uint32 physicalPort
)
1116 if(init_state
!= INIT_COMPLETED
)
1117 return UNDEFINE_PORT
;
1119 if(physicalPort
>= RTK_SWITCH_PORT_NUM
)
1120 return UNDEFINE_PORT
;
1122 return (halCtrl
->p2l_port
[physicalPort
]);
1126 * rtk_switch_isPortMaskValid
1128 * Check portmask is valid or not
1130 * pPmask - logical port mask
1134 * RT_ERR_OK - port mask is valid
1135 * RT_ERR_FAILED - port mask is not valid
1136 * RT_ERR_NOT_INIT - Not Initialize
1137 * RT_ERR_NULL_POINTER - Null pointer
1141 rtk_api_ret_t
rtk_switch_isPortMaskValid(rtk_portmask_t
*pPmask
)
1143 if(init_state
!= INIT_COMPLETED
)
1144 return RT_ERR_NOT_INIT
;
1147 return RT_ERR_NULL_POINTER
;
1149 if( (pPmask
->bits
[0] | halCtrl
->valid_portmask
) != halCtrl
->valid_portmask
)
1150 return RT_ERR_FAILED
;
1156 * rtk_switch_isPortMaskUtp
1158 * Check all ports in portmask are only UTP port
1160 * pPmask - logical port mask
1164 * RT_ERR_OK - Only UTP port in port mask
1165 * RT_ERR_FAILED - Not only UTP port in port mask
1166 * RT_ERR_NOT_INIT - Not Initialize
1167 * RT_ERR_NULL_POINTER - Null pointer
1171 rtk_api_ret_t
rtk_switch_isPortMaskUtp(rtk_portmask_t
*pPmask
)
1173 if(init_state
!= INIT_COMPLETED
)
1174 return RT_ERR_NOT_INIT
;
1177 return RT_ERR_NULL_POINTER
;
1179 if( (pPmask
->bits
[0] | halCtrl
->valid_utp_portmask
) != halCtrl
->valid_utp_portmask
)
1180 return RT_ERR_FAILED
;
1186 * rtk_switch_isPortMaskExt
1188 * Check all ports in portmask are only EXT port
1190 * pPmask - logical port mask
1194 * RT_ERR_OK - Only EXT port in port mask
1195 * RT_ERR_FAILED - Not only EXT port in port mask
1196 * RT_ERR_NOT_INIT - Not Initialize
1197 * RT_ERR_NULL_POINTER - Null pointer
1201 rtk_api_ret_t
rtk_switch_isPortMaskExt(rtk_portmask_t
*pPmask
)
1203 if(init_state
!= INIT_COMPLETED
)
1204 return RT_ERR_NOT_INIT
;
1207 return RT_ERR_NULL_POINTER
;
1209 if( (pPmask
->bits
[0] | halCtrl
->valid_ext_portmask
) != halCtrl
->valid_ext_portmask
)
1210 return RT_ERR_FAILED
;
1216 * rtk_switch_portmask_L2P_get
1218 * Get physicl portmask from logical portmask
1220 * pLogicalPmask - logical port mask
1222 * pPhysicalPortmask - physical port mask
1225 * RT_ERR_NOT_INIT - Not Initialize
1226 * RT_ERR_NULL_POINTER - Null pointer
1227 * RT_ERR_PORT_MASK - Error port mask
1231 rtk_api_ret_t
rtk_switch_portmask_L2P_get(rtk_portmask_t
*pLogicalPmask
, rtk_uint32
*pPhysicalPortmask
)
1233 rtk_uint32 log_port
, phy_port
;
1235 if(init_state
!= INIT_COMPLETED
)
1236 return RT_ERR_NOT_INIT
;
1238 if(NULL
== pLogicalPmask
)
1239 return RT_ERR_NULL_POINTER
;
1241 if(NULL
== pPhysicalPortmask
)
1242 return RT_ERR_NULL_POINTER
;
1244 if(rtk_switch_isPortMaskValid(pLogicalPmask
) != RT_ERR_OK
)
1245 return RT_ERR_PORT_MASK
;
1247 /* reset physical port mask */
1248 *pPhysicalPortmask
= 0;
1250 RTK_PORTMASK_SCAN((*pLogicalPmask
), log_port
)
1252 phy_port
= rtk_switch_port_L2P_get((rtk_port_t
)log_port
);
1253 *pPhysicalPortmask
|= (0x0001 << phy_port
);
1260 * rtk_switch_portmask_P2L_get
1262 * Get logical portmask from physical portmask
1264 * physicalPortmask - physical port mask
1266 * pLogicalPmask - logical port mask
1269 * RT_ERR_NOT_INIT - Not Initialize
1270 * RT_ERR_NULL_POINTER - Null pointer
1271 * RT_ERR_PORT_MASK - Error port mask
1275 rtk_api_ret_t
rtk_switch_portmask_P2L_get(rtk_uint32 physicalPortmask
, rtk_portmask_t
*pLogicalPmask
)
1277 rtk_uint32 log_port
, phy_port
;
1279 if(init_state
!= INIT_COMPLETED
)
1280 return RT_ERR_NOT_INIT
;
1282 if(NULL
== pLogicalPmask
)
1283 return RT_ERR_NULL_POINTER
;
1285 RTK_PORTMASK_CLEAR(*pLogicalPmask
);
1287 for(phy_port
= halCtrl
->min_phy_port
; phy_port
<= halCtrl
->max_phy_port
; phy_port
++)
1289 if(physicalPortmask
& (0x0001 << phy_port
))
1291 log_port
= rtk_switch_port_P2L_get(phy_port
);
1292 if(log_port
!= UNDEFINE_PORT
)
1294 RTK_PORTMASK_PORT_SET(*pLogicalPmask
, log_port
);
1303 * rtk_switch_phyPortMask_get
1305 * Get physical portmask
1311 * 0x00 - Not Initialize
1312 * Other value - Physical port mask
1316 rtk_uint32
rtk_switch_phyPortMask_get(void)
1318 if(init_state
!= INIT_COMPLETED
)
1319 return 0x00; /* No port in portmask */
1321 return (halCtrl
->phy_portmask
);
1325 * rtk_switch_logPortMask_get
1327 * Get Logical portmask
1334 * RT_ERR_NOT_INIT - Not Initialize
1335 * RT_ERR_NULL_POINTER - Null pointer
1339 rtk_api_ret_t
rtk_switch_logPortMask_get(rtk_portmask_t
*pPortmask
)
1341 if(init_state
!= INIT_COMPLETED
)
1342 return RT_ERR_FAILED
;
1344 if(NULL
== pPortmask
)
1345 return RT_ERR_NULL_POINTER
;
1347 pPortmask
->bits
[0] = halCtrl
->valid_portmask
;
1354 * Set chip to default configuration enviroment
1361 * RT_ERR_FAILED - Failed
1362 * RT_ERR_SMI - SMI access error
1364 * The API can set chip registers to default configuration for different release chip model.
1366 rtk_api_ret_t
rtk_switch_init(void)
1369 rtl8367c_rma_t rmaCfg
;
1370 switch_chip_t switchChip
;
1373 if((retVal
= rtk_switch_probe(&switchChip
)) != RT_ERR_OK
)
1376 /* Set initial state */
1378 if((retVal
= rtk_switch_initialState_set(INIT_COMPLETED
)) != RT_ERR_OK
)
1385 if((retVal
= _rtk_switch_init_8367c()) != RT_ERR_OK
)
1389 if((retVal
= _rtk_switch_init_8370b()) != RT_ERR_OK
)
1393 if((retVal
= _rtk_switch_init_8364b()) != RT_ERR_OK
)
1396 case CHIP_RTL8363SC_VB
:
1397 if((retVal
= _rtk_switch_init_8363sc_vb()) != RT_ERR_OK
)
1401 return RT_ERR_CHIP_NOT_FOUND
;
1404 /* Set Old max packet length to 16K */
1405 if((retVal
= rtl8367c_setAsicRegBits(RTL8367C_REG_MAX_LENGTH_LIMINT_IPG
, RTL8367C_MAX_LENTH_CTRL_MASK
, 3)) != RT_ERR_OK
)
1408 if((retVal
= rtl8367c_setAsicRegBits(RTL8367C_REG_MAX_LEN_RX_TX
, RTL8367C_MAX_LEN_RX_TX_MASK
, 3)) != RT_ERR_OK
)
1412 if((retVal
= rtl8367c_setAsicRegBits(RTL8367C_REG_ACL_ACCESS_MODE
, RTL8367C_ACL_ACCESS_MODE_MASK
, 1)) != RT_ERR_OK
)
1416 if((retVal
= rtk_rate_igrBandwidthCtrlRate_set(halCtrl
->hsg_logical_port
, RTL8367C_QOS_RATE_INPUT_MAX_HSG
, DISABLED
, ENABLED
)) != RT_ERR_OK
)
1419 if((retVal
= rtk_rate_egrBandwidthCtrlRate_set(halCtrl
->hsg_logical_port
, RTL8367C_QOS_RATE_INPUT_MAX_HSG
, ENABLED
)) != RT_ERR_OK
)
1422 if((retVal
= rtl8367c_setAsicReg(0x03fa, 0x0007)) != RT_ERR_OK
)
1425 /* Change unknown DA to per port setting */
1426 if((retVal
= rtl8367c_setAsicRegBits(RTL8367C_PORT_SECURIT_CTRL_REG
, RTL8367C_UNKNOWN_UNICAST_DA_BEHAVE_MASK
, 3)) != RT_ERR_OK
)
1429 /* LUT lookup OP = 1 */
1430 if ((retVal
= rtl8367c_setAsicLutIpLookupMethod(1))!=RT_ERR_OK
)
1434 rmaCfg
.portiso_leaky
= 0;
1435 rmaCfg
.vlan_leaky
= 0;
1436 rmaCfg
.keep_format
= 0;
1437 rmaCfg
.trap_priority
= 0;
1438 rmaCfg
.discard_storm_filter
= 0;
1439 rmaCfg
.operation
= 0;
1440 if ((retVal
= rtl8367c_setAsicRma(2, &rmaCfg
))!=RT_ERR_OK
)
1443 /* Enable TX Mirror isolation leaky */
1444 if ((retVal
= rtl8367c_setAsicPortMirrorIsolationTxLeaky(ENABLED
)) != RT_ERR_OK
)
1448 if((retVal
= rtl8367c_setAsicRegBit(RTL8367C_REG_IO_MISC_FUNC
, RTL8367C_INT_EN_OFFSET
, 1)) != RT_ERR_OK
)
1455 * rtk_switch_portMaxPktLen_set
1457 * Set Max packet length
1461 * cfgId - Configuration ID
1466 * RT_ERR_FAILED - Failed
1467 * RT_ERR_SMI - SMI access error
1468 * RT_ERR_INPUT - Error Input
1471 rtk_api_ret_t
rtk_switch_portMaxPktLen_set(rtk_port_t port
, rtk_switch_maxPktLen_linkSpeed_t speed
, rtk_uint32 cfgId
)
1473 rtk_api_ret_t retVal
;
1475 /* Check initialization state */
1476 RTK_CHK_INIT_STATE();
1478 /* Check Port Valid */
1479 RTK_CHK_PORT_VALID(port
);
1481 if(speed
>= MAXPKTLEN_LINK_SPEED_END
)
1482 return RT_ERR_INPUT
;
1484 if(cfgId
> MAXPKTLEN_CFG_ID_MAX
)
1485 return RT_ERR_INPUT
;
1487 if((retVal
= rtl8367c_setAsicMaxLength(rtk_switch_port_L2P_get(port
), (rtk_uint32
)speed
, cfgId
)) != RT_ERR_OK
)
1494 * rtk_switch_portMaxPktLen_get
1496 * Get Max packet length
1501 * pCfgId - Configuration ID
1504 * RT_ERR_FAILED - Failed
1505 * RT_ERR_SMI - SMI access error
1506 * RT_ERR_INPUT - Error Input
1509 rtk_api_ret_t
rtk_switch_portMaxPktLen_get(rtk_port_t port
, rtk_switch_maxPktLen_linkSpeed_t speed
, rtk_uint32
*pCfgId
)
1511 rtk_api_ret_t retVal
;
1513 /* Check initialization state */
1514 RTK_CHK_INIT_STATE();
1516 /* Check Port Valid */
1517 RTK_CHK_PORT_VALID(port
);
1519 if(speed
>= MAXPKTLEN_LINK_SPEED_END
)
1520 return RT_ERR_INPUT
;
1523 return RT_ERR_NULL_POINTER
;
1525 if((retVal
= rtl8367c_getAsicMaxLength(rtk_switch_port_L2P_get(port
), (rtk_uint32
)speed
, pCfgId
)) != RT_ERR_OK
)
1532 * rtk_switch_maxPktLenCfg_set
1534 * Set Max packet length configuration
1536 * cfgId - Configuration ID
1537 * pktLen - Max packet length
1542 * RT_ERR_FAILED - Failed
1543 * RT_ERR_SMI - SMI access error
1544 * RT_ERR_INPUT - Error Input
1547 rtk_api_ret_t
rtk_switch_maxPktLenCfg_set(rtk_uint32 cfgId
, rtk_uint32 pktLen
)
1549 rtk_api_ret_t retVal
;
1551 /* Check initialization state */
1552 RTK_CHK_INIT_STATE();
1554 if(cfgId
> MAXPKTLEN_CFG_ID_MAX
)
1555 return RT_ERR_INPUT
;
1557 if(pktLen
> RTK_SWITCH_MAX_PKTLEN
)
1558 return RT_ERR_INPUT
;
1560 if((retVal
= rtl8367c_setAsicMaxLengthCfg(cfgId
, pktLen
)) != RT_ERR_OK
)
1567 * rtk_switch_maxPktLenCfg_get
1569 * Get Max packet length configuration
1571 * cfgId - Configuration ID
1572 * pPktLen - Max packet length
1577 * RT_ERR_FAILED - Failed
1578 * RT_ERR_SMI - SMI access error
1579 * RT_ERR_INPUT - Error Input
1582 rtk_api_ret_t
rtk_switch_maxPktLenCfg_get(rtk_uint32 cfgId
, rtk_uint32
*pPktLen
)
1584 rtk_api_ret_t retVal
;
1586 /* Check initialization state */
1587 RTK_CHK_INIT_STATE();
1589 if(cfgId
> MAXPKTLEN_CFG_ID_MAX
)
1590 return RT_ERR_INPUT
;
1593 return RT_ERR_NULL_POINTER
;
1595 if((retVal
= rtl8367c_getAsicMaxLengthCfg(cfgId
, pPktLen
)) != RT_ERR_OK
)
1602 * rtk_switch_greenEthernet_set
1604 * Set all Ports Green Ethernet state.
1606 * enable - Green Ethernet state.
1611 * RT_ERR_FAILED - Failed
1612 * RT_ERR_SMI - SMI access error
1613 * RT_ERR_ENABLE - Invalid enable input.
1615 * This API can set all Ports Green Ethernet state.
1616 * The configuration is as following:
1620 rtk_api_ret_t
rtk_switch_greenEthernet_set(rtk_enable_t enable
)
1622 rtk_api_ret_t retVal
;
1625 /* Check initialization state */
1626 RTK_CHK_INIT_STATE();
1628 RTK_SCAN_ALL_LOG_PORT(port
)
1630 if(rtk_switch_isUtpPort(port
) == RT_ERR_OK
)
1632 if ((retVal
= rtl8367c_setAsicPowerSaving(rtk_switch_port_L2P_get(port
),enable
))!=RT_ERR_OK
)
1635 if ((retVal
= rtl8367c_setAsicGreenEthernet(rtk_switch_port_L2P_get(port
), enable
))!=RT_ERR_OK
)
1644 * rtk_switch_greenEthernet_get
1646 * Get all Ports Green Ethernet state.
1650 * pEnable - Green Ethernet state.
1653 * RT_ERR_FAILED - Failed
1654 * RT_ERR_SMI - SMI access error
1656 * This API can get Green Ethernet state.
1658 rtk_api_ret_t
rtk_switch_greenEthernet_get(rtk_enable_t
*pEnable
)
1660 rtk_api_ret_t retVal
;
1664 /* Check initialization state */
1665 RTK_CHK_INIT_STATE();
1667 RTK_SCAN_ALL_LOG_PORT(port
)
1669 if(rtk_switch_isUtpPort(port
) == RT_ERR_OK
)
1671 if ((retVal
= rtl8367c_getAsicPowerSaving(rtk_switch_port_L2P_get(port
), &state
))!=RT_ERR_OK
)
1674 if(state
== DISABLED
)
1676 *pEnable
= DISABLED
;
1680 if ((retVal
= rtl8367c_getAsicGreenEthernet(rtk_switch_port_L2P_get(port
), &state
))!=RT_ERR_OK
)
1683 if(state
== DISABLED
)
1685 *pEnable
= DISABLED
;
1696 * rtk_switch_maxLogicalPort_get
1698 * Get Max logical port ID
1706 * This API can get max logical port
1708 rtk_port_t
rtk_switch_maxLogicalPort_get(void)
1710 rtk_port_t port
, maxLogicalPort
= 0;
1712 /* Check initialization state */
1713 if(rtk_switch_initialState_get() != INIT_COMPLETED
)
1715 return UNDEFINE_PORT
;
1718 for(port
= 0; port
< RTK_SWITCH_PORT_NUM
; port
++)
1720 if( (halCtrl
->log_port_type
[port
] == UTP_PORT
) || (halCtrl
->log_port_type
[port
] == EXT_PORT
) )
1721 maxLogicalPort
= port
;
1724 return maxLogicalPort
;
1728 * rtk_switch_maxMeterId_get
1736 * 0x00 - Not Initialize
1737 * Other value - Max Meter ID
1741 rtk_uint32
rtk_switch_maxMeterId_get(void)
1743 if(init_state
!= INIT_COMPLETED
)
1746 return (halCtrl
->max_meter_id
);
1750 * rtk_switch_maxLutAddrNumber_get
1752 * Get Max LUT Address number
1758 * 0x00 - Not Initialize
1759 * Other value - Max LUT Address number
1763 rtk_uint32
rtk_switch_maxLutAddrNumber_get(void)
1765 if(init_state
!= INIT_COMPLETED
)
1768 return (halCtrl
->max_lut_addr_num
);
1772 * rtk_switch_isValidTrunkGrpId
1774 * Check if trunk group is valid or not
1780 * RT_ERR_OK - Trunk Group ID is valid
1781 * RT_ERR_LA_TRUNK_ID - Trunk Group ID is not valid
1785 rtk_uint32
rtk_switch_isValidTrunkGrpId(rtk_uint32 grpId
)
1787 if(init_state
!= INIT_COMPLETED
)
1790 if( (halCtrl
->trunk_group_mask
& (0x01 << grpId
) ) != 0)
1793 return RT_ERR_LA_TRUNK_ID
;