2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * SPDX-License-Identifier: (GPL-2.0-only OR MIT)
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
12 #include "mt7622.dtsi"
13 #include "mt6380.dtsi"
16 model = "Bananapi BPI-R64";
17 compatible = "bananapi,bpi-r64-rootdisk", "mediatek,mt7622";
24 stdout-path = "serial0:115200n8";
25 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=/dev/mmcblk0p7 rootfstype=squashfs,f2fs";
30 proc-supply = <&mt6380_vcpu_reg>;
31 sram-supply = <&mt6380_vm_reg>;
35 proc-supply = <&mt6380_vcpu_reg>;
36 sram-supply = <&mt6380_vm_reg>;
41 compatible = "gpio-keys";
46 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
51 linux,code = <KEY_WPS_BUTTON>;
52 gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
57 compatible = "gpio-leds";
60 label = "bpi-r64:pio:green";
61 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
65 label = "bpi-r64:pio:red";
66 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
71 reg = <0 0x40000000 0 0x40000000>;
74 reg_1p8v: regulator-1p8v {
75 compatible = "regulator-fixed";
76 regulator-name = "fixed-1.8V";
77 regulator-min-microvolt = <1800000>;
78 regulator-max-microvolt = <1800000>;
82 reg_3p3v: regulator-3p3v {
83 compatible = "regulator-fixed";
84 regulator-name = "fixed-3.3V";
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
91 reg_5v: regulator-5v {
92 compatible = "regulator-fixed";
93 regulator-name = "fixed-5V";
94 regulator-min-microvolt = <5000000>;
95 regulator-max-microvolt = <5000000>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&irrx_pins>;
118 compatible = "mediatek,eth-mac";
120 phy-mode = "2500base-x";
130 compatible = "mediatek,eth-mac";
142 #address-cells = <1>;
146 compatible = "mediatek,mt7531";
148 reset-gpios = <&pio 54 0>;
151 #address-cells = <1>;
183 phy-mode = "2500base-x";
198 pinctrl-names = "default";
199 pinctrl-0 = <&i2c1_pins>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&i2c2_pins>;
210 pinctrl-names = "default", "state_uhs";
211 pinctrl-0 = <&emmc_pins_default>;
212 pinctrl-1 = <&emmc_pins_uhs>;
215 max-frequency = <50000000>;
218 vmmc-supply = <®_3p3v>;
219 vqmmc-supply = <®_1p8v>;
220 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
221 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
226 pinctrl-names = "default", "state_uhs";
227 pinctrl-0 = <&sd0_pins_default>;
228 pinctrl-1 = <&sd0_pins_uhs>;
231 max-frequency = <50000000>;
234 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
235 vmmc-supply = <®_3p3v>;
236 vqmmc-supply = <®_3p3v>;
237 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
238 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
242 pinctrl-names = "default";
243 pinctrl-0 = <¶llel_nand_pins>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&spi_nor_pins>;
253 compatible = "jedec,spi-nor";
259 pinctrl-names = "default";
260 pinctrl-0 = <&pcie0_pins>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pcie1_pins>;
271 /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
272 * SATA functions. i.e. output-high: PCIe, output-low: SATA
276 gpios = <90 GPIO_ACTIVE_HIGH>;
280 /* eMMC is shared pin with parallel NAND */
281 emmc_pins_default: emmc-pins-default {
283 function = "emmc", "emmc_rst";
287 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
288 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
289 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
292 pins = "NDL0", "NDL1", "NDL2",
293 "NDL3", "NDL4", "NDL5",
294 "NDL6", "NDL7", "NRB";
305 emmc_pins_uhs: emmc-pins-uhs {
312 pins = "NDL0", "NDL1", "NDL2",
313 "NDL3", "NDL4", "NDL5",
314 "NDL6", "NDL7", "NRB";
316 drive-strength = <4>;
322 drive-strength = <4>;
330 groups = "mdc_mdio", "rgmii_via_gmac2";
334 i2c1_pins: i2c1-pins {
341 i2c2_pins: i2c2-pins {
348 i2s1_pins: i2s1-pins {
351 groups = "i2s_out_mclk_bclk_ws",
357 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
358 "I2S_WS", "I2S_MCLK";
359 drive-strength = <12>;
364 irrx_pins: irrx-pins {
371 irtx_pins: irtx-pins {
378 /* Parallel nand is shared pin with eMMC */
379 parallel_nand_pins: parallel-nand-pins {
386 pcie0_pins: pcie0-pins {
389 groups = "pcie0_pad_perst",
395 pcie1_pins: pcie1-pins {
398 groups = "pcie1_pad_perst",
404 pmic_bus_pins: pmic-bus-pins {
411 pwm7_pins: pwm1-2-pins {
414 groups = "pwm_ch7_2";
418 wled_pins: wled-pins {
425 sd0_pins_default: sd0-pins-default {
431 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
432 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
433 * DAT2, DAT3, CMD, CLK for SD respectively.
436 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
437 "I2S2_IN","I2S4_OUT";
439 drive-strength = <8>;
444 drive-strength = <12>;
453 sd0_pins_uhs: sd0-pins-uhs {
460 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
461 "I2S2_IN","I2S4_OUT";
472 /* Serial NAND is shared pin with SPI-NOR */
473 serial_nand_pins: serial-nand-pins {
480 spic0_pins: spic0-pins {
487 spic1_pins: spic1-pins {
494 /* SPI-NOR is shared pin with serial NAND */
495 spi_nor_pins: spi-nor-pins {
502 /* serial NAND is shared pin with SPI-NOR */
503 serial_nand_pins: serial-nand-pins {
510 uart0_pins: uart0-pins {
513 groups = "uart0_0_tx_rx" ;
517 uart2_pins: uart2-pins {
520 groups = "uart2_1_tx_rx" ;
524 watchdog_pins: watchdog-pins {
526 function = "watchdog";
533 pinctrl-names = "default";
534 pinctrl-0 = <&pwm7_pins>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&pmic_bus_pins>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&spic0_pins>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&spic1_pins>;
566 vusb33-supply = <®_3p3v>;
567 vbus-supply = <®_5v>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&uart0_pins>;
582 pinctrl-names = "default";
583 pinctrl-0 = <&uart2_pins>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&watchdog_pins>;