mediatek: add support for rtl8367c
[openwrt/openwrt.git] / target / linux / mediatek / files-5.4 / drivers / net / phy / rtk / rtl8367c / include / rtl8367c_asicdrv.h
1 /*
2 * Copyright (C) 2013 Realtek Semiconductor Corp.
3 * All Rights Reserved.
4 *
5 * Unless you and Realtek execute a separate written software license
6 * agreement governing use of this software, this software is licensed
7 * to you under the terms of the GNU General Public License version 2,
8 * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
9 *
10 * $Revision: 76306 $
11 * $Date: 2017-03-08 15:13:58 +0800 (¶g¤T, 08 ¤T¤ë 2017) $
12 *
13 * Purpose : RTL8367C switch high-level API for RTL8367C
14 * Feature :
15 *
16 */
17
18
19 #ifndef _RTL8367C_ASICDRV_H_
20 #define _RTL8367C_ASICDRV_H_
21
22 #include <rtk_types.h>
23 #include <rtk_error.h>
24 #include <rtl8367c_reg.h>
25 #include <rtl8367c_base.h>
26
27 #define RTL8367C_REGBITLENGTH 16
28 #define RTL8367C_REGDATAMAX 0xFFFF
29
30 #define RTL8367C_VIDMAX 0xFFF
31 #define RTL8367C_EVIDMAX 0x1FFF
32 #define RTL8367C_CVIDXNO 32
33 #define RTL8367C_CVIDXMAX (RTL8367C_CVIDXNO-1)
34
35 #define RTL8367C_PRIMAX 7
36 #define RTL8367C_DSCPMAX 63
37
38 #define RTL8367C_PORTNO 11
39 #define RTL8367C_PORTIDMAX (RTL8367C_PORTNO-1)
40 #define RTL8367C_PMSKMAX ((1<<(RTL8367C_PORTNO))-1)
41 #define RTL8367C_PORTMASK 0x7FF
42
43 #define RTL8367C_PHYNO 5
44 #define RTL8367C_PHYIDMAX (RTL8367C_PHYNO-1)
45
46 #define RTL8367C_SVIDXNO 64
47 #define RTL8367C_SVIDXMAX (RTL8367C_SVIDXNO-1)
48 #define RTL8367C_MSTIMAX 15
49
50 #define RTL8367C_METERNO 64
51 #define RTL8367C_METERMAX (RTL8367C_METERNO-1)
52 #define RTL8367C_METERBUCKETSIZEMAX 0xFFFF
53
54 #define RTL8367C_QUEUENO 8
55 #define RTL8367C_QIDMAX (RTL8367C_QUEUENO-1)
56
57 #define RTL8367C_PHY_BUSY_CHECK_COUNTER 1000
58
59 #define RTL8367C_QOS_GRANULARTY_MAX 0x7FFFF
60 #define RTL8367C_QOS_GRANULARTY_LSB_MASK 0xFFFF
61 #define RTL8367C_QOS_GRANULARTY_LSB_OFFSET 0
62 #define RTL8367C_QOS_GRANULARTY_MSB_MASK 0x70000
63 #define RTL8367C_QOS_GRANULARTY_MSB_OFFSET 16
64
65 #define RTL8367C_QOS_GRANULARTY_UNIT_KBPS 8
66
67 #define RTL8367C_QOS_RATE_INPUT_MAX (0x1FFFF * 8)
68 #define RTL8367C_QOS_RATE_INPUT_MAX_HSG (0x7FFFF * 8)
69 #define RTL8367C_QOS_RATE_INPUT_MIN 8
70 #define RTL8367C_QOS_PPS_INPUT_MAX (0x7FFFF)
71 #define RTL8367C_QOS_PPS_INPUT_MIN 1
72
73 #define RTL8367C_QUEUE_MASK 0xFF
74
75 #define RTL8367C_EFIDMAX 0x7
76 #define RTL8367C_FIDMAX 0xF
77
78 #define RTL8367C_EAV_SECONDMAX 0xFFFFFFFF
79 #define RTL8367C_EAV_NANOSECONDMAX 0x3B9AC9FF
80
81
82 /* the above macro is generated by genDotH */
83 #define RTL8367C_VALID_REG_NO 3869
84
85 /*=======================================================================
86 * Enum
87 *========================================================================*/
88 enum RTL8367C_TABLE_ACCESS_OP
89 {
90 TB_OP_READ = 0,
91 TB_OP_WRITE
92 };
93
94 enum RTL8367C_TABLE_ACCESS_TARGET
95 {
96 TB_TARGET_ACLRULE = 1,
97 TB_TARGET_ACLACT,
98 TB_TARGET_CVLAN,
99 TB_TARGET_L2,
100 TB_TARGET_IGMP_GROUP
101 };
102
103 #define RTL8367C_TABLE_ACCESS_REG_DATA(op, target) ((op << 3) | target)
104
105 /*=======================================================================
106 * Structures
107 *========================================================================*/
108
109
110 #ifdef __cplusplus
111 extern "C" {
112 #endif
113 extern ret_t rtl8367c_setAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 value);
114 extern ret_t rtl8367c_getAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 *pValue);
115
116 extern ret_t rtl8367c_setAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 value);
117 extern ret_t rtl8367c_getAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 *pValue);
118
119 extern ret_t rtl8367c_setAsicReg(rtk_uint32 reg, rtk_uint32 value);
120 extern ret_t rtl8367c_getAsicReg(rtk_uint32 reg, rtk_uint32 *pValue);
121
122 #ifdef __cplusplus
123 }
124 #endif
125
126
127
128 #endif /*#ifndef _RTL8367C_ASICDRV_H_*/
129