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mediatek: add support for rtl8367c
[openwrt/openwrt.git] / target / linux / mediatek / files-5.4 / drivers / net / phy / rtk / rtl8367c / rtk_hal.c
1 #include <linux/kernel.h>
2 #include <linux/delay.h>
3 #include "./include/rtk_switch.h"
4 #include "./include/vlan.h"
5 #include "./include/port.h"
6 #include "./include/rate.h"
7 #include "./include/rtk_hal.h"
8 #include "./include/l2.h"
9 #include "./include/stat.h"
10 #include "./include/igmp.h"
11 #include "./include/trap.h"
12 #include "./include/leaky.h"
13 #include "./include/mirror.h"
14 #include "./include/rtl8367c_asicdrv_port.h"
15 #include "./include/rtl8367c_asicdrv_mib.h"
16 #include "./include/smi.h"
17 #include "./include/qos.h"
18 #include "./include/trunk.h"
19
20 void rtk_hal_switch_init(void)
21 {
22 if(rtk_switch_init() != 0)
23 printk("rtk_switch_init failed\n");
24 mdelay(500);
25 /*vlan init */
26 if (rtk_vlan_init() != 0)
27 printk("rtk_vlan_init failed\n");
28 }
29
30 void rtk_hal_dump_full_mib(void)
31 {
32 rtk_port_t port;
33 rtk_stat_counter_t Cntr;
34 rtk_stat_port_type_t cntr_idx;
35
36 for (port = UTP_PORT0; port < (UTP_PORT0 + 5); port++) {
37 printk("\nPort%d\n", port);
38 for (cntr_idx = STAT_IfInOctets; cntr_idx < STAT_PORT_CNTR_END; cntr_idx ++) {
39 rtk_stat_port_get(port, cntr_idx, &Cntr);
40 printk("%8llu ", Cntr);
41 if (((cntr_idx%10) == 9))
42 printk("\n");
43 }
44 }
45
46 for (port = EXT_PORT0; port < (EXT_PORT0 + 2); port++) {
47 printk("\nPort%d\n", port);
48 for (cntr_idx = STAT_IfInOctets; cntr_idx < STAT_PORT_CNTR_END; cntr_idx ++) {
49 rtk_stat_port_get(port, cntr_idx, &Cntr);
50 printk("%8llu ", Cntr);
51 if (((cntr_idx%10) == 9))
52 printk("\n");
53 }
54 }
55 rtk_stat_global_reset();
56 }
57 void rtk_dump_mib_type(rtk_stat_port_type_t cntr_idx)
58 {
59 rtk_port_t port;
60 rtk_stat_counter_t Cntr;
61
62 for (port = UTP_PORT0; port < (UTP_PORT0 + 5); port++) {
63 rtk_stat_port_get(port, cntr_idx, &Cntr);
64 printk("%8llu", Cntr);
65 }
66 for (port = EXT_PORT0; port < (EXT_PORT0 + 2); port++) {
67 rtk_stat_port_get(port, cntr_idx, &Cntr);
68 printk("%8llu", Cntr);
69 }
70 printk("\n");
71 }
72
73 void rtk_hal_dump_mib(void)
74 {
75
76 printk("==================%8s%8s%8s%8s%8s%8s%8s\n", "Port0", "Port1",
77 "Port2", "Port3", "Port4", "Port16", "Port17");
78 /* Get TX Unicast Pkts */
79 printk("TX Unicast Pkts :");
80 rtk_dump_mib_type(STAT_IfOutUcastPkts);
81 /* Get TX Multicast Pkts */
82 printk("TX Multicast Pkts:");
83 rtk_dump_mib_type(STAT_IfOutMulticastPkts);
84 /* Get TX BroadCast Pkts */
85 printk("TX BroadCast Pkts:");
86 rtk_dump_mib_type(STAT_IfOutBroadcastPkts);
87 /* Get TX Collisions */
88 /* Get TX Puase Frames */
89 printk("TX Pause Frames :");
90 rtk_dump_mib_type(STAT_Dot3OutPauseFrames);
91 /* Get TX Drop Events */
92 /* Get RX Unicast Pkts */
93 printk("RX Unicast Pkts :");
94 rtk_dump_mib_type(STAT_IfInUcastPkts);
95 /* Get RX Multicast Pkts */
96 printk("RX Multicast Pkts:");
97 rtk_dump_mib_type(STAT_IfInMulticastPkts);
98 /* Get RX Broadcast Pkts */
99 printk("RX Broadcast Pkts:");
100 rtk_dump_mib_type(STAT_IfInBroadcastPkts);
101 /* Get RX FCS Erros */
102 printk("RX FCS Errors :");
103 rtk_dump_mib_type(STAT_Dot3StatsFCSErrors);
104 /* Get RX Undersize Pkts */
105 printk("RX Undersize Pkts:");
106 rtk_dump_mib_type(STAT_EtherStatsUnderSizePkts);
107 /* Get RX Discard Pkts */
108 printk("RX Discard Pkts :");
109 rtk_dump_mib_type(STAT_Dot1dTpPortInDiscards);
110 /* Get RX Fragments */
111 printk("RX Fragments :");
112 rtk_dump_mib_type(STAT_EtherStatsFragments);
113 /* Get RX Oversize Pkts */
114 printk("RX Oversize Pkts :");
115 rtk_dump_mib_type(STAT_EtherOversizeStats);
116 /* Get RX Jabbers */
117 printk("RX Jabbers :");
118 rtk_dump_mib_type(STAT_EtherStatsJabbers);
119 /* Get RX Pause Frames */
120 printk("RX Pause Frames :");
121 rtk_dump_mib_type(STAT_Dot3InPauseFrames);
122 /* clear MIB */
123 rtk_stat_global_reset();
124 }
125 EXPORT_SYMBOL(rtk_hal_dump_mib);
126
127 int rtk_hal_dump_vlan(void)
128 {
129 rtk_vlan_cfg_t vlan;
130 int i;
131
132 printk("vid portmap\n");
133 for (i = 0; i < RTK_SW_VID_RANGE; i++) {
134 rtk_vlan_get(i, &vlan);
135 printk("%3d ", i);
136 printk("%c",
137 RTK_PORTMASK_IS_PORT_SET(vlan.mbr,
138 UTP_PORT0) ? '1' : '-');
139 printk("%c",
140 RTK_PORTMASK_IS_PORT_SET(vlan.mbr,
141 UTP_PORT1) ? '1' : '-');
142 printk("%c",
143 RTK_PORTMASK_IS_PORT_SET(vlan.mbr,
144 UTP_PORT2) ? '1' : '-');
145 printk("%c",
146 RTK_PORTMASK_IS_PORT_SET(vlan.mbr,
147 UTP_PORT3) ? '1' : '-');
148 printk("%c",
149 RTK_PORTMASK_IS_PORT_SET(vlan.mbr,
150 UTP_PORT4) ? '1' : '-');
151 printk("%c",
152 RTK_PORTMASK_IS_PORT_SET(vlan.mbr,
153 EXT_PORT0) ? '1' : '-');
154 printk("%c",
155 RTK_PORTMASK_IS_PORT_SET(vlan.mbr,
156 EXT_PORT1) ? '1' : '-');
157 printk("\n");
158 }
159 return 0;
160 }
161
162 void rtk_hal_clear_vlan(void)
163 {
164 rtk_api_ret_t ret;
165
166 ret = rtk_vlan_reset();
167 if (ret != RT_ERR_OK)
168 printk("rtk_vlan_reset failed\n");
169 }
170
171 int rtk_hal_set_vlan(struct ra_switch_ioctl_data *data)
172 {
173 rtk_vlan_cfg_t vlan;
174 rtk_api_ret_t ret;
175 int i;
176
177 /* clear vlan entry first */
178 memset(&vlan, 0x00, sizeof(rtk_vlan_cfg_t));
179 RTK_PORTMASK_CLEAR(vlan.mbr);
180 RTK_PORTMASK_CLEAR(vlan.untag);
181 rtk_vlan_set(data->vid, &vlan);
182
183 memset(&vlan, 0x00, sizeof(rtk_vlan_cfg_t));
184 for (i = 0; i < 5; i++) {
185 if (data->port_map & (1 << i)) {
186 RTK_PORTMASK_PORT_SET(vlan.mbr, i);
187 RTK_PORTMASK_PORT_SET(vlan.untag, i);
188 rtk_vlan_portPvid_set(i, data->vid, 0);
189 }
190 }
191 for (i = 0; i < 2; i++) {
192 if (data->port_map & (1 << (i + 5))) {
193 RTK_PORTMASK_PORT_SET(vlan.mbr, (i + EXT_PORT0));
194 RTK_PORTMASK_PORT_SET(vlan.untag, (i + EXT_PORT0));
195 rtk_vlan_portPvid_set((i + EXT_PORT0), data->vid, 0);
196 }
197 }
198 vlan.ivl_en = 1;
199 ret = rtk_vlan_set(data->vid, &vlan);
200
201 return 0;
202 }
203
204 void rtk_hal_vlan_portpvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority)
205 {
206 rtk_vlan_portPvid_set(port, pvid, priority);
207 }
208
209 int rtk_hal_set_ingress_rate(struct ra_switch_ioctl_data *data)
210 {
211 rtk_api_ret_t ret;
212
213 if (data->on_off == 1)
214 ret =
215 rtk_rate_igrBandwidthCtrlRate_set(data->port, data->bw, 0,
216 1);
217 else
218 ret =
219 rtk_rate_igrBandwidthCtrlRate_set(data->port, 1048568, 0,
220 1);
221
222 return ret;
223 }
224
225 int rtk_hal_set_egress_rate(struct ra_switch_ioctl_data *data)
226 {
227 rtk_api_ret_t ret;
228
229 if (data->on_off == 1)
230 ret =
231 rtk_rate_egrBandwidthCtrlRate_set(data->port, data->bw, 1);
232 else
233 ret = rtk_rate_egrBandwidthCtrlRate_set(data->port, 1048568, 1);
234
235 return ret;
236 }
237
238 void rtk_hal_dump_table(void)
239 {
240 rtk_uint32 i;
241 rtk_uint32 address = 0;
242 rtk_l2_ucastAddr_t l2_data;
243 rtk_l2_ipMcastAddr_t ipMcastAddr;
244
245 printk("hash port(0:17) fid vid mac-address\n");
246 while (1) {
247 if (rtk_l2_addr_next_get(READMETHOD_NEXT_L2UC, UTP_PORT0, &address, &l2_data) != RT_ERR_OK) {
248 break;
249 } else {
250 printk("%03x ", l2_data.address);
251 for (i = 0; i < 5; i++)
252 if ( l2_data.port == i)
253 printk("1");
254 else
255 printk("-");
256 for (i = 16; i < 18; i++)
257 if ( l2_data.port == i)
258 printk("1");
259 else
260 printk("-");
261
262 printk(" %2d", l2_data.fid);
263 printk(" %4d", l2_data.cvid);
264 printk(" %02x%02x%02x%02x%02x%02x\n", l2_data.mac.octet[0],
265 l2_data.mac.octet[1], l2_data.mac.octet[2], l2_data.mac.octet[3],
266 l2_data.mac.octet[4], l2_data.mac.octet[5]);
267 address ++;
268 }
269 }
270
271 address = 0;
272 while (1) {
273 if (rtk_l2_ipMcastAddr_next_get(&address, &ipMcastAddr) != RT_ERR_OK) {
274 break;
275 } else {
276 printk("%03x ", ipMcastAddr.address);
277 for (i = 0; i < 5; i++)
278 printk("%c", RTK_PORTMASK_IS_PORT_SET(ipMcastAddr.portmask, i) ? '1' : '-');
279 for (i = 16; i < 18; i++)
280 printk("%c", RTK_PORTMASK_IS_PORT_SET(ipMcastAddr.portmask, i) ? '1' : '-');
281 printk(" ");
282 printk("01005E%06x\n", (ipMcastAddr.dip & 0xefffff));
283 address ++;
284 }
285 }
286 }
287
288 void rtk_hal_clear_table(void)
289 {
290 rtk_api_ret_t ret;
291
292 ret = rtk_l2_table_clear();
293 if (ret != RT_ERR_OK)
294 printk("rtk_l2_table_clear failed\n");
295 }
296
297 void rtk_hal_add_table(struct ra_switch_ioctl_data *data)
298 {
299 rtk_api_ret_t ret;
300 rtk_l2_ucastAddr_t l2_entry;
301 rtk_mac_t mac;
302
303 mac.octet[0] =data->mac[0];
304 mac.octet[1] =data->mac[1];
305 mac.octet[2] =data->mac[2];
306 mac.octet[3] =data->mac[3];
307 mac.octet[4] =data->mac[4];
308 mac.octet[5] =data->mac[5];
309
310 memset(&l2_entry, 0x00, sizeof(rtk_l2_ucastAddr_t));
311 l2_entry.port = data->port;
312 l2_entry.ivl = 1;
313 l2_entry.cvid = data->vid;
314 l2_entry.fid = 0;
315 l2_entry.efid = 0;
316 l2_entry.is_static = 1;
317 ret = rtk_l2_addr_add(&mac, &l2_entry);
318 if (ret != RT_ERR_OK)
319 printk("rtk_hal_add_table failed\n");
320 }
321
322 void rtk_hal_del_table(struct ra_switch_ioctl_data *data)
323 {
324 rtk_api_ret_t ret;
325 rtk_l2_ucastAddr_t l2_entry;
326 rtk_mac_t mac;
327
328 mac.octet[0] =data->mac[0];
329 mac.octet[1] =data->mac[1];
330 mac.octet[2] =data->mac[2];
331 mac.octet[3] =data->mac[3];
332 mac.octet[4] =data->mac[4];
333 mac.octet[5] =data->mac[5];
334
335 memset(&l2_entry, 0x00, sizeof(rtk_l2_ucastAddr_t));
336 l2_entry.port = data->port;
337 l2_entry.ivl = 1;
338 l2_entry.cvid = data->vid;
339 l2_entry.fid = 0;
340 l2_entry.efid = 0;
341 ret = rtk_l2_addr_del(&mac, &l2_entry);
342 if (ret != RT_ERR_OK)
343 printk("rtk_hal_add_table failed\n");
344 }
345 void rtk_hal_get_phy_status(struct ra_switch_ioctl_data *data)
346 {
347 rtk_port_linkStatus_t linkStatus;
348 rtk_port_speed_t speed;
349 rtk_port_duplex_t duplex;
350
351 rtk_port_phyStatus_get(data->port, &linkStatus, &speed, &duplex);
352 printk("Port%d Status:\n", data->port);
353 if (linkStatus == 1) {
354 printk("Link Up");
355 if (speed == 0)
356 printk(" 10M");
357 else if (speed == 1)
358 printk(" 100M");
359 else if (speed == 2)
360 printk(" 1000M");
361 if (duplex == 0)
362 printk(" Half Duplex\n");
363 else
364 printk(" Full Duplex\n");
365 } else
366 printk("Link Down\n");
367
368 }
369
370 void rtk_hal_set_port_mirror(struct ra_switch_ioctl_data *data)
371 {
372 rtk_portmask_t rx_portmask;
373 rtk_portmask_t tx_portmask;
374 rtk_api_ret_t ret;
375 int i;
376
377 rtk_mirror_portIso_set(ENABLED);
378 RTK_PORTMASK_CLEAR(rx_portmask);
379 RTK_PORTMASK_CLEAR(tx_portmask);
380 for (i = 0; i < 5; i++)
381 if (data->rx_port_map & (1 << i))
382 RTK_PORTMASK_PORT_SET(rx_portmask, i);
383 for (i = 0; i < 2; i++)
384 if (data->rx_port_map & (1 << (i + 5)))
385 RTK_PORTMASK_PORT_SET(rx_portmask, (i + EXT_PORT0));
386
387 RTK_PORTMASK_CLEAR(tx_portmask);
388 for (i = 0; i < 5; i++)
389 if (data->tx_port_map & (1 << i))
390 RTK_PORTMASK_PORT_SET(tx_portmask, i);
391 for (i = 0; i < 2; i++)
392 if (data->tx_port_map & (1 << (i + 5)))
393 RTK_PORTMASK_PORT_SET(tx_portmask, (i + EXT_PORT0));
394
395 ret = rtk_mirror_portBased_set(data->port, &rx_portmask, &tx_portmask);
396 if (!ret)
397 printk("rtk_mirror_portBased_set success\n");
398 }
399
400 void rtk_hal_read_reg(struct ra_switch_ioctl_data *data)
401 {
402 ret_t retVal;
403
404 retVal = smi_read(data->reg_addr, &data->reg_val);
405 if(retVal != RT_ERR_OK)
406 printk("switch reg read failed\n");
407 else
408 printk("reg0x%x = 0x%x\n", data->reg_addr, data->reg_val);
409 }
410
411 void rtk_hal_write_reg(struct ra_switch_ioctl_data *data)
412 {
413 ret_t retVal;
414
415 retVal = smi_write(data->reg_addr, data->reg_val);
416 if(retVal != RT_ERR_OK)
417 printk("switch reg write failed\n");
418 else
419 printk("write switch reg0x%x 0x%x success\n", data->reg_addr, data->reg_val);
420 }
421
422 void rtk_hal_get_phy_reg(struct ra_switch_ioctl_data *data)
423 {
424 ret_t retVal;
425 rtk_port_phy_data_t Data;
426
427 retVal = rtk_port_phyReg_get(data->port, data->reg_addr, &Data);
428 if (retVal == RT_ERR_OK)
429 printk("Get: phy[%d].reg[%d] = 0x%04x\n", data->port, data->reg_addr, Data);
430 else
431 printk("read phy reg failed\n");
432 }
433
434 void rtk_hal_set_phy_reg(struct ra_switch_ioctl_data *data)
435 {
436 ret_t retVal;
437
438 retVal = rtk_port_phyReg_set(data->port, data->reg_addr, data->reg_val);
439 if (retVal == RT_ERR_OK)
440 printk("Set: phy[%d].reg[%d] = 0x%04x\n", data->port, data->reg_addr, data->reg_val);
441 else
442 printk("write phy reg failed\n");
443 }
444 void rtk_hal_qos_en(struct ra_switch_ioctl_data *data)
445 {
446
447 if (data->on_off == 1) {
448 if (rtk_qos_init(8) != 0)
449 printk("rtk_qos_init(8) failed\n");
450 }
451 else {
452 if (rtk_qos_init(1) != 0)
453 printk("rtk_qos_init(1) failed\n");
454 }
455 }
456
457 void rtk_hal_qos_set_table2type(struct ra_switch_ioctl_data *data)
458 {
459 rtk_api_ret_t ret;
460 rtk_priority_select_t PriDec;
461
462 /* write all pri to 0 */
463 PriDec.port_pri = 0;
464 PriDec.dot1q_pri = 0;
465 PriDec.acl_pri = 0;
466 PriDec.cvlan_pri = 0;
467 PriDec.svlan_pri = 0;
468 PriDec.dscp_pri = 0;
469 PriDec.dmac_pri = 0;
470 PriDec.smac_pri = 0;
471
472 if (data->qos_type == 0)
473 PriDec.port_pri = 1;
474 else if (data->qos_type == 1)
475 PriDec.dot1q_pri = 1;
476 else if (data->qos_type == 2)
477 PriDec.acl_pri = 1;
478 else if (data->qos_type == 3)
479 PriDec.dscp_pri = 1;
480 else if (data->qos_type == 4)
481 PriDec.cvlan_pri = 1;
482 else if (data->qos_type == 5)
483 PriDec.svlan_pri = 1;
484 else if (data->qos_type == 6)
485 PriDec.dmac_pri = 1;
486 else if (data->qos_type == 7)
487 PriDec.smac_pri = 1;
488
489 if (data->qos_table_idx == 0)
490 ret = rtk_qos_priSel_set(PRIDECTBL_IDX0, &PriDec);
491 else
492 ret = rtk_qos_priSel_set(PRIDECTBL_IDX1, &PriDec);
493
494 if (ret != 0)
495 printk("rtk_qos_priSel_set failed\n");
496
497 }
498
499 void rtk_hal_qos_get_table2type(struct ra_switch_ioctl_data *data)
500 {
501 rtk_api_ret_t ret;
502 rtk_priority_select_t PriDec;
503
504 if (data->qos_table_idx == 0)
505 ret = rtk_qos_priSel_get(PRIDECTBL_IDX0, &PriDec);
506 else
507 ret = rtk_qos_priSel_get(PRIDECTBL_IDX1, &PriDec);
508
509 if (ret != 0)
510 printk("rtk_qos_priSel_set failed\n");
511 else {
512 printk("port_pri = %d\n", PriDec.port_pri);
513 printk("dot1q_pri = %d\n", PriDec.dot1q_pri);
514 printk("acl_pri = %d\n", PriDec.acl_pri);
515 printk("dscp_pri = %d\n", PriDec.dscp_pri);
516 printk("cvlan_pri = %d\n", PriDec.cvlan_pri);
517 printk("svlan_pri = %d\n", PriDec.svlan_pri);
518 printk("dmac_pri = %d\n", PriDec.dmac_pri);
519 printk("smac_pri = %d\n", PriDec.smac_pri);
520 }
521 }
522
523 void rtk_hal_qos_set_port2table(struct ra_switch_ioctl_data *data)
524 {
525 rtk_api_ret_t ret;
526
527 ret = rtk_qos_portPriSelIndex_set(data->port, data->qos_table_idx);
528 if (ret != 0)
529 printk("rtk_qos_portPriSelIndex_set failed\n");
530 }
531
532 void rtk_hal_qos_get_port2table(struct ra_switch_ioctl_data *data)
533 {
534 rtk_api_ret_t ret;
535 rtk_qos_priDecTbl_t Index;
536
537 ret = rtk_qos_portPriSelIndex_get(data->port, &Index);
538 if (ret != 0)
539 printk("rtk_qos_portPriSelIndex_set failed\n");
540 else
541 printk("port%d belongs to table%d\n", data->port, Index);
542 }
543
544 void rtk_hal_qos_set_port2pri(struct ra_switch_ioctl_data *data)
545 {
546 rtk_api_ret_t ret;
547
548 ret = rtk_qos_portPri_set(data->port, data->qos_pri);
549 if (ret != 0)
550 printk("rtk_qos_portPri_set failed\n");
551 }
552
553 void rtk_hal_qos_get_port2pri(struct ra_switch_ioctl_data *data)
554 {
555 rtk_api_ret_t ret;
556 rtk_pri_t Int_pri;
557
558 ret = rtk_qos_portPri_get(data->port, &Int_pri);
559 if (ret != 0)
560 printk("rtk_qos_portPri_set failed\n");
561 else
562 printk("port%d priority = %d\n", data->port, Int_pri);
563 }
564
565 void rtk_hal_qos_set_dscp2pri(struct ra_switch_ioctl_data *data)
566 {
567 rtk_api_ret_t ret;
568
569 ret = rtk_qos_dscpPriRemap_set(data->qos_dscp, data->qos_pri);
570 if (ret != 0)
571 printk("rtk_qos_dscpPriRemap_set failed\n");
572 }
573
574 void rtk_hal_qos_get_dscp2pri(struct ra_switch_ioctl_data *data)
575 {
576 rtk_api_ret_t ret;
577 rtk_pri_t Int_pri;
578
579 ret = rtk_qos_dscpPriRemap_get(data->qos_dscp, &Int_pri);
580 if (ret != 0)
581 printk("rtk_qos_dscpPriRemap_set failed\n");
582 else
583 printk("dscp%d priority is %d\n", data->qos_dscp, Int_pri);
584 }
585
586 void rtk_hal_qos_set_pri2queue(struct ra_switch_ioctl_data *data)
587 {
588 rtk_api_ret_t ret;
589 rtk_qos_pri2queue_t pri2qid;
590
591 ret = rtk_qos_priMap_get(8, &pri2qid);
592 pri2qid.pri2queue[data->qos_queue_num] = data->qos_pri;
593 ret = rtk_qos_priMap_set(8, &pri2qid);
594 if (ret != 0)
595 printk("rtk_qos_priMap_set failed\n");
596 }
597
598 void rtk_hal_qos_get_pri2queue(struct ra_switch_ioctl_data *data)
599 {
600 int i;
601 rtk_api_ret_t ret;
602 rtk_qos_pri2queue_t pri2qid;
603
604 ret = rtk_qos_priMap_get(8, &pri2qid);
605 if (ret != 0)
606 printk("rtk_qos_priMap_get failed\n");
607 else {
608 for (i = 0; i < 8; i++)
609 printk("pri2qid.pri2queue[%d] = %d\n", i, pri2qid.pri2queue[i]);
610 }
611 }
612
613 void rtk_hal_qos_set_queue_weight(struct ra_switch_ioctl_data *data)
614 {
615 rtk_api_ret_t ret;
616 rtk_qos_queue_weights_t qweights;
617
618 ret = rtk_qos_schedulingQueue_get(data->port, &qweights);
619 qweights.weights[data->qos_queue_num] = data->qos_weight;
620 ret = rtk_qos_schedulingQueue_set(data->port, &qweights);
621 if (ret != 0)
622 printk("rtk_qos_schedulingQueue_set failed\n");
623 }
624
625 void rtk_hal_qos_get_queue_weight(struct ra_switch_ioctl_data *data)
626 {
627 int i;
628 rtk_api_ret_t ret;
629 rtk_qos_queue_weights_t qweights;
630
631 ret = rtk_qos_schedulingQueue_get(data->port, &qweights);
632 if (ret != 0)
633 printk("rtk_qos_schedulingQueue_get failed\n");
634 else {
635 printk("=== Port%d queue weight ===\n", data->port);
636 for (i = 0; i < 8; i++)
637 printk("qweights.weights[%d] = %d\n",i ,qweights.weights[i]);
638 }
639 }
640
641 void rtk_hal_enable_igmpsnoop(struct ra_switch_ioctl_data *data)
642 {
643 rtk_api_ret_t ret;
644 rtk_portmask_t pmask;
645
646
647 ret = rtk_igmp_init();
648 if (data->on_off == 1) {
649 RTK_PORTMASK_CLEAR(pmask);
650 RTK_PORTMASK_PORT_SET(pmask, EXT_PORT0);
651 ret |= rtk_igmp_static_router_port_set(&pmask);
652 ret |= rtk_igmp_protocol_set(UTP_PORT4, PROTOCOL_IGMPv1, IGMP_ACTION_FORWARD);
653 ret |= rtk_igmp_protocol_set(UTP_PORT4, PROTOCOL_IGMPv2, IGMP_ACTION_FORWARD);
654 ret |= rtk_igmp_protocol_set(UTP_PORT4, PROTOCOL_MLDv1, IGMP_ACTION_FORWARD);
655 ret |= rtk_igmp_protocol_set(EXT_PORT1, PROTOCOL_IGMPv1, IGMP_ACTION_FORWARD);
656 ret |= rtk_igmp_protocol_set(EXT_PORT1, PROTOCOL_IGMPv2, IGMP_ACTION_FORWARD);
657 ret |= rtk_igmp_protocol_set(EXT_PORT1, PROTOCOL_MLDv1, IGMP_ACTION_FORWARD);
658 ret |= rtk_igmp_protocol_set(UTP_PORT0, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);
659 ret |= rtk_igmp_protocol_set(UTP_PORT1, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);
660 ret |= rtk_igmp_protocol_set(UTP_PORT2, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);
661 ret |= rtk_igmp_protocol_set(UTP_PORT3, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);
662 ret |= rtk_igmp_protocol_set(EXT_PORT0, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);
663
664 ret |= rtk_leaky_vlan_set(LEAKY_IPMULTICAST, ENABLED);
665 ret |= rtk_l2_ipMcastForwardRouterPort_set(DISABLED);
666 /* drop unknown multicast packets*/
667 /* ret |= rtk_trap_unknownMcastPktAction_set(UTP_PORT4, MCAST_IPV4, MCAST_ACTION_DROP);*/
668 } else {
669 RTK_PORTMASK_CLEAR(pmask);
670 RTK_PORTMASK_PORT_SET(pmask, EXT_PORT0);
671 RTK_PORTMASK_PORT_SET(pmask, EXT_PORT1);
672 ret |= rtk_igmp_protocol_set(UTP_PORT0, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);
673 ret |= rtk_igmp_protocol_set(UTP_PORT1, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);
674 ret |= rtk_igmp_protocol_set(UTP_PORT2, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);
675 ret |= rtk_igmp_protocol_set(UTP_PORT3, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);
676 ret |= rtk_igmp_protocol_set(EXT_PORT0, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);
677
678 ret |= rtk_igmp_static_router_port_set(&pmask);
679 }
680 if(ret != RT_ERR_OK)
681 printk("enable switch igmpsnoop failed\n");
682 }
683
684 void rtk_hal_disable_igmpsnoop(void)
685 {
686 if (rtk_igmp_state_set(DISABLED) != RT_ERR_OK)
687 printk("Disable IGMP SNOOPING failed\n");
688 }
689
690 rtk_api_ret_t rtk_port_phyTestMode_set(rtk_port_t port, rtk_port_phy_test_mode_t mode)
691 {
692 rtk_uint32 data, regData, i;
693 rtk_api_ret_t retVal;
694
695 RTK_CHK_PORT_IS_UTP(port);
696
697 if(mode >= PHY_TEST_MODE_END)
698 return RT_ERR_INPUT;
699
700 if( (mode == PHY_TEST_MODE_2) || (mode == PHY_TEST_MODE_3) )
701 return RT_ERR_INPUT;
702
703 if (PHY_TEST_MODE_NORMAL != mode)
704 {
705 /* Other port should be Normal mode */
706 RTK_SCAN_ALL_LOG_PORT(i)
707 {
708 if(rtk_switch_isUtpPort(i) == RT_ERR_OK)
709 {
710 if(i != port)
711 {
712 if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(i), 9, &data)) != RT_ERR_OK)
713 return retVal;
714
715 if((data & 0xE000) != 0)
716 return RT_ERR_NOT_ALLOWED;
717 }
718 }
719 }
720 }
721
722 if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), 9, &data)) != RT_ERR_OK)
723 return retVal;
724
725 data &= ~0xE000;
726 data |= (mode << 13);
727 if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), 9, data)) != RT_ERR_OK)
728 return retVal;
729
730 if (PHY_TEST_MODE_4 == mode)
731 {
732 if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)
733 return retVal;
734
735 if((retVal = rtl8367c_getAsicReg(0x1300, &regData)) != RT_ERR_OK)
736 return retVal;
737
738 if( (regData == 0x0276) || (regData == 0x0597) )
739 {
740 if ((retVal = rtl8367c_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), 0xbcc2, 0xF4F4)) != RT_ERR_OK)
741 return retVal;
742 }
743
744 if( (regData == 0x6367) )
745 {
746 if ((retVal = rtl8367c_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), 0xa436, 0x80c1)) != RT_ERR_OK)
747 return retVal;
748
749 if ((retVal = rtl8367c_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), 0xa438, 0xfe00)) != RT_ERR_OK)
750 return retVal;
751 }
752 }
753
754 return RT_ERR_OK;
755 }
756
757 void rtk_hal_set_phy_test_mode(struct ra_switch_ioctl_data *data)
758 {
759 rtk_api_ret_t ret;
760
761 ret = rtk_port_phyTestMode_set(data->port, data->mode);
762 if (ret != RT_ERR_OK)
763 printk("rtk_port_phyTestMode_set failed\n");
764 else
765 printk("set port%d in test mode %d.\n", data->port, data->mode);
766 }
767
768 void rtk_hal_set_port_trunk(struct ra_switch_ioctl_data *data)
769 {
770
771 rtk_api_ret_t ret;
772 rtk_portmask_t member;
773 int i;
774
775 RTK_PORTMASK_CLEAR(member);
776 for (i = 0; i < 4; i++) {
777 if (data->port_map & (1 << i))
778 RTK_PORTMASK_PORT_SET(member, i);
779 }
780
781 ret = rtk_trunk_port_set(TRUNK_GROUP0, &member);
782 if (ret != RT_ERR_OK)
783 printk("rtk_trunk_port_set failed\n");
784
785 ret = rtk_trunk_distributionAlgorithm_set(RTK_WHOLE_SYSTEM, 0x7F);
786 if (ret != RT_ERR_OK)
787 printk("rtk_trunk_distributionAlgorithm_set failed\n");
788 }
789
790 void rtk_hal_vlan_tag(struct ra_switch_ioctl_data *data)
791 {
792 rtk_api_ret_t ret;
793 rtk_vlan_cfg_t vlan;
794
795 ret = rtk_vlan_get(data->vid, &vlan);
796 if (ret != RT_ERR_OK)
797 printk("rtk_vlan_get failed\n");
798 else {
799 if (data->on_off == 0)
800 RTK_PORTMASK_PORT_SET(vlan.untag, data->port);
801 else
802 RTK_PORTMASK_PORT_CLEAR(vlan.untag, data->port);
803
804 ret = rtk_vlan_set(data->vid, &vlan);
805 if (ret != RT_ERR_OK)
806 printk("rtk_vlan_set failed\n");
807 }
808 }
809
810 void rtk_hal_vlan_mode(struct ra_switch_ioctl_data *data)
811 {
812 rtk_vlan_cfg_t vlan1, vlan2;
813 rtk_api_ret_t ret;
814
815 ret = rtk_vlan_get(1, &vlan1);
816 if (ret != RT_ERR_OK)
817 printk("rtk_vlan_get failed\n");
818
819 ret = rtk_vlan_get(2, &vlan2);
820 if (ret != RT_ERR_OK)
821 printk("rtk_vlan_get failed\n");
822
823 if (data->mode == 0) { //ivl
824 vlan1.ivl_en = 1;
825 vlan1.fid_msti = 0;
826 rtk_vlan_set(1, &vlan1);
827 vlan2.ivl_en = 1;
828 vlan2.fid_msti = 0;
829 rtk_vlan_set(2, &vlan2);
830 } else if(data->mode == 1) {//svl
831 vlan1.ivl_en = 0;
832 vlan1.fid_msti = 0;
833 rtk_vlan_set(1, &vlan1);
834 vlan2.ivl_en = 0;
835 vlan2.fid_msti = 1;
836 rtk_vlan_set(2, &vlan2);
837 } else
838 printk("mode not supported\n");
839 }
OpenWrt Source Repository