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mediatek: switch to pending XFI 10G Ethernet drivers
[openwrt/openwrt.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7988a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/reset/mediatek,mt7988-resets.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 /* TOPRGU resets */
17 #define MT7988_TOPRGU_SGMII0_GRST 1
18 #define MT7988_TOPRGU_SGMII1_GRST 2
19 #define MT7988_TOPRGU_XFI0_GRST 12
20 #define MT7988_TOPRGU_XFI1_GRST 13
21 #define MT7988_TOPRGU_XFI_PEXTP0_GRST 14
22 #define MT7988_TOPRGU_XFI_PEXTP1_GRST 15
23 #define MT7988_TOPRGU_XFI_PLL_GRST 16
24
25 / {
26 compatible = "mediatek,mt7988";
27 interrupt-parent = <&gic>;
28 #address-cells = <2>;
29 #size-cells = <2>;
30
31 cci: cci {
32 compatible = "mediatek,mt7988-cci",
33 "mediatek,mt8183-cci";
34 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
35 <&topckgen CLK_TOP_XTAL>;
36 clock-names = "cci", "intermediate";
37 operating-points-v2 = <&cci_opp>;
38 };
39
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 cpu0: cpu@0 {
45 compatible = "arm,cortex-a73";
46 reg = <0x0>;
47 device_type = "cpu";
48 enable-method = "psci";
49 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
50 <&topckgen CLK_TOP_XTAL>;
51 clock-names = "cpu", "intermediate";
52 operating-points-v2 = <&cluster0_opp>;
53 mediatek,cci = <&cci>;
54 };
55
56 cpu1: cpu@1 {
57 compatible = "arm,cortex-a73";
58 reg = <0x1>;
59 device_type = "cpu";
60 enable-method = "psci";
61 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
62 <&topckgen CLK_TOP_XTAL>;
63 clock-names = "cpu", "intermediate";
64 operating-points-v2 = <&cluster0_opp>;
65 mediatek,cci = <&cci>;
66 };
67
68 cpu2: cpu@2 {
69 compatible = "arm,cortex-a73";
70 reg = <0x2>;
71 device_type = "cpu";
72 enable-method = "psci";
73 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
74 <&topckgen CLK_TOP_XTAL>;
75 clock-names = "cpu", "intermediate";
76 operating-points-v2 = <&cluster0_opp>;
77 mediatek,cci = <&cci>;
78 };
79
80 cpu3: cpu@3 {
81 compatible = "arm,cortex-a73";
82 reg = <0x3>;
83 device_type = "cpu";
84 enable-method = "psci";
85 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
86 <&topckgen CLK_TOP_XTAL>;
87 clock-names = "cpu", "intermediate";
88 operating-points-v2 = <&cluster0_opp>;
89 mediatek,cci = <&cci>;
90 };
91
92 cluster0_opp: opp_table0 {
93 compatible = "operating-points-v2";
94 opp-shared;
95
96 opp00 {
97 opp-hz = /bits/ 64 <800000000>;
98 opp-microvolt = <850000>;
99 };
100
101 opp01 {
102 opp-hz = /bits/ 64 <1100000000>;
103 opp-microvolt = <850000>;
104 };
105
106 opp02 {
107 opp-hz = /bits/ 64 <1500000000>;
108 opp-microvolt = <850000>;
109 };
110
111 opp03 {
112 opp-hz = /bits/ 64 <1800000000>;
113 opp-microvolt = <900000>;
114 };
115 };
116 };
117
118 cci_opp: opp_table_cci {
119 compatible = "operating-points-v2";
120 opp-shared;
121
122 opp00 {
123 opp-hz = /bits/ 64 <480000000>;
124 opp-microvolt = <850000>;
125 };
126
127 opp01 {
128 opp-hz = /bits/ 64 <660000000>;
129 opp-microvolt = <850000>;
130 };
131
132 opp02 {
133 opp-hz = /bits/ 64 <900000000>;
134 opp-microvolt = <850000>;
135 };
136
137 opp03 {
138 opp-hz = /bits/ 64 <1080000000>;
139 opp-microvolt = <900000>;
140 };
141 };
142
143 clk40m: oscillator@0 {
144 compatible = "fixed-clock";
145 clock-frequency = <40000000>;
146 #clock-cells = <0>;
147 clock-output-names = "clkxtal";
148 };
149
150 fan: pwm-fan {
151 compatible = "pwm-fan";
152 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
153 cooling-levels = <0 128 255>;
154 #cooling-cells = <2>;
155 #thermal-sensor-cells = <1>;
156 status = "disabled";
157 };
158
159 pmu {
160 compatible = "arm,cortex-a73-pmu";
161 interrupt-parent = <&gic>;
162 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
163 };
164
165 psci {
166 compatible = "arm,psci-0.2";
167 method = "smc";
168 };
169
170 reg_1p8v: regulator-1p8v {
171 compatible = "regulator-fixed";
172 regulator-name = "fixed-1.8V";
173 regulator-min-microvolt = <1800000>;
174 regulator-max-microvolt = <1800000>;
175 regulator-boot-on;
176 regulator-always-on;
177 };
178
179 reg_3p3v: regulator-3p3v {
180 compatible = "regulator-fixed";
181 regulator-name = "fixed-3.3V";
182 regulator-min-microvolt = <3300000>;
183 regulator-max-microvolt = <3300000>;
184 regulator-boot-on;
185 regulator-always-on;
186 };
187
188 reserved-memory {
189 ranges;
190 #address-cells = <2>;
191 #size-cells = <2>;
192
193 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
194 secmon_reserved: secmon@43000000 {
195 reg = <0 0x43000000 0 0x50000>;
196 no-map;
197 };
198 };
199
200 soc {
201 compatible = "simple-bus";
202 ranges;
203 #address-cells = <2>;
204 #size-cells = <2>;
205
206 gic: interrupt-controller@c000000 {
207 compatible = "arm,gic-v3";
208 reg = <0 0x0c000000 0 0x40000>, /* GICD */
209 <0 0x0c080000 0 0x200000>, /* GICR */
210 <0 0x0c400000 0 0x2000>, /* GICC */
211 <0 0x0c410000 0 0x1000>, /* GICH */
212 <0 0x0c420000 0 0x2000>; /* GICV */
213 interrupt-parent = <&gic>;
214 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
215 interrupt-controller;
216 #interrupt-cells = <3>;
217 };
218
219 phyfw: phy-firmware@f000000 {
220 compatible = "mediatek,2p5gphy-fw";
221 reg = <0 0x0f000000 0 0x8000>,
222 <0 0x0f100000 0 0x20000>,
223 <0 0x0f0f0000 0 0x200>;
224 };
225
226 infracfg: infracfg@10001000 {
227 compatible = "mediatek,mt7988-infracfg", "syscon";
228 reg = <0 0x10001000 0 0x1000>;
229 #clock-cells = <1>;
230 #reset-cells = <1>;
231 };
232
233 topckgen: topckgen@1001b000 {
234 compatible = "mediatek,mt7988-topckgen", "syscon";
235 reg = <0 0x1001b000 0 0x1000>;
236 #clock-cells = <1>;
237 };
238
239 watchdog: watchdog@1001c000 {
240 compatible = "mediatek,mt7988-wdt",
241 "mediatek,mt6589-wdt",
242 "syscon";
243 reg = <0 0x1001c000 0 0x1000>;
244 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
245 #reset-cells = <1>;
246 };
247
248 apmixedsys: apmixedsys@1001e000 {
249 compatible = "mediatek,mt7988-apmixedsys";
250 reg = <0 0x1001e000 0 0x1000>;
251 #clock-cells = <1>;
252 };
253
254 pio: pinctrl@1001f000 {
255 compatible = "mediatek,mt7988-pinctrl", "syscon";
256 reg = <0 0x1001f000 0 0x1000>,
257 <0 0x11c10000 0 0x1000>,
258 <0 0x11d00000 0 0x1000>,
259 <0 0x11d20000 0 0x1000>,
260 <0 0x11e00000 0 0x1000>,
261 <0 0x11f00000 0 0x1000>,
262 <0 0x1000b000 0 0x1000>;
263 reg-names = "gpio_base", "iocfg_tr_base",
264 "iocfg_br_base", "iocfg_rb_base",
265 "iocfg_lb_base", "iocfg_tl_base", "eint";
266 gpio-controller;
267 #gpio-cells = <2>;
268 gpio-ranges = <&pio 0 0 84>;
269 interrupt-controller;
270 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
271 interrupt-parent = <&gic>;
272 #interrupt-cells = <2>;
273
274 mdio0_pins: mdio0-pins {
275 mux {
276 function = "eth";
277 groups = "mdc_mdio0";
278 };
279
280 conf {
281 groups = "mdc_mdio0";
282 drive-strength = <MTK_DRIVE_8mA>;
283 };
284 };
285
286 i2c0_pins: i2c0-pins-g0 {
287 mux {
288 function = "i2c";
289 groups = "i2c0_1";
290 };
291 };
292
293 i2c1_pins: i2c1-pins-g0 {
294 mux {
295 function = "i2c";
296 groups = "i2c1_0";
297 };
298 };
299
300 i2c1_sfp_pins: i2c1-sfp-pins-g0 {
301 mux {
302 function = "i2c";
303 groups = "i2c1_sfp";
304 };
305 };
306
307 i2c2_pins: i2c2-pins {
308 mux {
309 function = "i2c";
310 groups = "i2c2";
311 };
312 };
313
314 i2c2_0_pins: i2c2-pins-g0 {
315 mux {
316 function = "i2c";
317 groups = "i2c2_0";
318 };
319 };
320
321 i2c2_1_pins: i2c2-pins-g1 {
322 mux {
323 function = "i2c";
324 groups = "i2c2_1";
325 };
326 };
327
328 gbe0_led0_pins: gbe0-led0-pins {
329 mux {
330 function = "led";
331 groups = "gbe0_led0";
332 };
333 };
334
335 gbe1_led0_pins: gbe1-led0-pins {
336 mux {
337 function = "led";
338 groups = "gbe1_led0";
339 };
340 };
341
342 gbe2_led0_pins: gbe2-led0-pins {
343 mux {
344 function = "led";
345 groups = "gbe2_led0";
346 };
347 };
348
349 gbe3_led0_pins: gbe3-led0-pins {
350 mux {
351 function = "led";
352 groups = "gbe3_led0";
353 };
354 };
355
356 gbe0_led1_pins: gbe0-led1-pins {
357 mux {
358 function = "led";
359 groups = "gbe0_led1";
360 };
361 };
362
363 gbe1_led1_pins: gbe1-led1-pins {
364 mux {
365 function = "led";
366 groups = "gbe1_led1";
367 };
368 };
369
370 gbe2_led1_pins: gbe2-led1-pins {
371 mux {
372 function = "led";
373 groups = "gbe2_led1";
374 };
375 };
376
377 gbe3_led1_pins: gbe3-led1-pins {
378 mux {
379 function = "led";
380 groups = "gbe3_led1";
381 };
382 };
383
384 i2p5gbe_led0_pins: 2p5gbe-led0-pins {
385 mux {
386 function = "led";
387 groups = "2p5gbe_led0";
388 };
389 };
390
391 i2p5gbe_led1_pins: 2p5gbe-led1-pins {
392 mux {
393 function = "led";
394 groups = "2p5gbe_led1";
395 };
396 };
397
398 mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
399 mux {
400 function = "flash";
401 groups = "emmc_45";
402 };
403 };
404
405 mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
406 mux {
407 function = "flash";
408 groups = "emmc_51";
409 };
410 };
411
412 mmc0_pins_sdcard: mmc0-pins-sdcard {
413 mux {
414 function = "flash";
415 groups = "sdcard";
416 };
417 };
418
419 uart0_pins: uart0-pins {
420 mux {
421 function = "uart";
422 groups = "uart0";
423 };
424 };
425
426 snfi_pins: snfi-pins {
427 mux {
428 function = "flash";
429 groups = "snfi";
430 };
431 };
432
433 spi0_pins: spi0-pins {
434 mux {
435 function = "spi";
436 groups = "spi0";
437 };
438 };
439
440 spi0_flash_pins: spi0-flash-pins {
441 mux {
442 function = "spi";
443 groups = "spi0", "spi0_wp_hold";
444 };
445 };
446
447 spi1_pins: spi1-pins {
448 mux {
449 function = "spi";
450 groups = "spi1";
451 };
452 };
453
454 spi2_pins: spi2-pins {
455 mux {
456 function = "spi";
457 groups = "spi2";
458 };
459 };
460
461 spi2_flash_pins: spi2-flash-pins {
462 mux {
463 function = "spi";
464 groups = "spi2", "spi2_wp_hold";
465 };
466 };
467
468 pcie0_pins: pcie0-pins {
469 mux {
470 function = "pcie";
471 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
472 "pcie_wake_n0_0";
473 };
474 };
475
476 pcie1_pins: pcie1-pins {
477 mux {
478 function = "pcie";
479 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
480 "pcie_wake_n1_0";
481 };
482 };
483
484 pcie2_pins: pcie2-pins {
485 mux {
486 function = "pcie";
487 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
488 "pcie_wake_n2_0";
489 };
490 };
491
492 pcie3_pins: pcie3-pins {
493 mux {
494 function = "pcie";
495 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
496 "pcie_wake_n3_0";
497 };
498 };
499 };
500
501 pwm: pwm@10048000 {
502 compatible = "mediatek,mt7988-pwm";
503 reg = <0 0x10048000 0 0x1000>;
504 #pwm-cells = <2>;
505 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
506 <&infracfg CLK_INFRA_66M_PWM_HCK>,
507 <&infracfg CLK_INFRA_66M_PWM_CK1>,
508 <&infracfg CLK_INFRA_66M_PWM_CK2>,
509 <&infracfg CLK_INFRA_66M_PWM_CK3>,
510 <&infracfg CLK_INFRA_66M_PWM_CK4>,
511 <&infracfg CLK_INFRA_66M_PWM_CK5>,
512 <&infracfg CLK_INFRA_66M_PWM_CK6>,
513 <&infracfg CLK_INFRA_66M_PWM_CK7>,
514 <&infracfg CLK_INFRA_66M_PWM_CK8>;
515 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
516 "pwm4","pwm5","pwm6","pwm7","pwm8";
517 status = "disabled";
518 };
519
520 sgmiisys0: syscon@10060000 {
521 compatible = "mediatek,mt7988-sgmiisys",
522 "mediatek,mt7988-sgmiisys0",
523 "syscon",
524 "simple-mfd";
525 reg = <0 0x10060000 0 0x1000>;
526 resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
527 #clock-cells = <1>;
528
529 sgmiipcs0: pcs {
530 compatible = "mediatek,mt7988-sgmii";
531 clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
532 <&sgmiisys0 CLK_SGM0_TX_EN>,
533 <&sgmiisys0 CLK_SGM0_RX_EN>;
534 clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
535 };
536 };
537
538 sgmiisys1: syscon@10070000 {
539 compatible = "mediatek,mt7988-sgmiisys",
540 "mediatek,mt7988-sgmiisys1",
541 "syscon",
542 "simple-mfd";
543 reg = <0 0x10070000 0 0x1000>;
544 resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
545 #clock-cells = <1>;
546
547 sgmiipcs1: pcs {
548 compatible = "mediatek,mt7988-sgmii";
549 clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
550 <&sgmiisys1 CLK_SGM1_TX_EN>,
551 <&sgmiisys1 CLK_SGM1_RX_EN>;
552 clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
553 };
554 };
555
556 usxgmiisys0: pcs@10080000 {
557 compatible = "mediatek,mt7988-usxgmiisys";
558 reg = <0 0x10080000 0 0x1000>;
559 resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
560 clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
561 };
562
563 usxgmiisys1: pcs@10081000 {
564 compatible = "mediatek,mt7988-usxgmiisys";
565 reg = <0 0x10081000 0 0x1000>;
566 resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
567 clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
568 };
569
570 mcusys: mcusys@100e0000 {
571 compatible = "mediatek,mt7988-mcusys", "syscon";
572 reg = <0 0x100e0000 0 0x1000>;
573 #clock-cells = <1>;
574 };
575
576 uart0: serial@11000000 {
577 compatible = "mediatek,mt7986-uart",
578 "mediatek,mt6577-uart";
579 reg = <0 0x11000000 0 0x100>;
580 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
581 /*
582 * 8250-mtk driver don't control "baud" clock since commit
583 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
584 * still need to be passed to the driver to prevent probe fail
585 */
586 clocks = <&topckgen CLK_TOP_UART_SEL>,
587 <&infracfg CLK_INFRA_52M_UART0_CK>;
588 clock-names = "baud", "bus";
589 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
590 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
591 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
592 <&topckgen CLK_TOP_UART_SEL>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&uart0_pins>;
595 status = "disabled";
596 };
597
598 snand: spi@11001000 {
599 compatible = "mediatek,mt7986-snand";
600 reg = <0 0x11001000 0 0x1000>;
601 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&infracfg CLK_INFRA_SPINFI>,
603 <&infracfg CLK_INFRA_NFI>;
604 clock-names = "pad_clk", "nfi_clk";
605 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
606 <&topckgen CLK_TOP_NFI1X_SEL>;
607 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
608 <&topckgen CLK_TOP_MPLL_D8>;
609 nand-ecc-engine = <&bch>;
610 mediatek,quad-spi;
611 #address-cells = <1>;
612 #size-cells = <0>;
613 pinctrl-names = "default";
614 pinctrl-0 = <&snfi_pins>;
615 status = "disabled";
616 };
617
618 bch: ecc@11002000 {
619 compatible = "mediatek,mt7686-ecc";
620 reg = <0 0x11002000 0 0x1000>;
621 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
623 clock-names = "nfiecc_clk";
624 status = "disabled";
625 };
626
627 i2c0: i2c@11003000 {
628 compatible = "mediatek,mt7988-i2c",
629 "mediatek,mt7981-i2c";
630 reg = <0 0x11003000 0 0x1000>,
631 <0 0x10217080 0 0x80>;
632 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
633 clock-div = <1>;
634 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
635 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
636 clock-names = "main", "dma";
637 #address-cells = <1>;
638 #size-cells = <0>;
639 status = "disabled";
640 };
641
642 i2c1: i2c@11004000 {
643 compatible = "mediatek,mt7988-i2c",
644 "mediatek,mt7981-i2c";
645 reg = <0 0x11004000 0 0x1000>,
646 <0 0x10217100 0 0x80>;
647 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
648 clock-div = <1>;
649 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
650 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
651 clock-names = "main", "dma";
652 #address-cells = <1>;
653 #size-cells = <0>;
654 status = "disabled";
655 };
656
657 i2c2: i2c@11005000 {
658 compatible = "mediatek,mt7988-i2c",
659 "mediatek,mt7981-i2c";
660 reg = <0 0x11005000 0 0x1000>,
661 <0 0x10217180 0 0x80>;
662 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
663 clock-div = <1>;
664 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
665 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
666 clock-names = "main", "dma";
667 #address-cells = <1>;
668 #size-cells = <0>;
669 status = "disabled";
670 };
671
672 spi0: spi@11007000 {
673 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
674 reg = <0 0x11007000 0 0x100>;
675 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&topckgen CLK_TOP_MPLL_D2>,
677 <&topckgen CLK_TOP_SPI_SEL>,
678 <&infracfg CLK_INFRA_104M_SPI0>,
679 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
680 clock-names = "parent-clk", "sel-clk", "spi-clk",
681 "spi-hclk";
682 #address-cells = <1>;
683 #size-cells = <0>;
684 status = "disabled";
685 };
686
687 spi1: spi@11008000 {
688 compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
689 reg = <0 0x11008000 0 0x100>;
690 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&topckgen CLK_TOP_MPLL_D2>,
692 <&topckgen CLK_TOP_SPI_SEL>,
693 <&infracfg CLK_INFRA_104M_SPI1>,
694 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
695 clock-names = "parent-clk", "sel-clk", "spi-clk",
696 "spi-hclk";
697 #address-cells = <1>;
698 #size-cells = <0>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&spi1_pins>;
701 status = "disabled";
702 };
703
704 spi2: spi@11009000 {
705 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
706 reg = <0 0x11009000 0 0x100>;
707 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&topckgen CLK_TOP_MPLL_D2>,
709 <&topckgen CLK_TOP_SPI_SEL>,
710 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
711 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
712 clock-names = "parent-clk", "sel-clk", "spi-clk",
713 "spi-hclk";
714 #address-cells = <1>;
715 #size-cells = <0>;
716 status = "disabled";
717 };
718
719 lvts: lvts@1100a000 {
720 compatible = "mediatek,mt7988-lvts-ap";
721 reg = <0 0x1100a000 0 0x1000>;
722 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
723 clock-names = "lvts_clk";
724 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
725 resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
726 nvmem-cells = <&lvts_calibration>;
727 nvmem-cell-names = "lvts-calib-data-1";
728 #thermal-sensor-cells = <1>;
729 };
730
731 ssusb0: usb@11190000 {
732 compatible = "mediatek,mt7988-xhci",
733 "mediatek,mtk-xhci";
734 reg = <0 0x11190000 0 0x2e00>,
735 <0 0x11193e00 0 0x0100>;
736 reg-names = "mac", "ippc";
737 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
738 phys = <&xphyu2port0 PHY_TYPE_USB2>,
739 <&xphyu3port0 PHY_TYPE_USB3>;
740 clocks = <&infracfg CLK_INFRA_USB_SYS>,
741 <&infracfg CLK_INFRA_USB_XHCI>,
742 <&infracfg CLK_INFRA_USB_REF>,
743 <&infracfg CLK_INFRA_66M_USB_HCK>,
744 <&infracfg CLK_INFRA_133M_USB_HCK>;
745 clock-names = "sys_ck",
746 "xhci_ck",
747 "ref_ck",
748 "mcu_ck",
749 "dma_ck";
750 #address-cells = <2>;
751 #size-cells = <2>;
752 mediatek,p0_speed_fixup;
753 status = "disabled";
754 };
755
756 ssusb1: usb@11200000 {
757 compatible = "mediatek,mt7988-xhci",
758 "mediatek,mtk-xhci";
759 reg = <0 0x11200000 0 0x2e00>,
760 <0 0x11203e00 0 0x0100>;
761 reg-names = "mac", "ippc";
762 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
763 phys = <&tphyu2port0 PHY_TYPE_USB2>,
764 <&tphyu3port0 PHY_TYPE_USB3>;
765 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
766 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
767 <&infracfg CLK_INFRA_USB_CK_P1>,
768 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
769 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
770 clock-names = "sys_ck",
771 "xhci_ck",
772 "ref_ck",
773 "mcu_ck",
774 "dma_ck";
775 #address-cells = <2>;
776 #size-cells = <2>;
777 status = "disabled";
778 };
779
780 afe: audio-controller@11210000 {
781 compatible = "mediatek,mt79xx-audio";
782 reg = <0 0x11210000 0 0x9000>;
783 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
785 <&infracfg CLK_INFRA_AUD_26M>,
786 <&infracfg CLK_INFRA_AUD_L>,
787 <&infracfg CLK_INFRA_AUD_AUD>,
788 <&infracfg CLK_INFRA_AUD_EG2>,
789 <&topckgen CLK_TOP_AUD_SEL>,
790 <&topckgen CLK_TOP_AUD_I2S_M>;
791 clock-names = "aud_bus_ck",
792 "aud_26m_ck",
793 "aud_l_ck",
794 "aud_aud_ck",
795 "aud_eg2_ck",
796 "aud_sel",
797 "aud_i2s_m";
798 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
799 <&topckgen CLK_TOP_A1SYS_SEL>,
800 <&topckgen CLK_TOP_AUD_L_SEL>,
801 <&topckgen CLK_TOP_A_TUNER_SEL>;
802 assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
803 <&topckgen CLK_TOP_APLL2_D4>,
804 <&apmixedsys CLK_APMIXED_APLL2>,
805 <&topckgen CLK_TOP_APLL2_D4>;
806 status = "disabled";
807 };
808
809 mmc0: mmc@11230000 {
810 compatible = "mediatek,mt7986-mmc",
811 "mediatek,mt7981-mmc";
812 reg = <0 0x11230000 0 0x1000>,
813 <0 0x11D60000 0 0x1000>;
814 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&infracfg CLK_INFRA_MSDC400>,
816 <&infracfg CLK_INFRA_MSDC2_HCK>,
817 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
818 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
819 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
820 <&topckgen CLK_TOP_EMMC_400M_SEL>;
821 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
822 <&apmixedsys CLK_APMIXED_MSDCPLL>;
823 clock-names = "source",
824 "hclk",
825 "axi_cg",
826 "ahb_cg";
827 #address-cells = <1>;
828 #size-cells = <0>;
829 status = "disabled";
830 };
831
832 pcie2: pcie@11280000 {
833 compatible = "mediatek,mt7988-pcie",
834 "mediatek,mt7986-pcie",
835 "mediatek,mt8192-pcie";
836 reg = <0 0x11280000 0 0x2000>;
837 reg-names = "pcie-mac";
838 ranges = <0x81000000 0x00 0x20000000 0x00
839 0x20000000 0x00 0x00200000>,
840 <0x82000000 0x00 0x20200000 0x00
841 0x20200000 0x00 0x07e00000>;
842 device_type = "pci";
843 linux,pci-domain = <3>;
844 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
845 bus-range = <0x00 0xff>;
846 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
847 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
848 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
849 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
850 clock-names = "pl_250m", "tl_26m", "peri_26m",
851 "top_133m";
852 pinctrl-names = "default";
853 pinctrl-0 = <&pcie2_pins>;
854 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
855 phy-names = "pcie-phy";
856 #interrupt-cells = <1>;
857 interrupt-map-mask = <0 0 0 0x7>;
858 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
859 <0 0 0 2 &pcie_intc2 1>,
860 <0 0 0 3 &pcie_intc2 2>,
861 <0 0 0 4 &pcie_intc2 3>;
862 #address-cells = <3>;
863 #size-cells = <2>;
864 status = "disabled";
865
866 pcie_intc2: interrupt-controller {
867 #address-cells = <0>;
868 #interrupt-cells = <1>;
869 interrupt-controller;
870 };
871 };
872
873 pcie3: pcie@11290000 {
874 compatible = "mediatek,mt7988-pcie",
875 "mediatek,mt7986-pcie",
876 "mediatek,mt8192-pcie";
877 reg = <0 0x11290000 0 0x2000>;
878 reg-names = "pcie-mac";
879 ranges = <0x81000000 0x00 0x28000000 0x00
880 0x28000000 0x00 0x00200000>,
881 <0x82000000 0x00 0x28200000 0x00
882 0x28200000 0x00 0x07e00000>;
883 device_type = "pci";
884 linux,pci-domain = <2>;
885 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
886 bus-range = <0x00 0xff>;
887 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
888 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
889 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
890 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
891 clock-names = "pl_250m", "tl_26m", "peri_26m",
892 "top_133m";
893 pinctrl-names = "default";
894 pinctrl-0 = <&pcie3_pins>;
895 #interrupt-cells = <1>;
896 interrupt-map-mask = <0 0 0 0x7>;
897 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
898 <0 0 0 2 &pcie_intc3 1>,
899 <0 0 0 3 &pcie_intc3 2>,
900 <0 0 0 4 &pcie_intc3 3>;
901 #address-cells = <3>;
902 #size-cells = <2>;
903 status = "disabled";
904
905 pcie_intc3: interrupt-controller {
906 #address-cells = <0>;
907 #interrupt-cells = <1>;
908 interrupt-controller;
909 };
910 };
911
912 pcie0: pcie@11300000 {
913 compatible = "mediatek,mt7988-pcie",
914 "mediatek,mt7986-pcie",
915 "mediatek,mt8192-pcie";
916 reg = <0 0x11300000 0 0x2000>;
917 reg-names = "pcie-mac";
918 ranges = <0x81000000 0x00 0x30000000 0x00
919 0x30000000 0x00 0x00200000>,
920 <0x82000000 0x00 0x30200000 0x00
921 0x30200000 0x00 0x07e00000>;
922 device_type = "pci";
923 linux,pci-domain = <0>;
924 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
925 bus-range = <0x00 0xff>;
926 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
927 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
928 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
929 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
930 clock-names = "pl_250m", "tl_26m", "peri_26m",
931 "top_133m";
932 pinctrl-names = "default";
933 pinctrl-0 = <&pcie0_pins>;
934 #interrupt-cells = <1>;
935 interrupt-map-mask = <0 0 0 0x7>;
936 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
937 <0 0 0 2 &pcie_intc0 1>,
938 <0 0 0 3 &pcie_intc0 2>,
939 <0 0 0 4 &pcie_intc0 3>;
940 #address-cells = <3>;
941 #size-cells = <2>;
942 status = "disabled";
943
944 pcie_intc0: interrupt-controller {
945 #address-cells = <0>;
946 #interrupt-cells = <1>;
947 interrupt-controller;
948 };
949 };
950
951 pcie1: pcie@11310000 {
952 compatible = "mediatek,mt7988-pcie",
953 "mediatek,mt7986-pcie",
954 "mediatek,mt8192-pcie";
955 reg = <0 0x11310000 0 0x2000>;
956 reg-names = "pcie-mac";
957 ranges = <0x81000000 0x00 0x38000000 0x00
958 0x38000000 0x00 0x00200000>,
959 <0x82000000 0x00 0x38200000 0x00
960 0x38200000 0x00 0x07e00000>;
961 device_type = "pci";
962 linux,pci-domain = <1>;
963 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
964 bus-range = <0x00 0xff>;
965 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
966 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
967 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
968 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
969 clock-names = "pl_250m", "tl_26m", "peri_26m",
970 "top_133m";
971 pinctrl-names = "default";
972 pinctrl-0 = <&pcie1_pins>;
973 #interrupt-cells = <1>;
974 interrupt-map-mask = <0 0 0 0x7>;
975 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
976 <0 0 0 2 &pcie_intc1 1>,
977 <0 0 0 3 &pcie_intc1 2>,
978 <0 0 0 4 &pcie_intc1 3>;
979 #address-cells = <3>;
980 #size-cells = <2>;
981 status = "disabled";
982
983 pcie_intc1: interrupt-controller {
984 #address-cells = <0>;
985 #interrupt-cells = <1>;
986 interrupt-controller;
987 };
988 };
989
990 tphy: tphy@11c50000 {
991 compatible = "mediatek,mt7988",
992 "mediatek,generic-tphy-v2";
993 ranges;
994 #address-cells = <2>;
995 #size-cells = <2>;
996 status = "disabled";
997
998 tphyu2port0: usb-phy@11c50000 {
999 reg = <0 0x11c50000 0 0x700>;
1000 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
1001 clock-names = "ref";
1002 #phy-cells = <1>;
1003 };
1004
1005 tphyu3port0: usb-phy@11c50700 {
1006 reg = <0 0x11c50700 0 0x900>;
1007 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
1008 clock-names = "ref";
1009 #phy-cells = <1>;
1010 mediatek,usb3-pll-ssc-delta;
1011 mediatek,usb3-pll-ssc-delta1;
1012 };
1013 };
1014
1015 topmisc: topmisc@11d10000 {
1016 compatible = "mediatek,mt7988-topmisc", "syscon",
1017 "mediatek,mt7988-power-controller";
1018 reg = <0 0x11d10000 0 0x10000>;
1019 #clock-cells = <1>;
1020 #power-domain-cells = <1>;
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 };
1024
1025 xphy: xphy@11e10000 {
1026 compatible = "mediatek,mt7988",
1027 "mediatek,xsphy";
1028 ranges;
1029 #address-cells = <2>;
1030 #size-cells = <2>;
1031 status = "disabled";
1032
1033 xphyu2port0: usb-phy@11e10000 {
1034 reg = <0 0x11e10000 0 0x400>;
1035 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
1036 clock-names = "ref";
1037 #phy-cells = <1>;
1038 };
1039
1040 xphyu3port0: usb-phy@11e13000 {
1041 reg = <0 0x11e13400 0 0x500>;
1042 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
1043 clock-names = "ref";
1044 #phy-cells = <1>;
1045 mediatek,syscon-type = <&topmisc 0x218 0>;
1046 };
1047 };
1048
1049 xfi_tphy0: phy@11f20000 {
1050 compatible = "mediatek,mt7988-xfi-tphy";
1051 reg = <0 0x11f20000 0 0x10000>;
1052 resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
1053 clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
1054 clock-names = "xfipll", "topxtal";
1055 mediatek,usxgmii-performance-errata;
1056 #phy-cells = <0>;
1057 };
1058
1059 xfi_tphy1: phy@11f30000 {
1060 compatible = "mediatek,mt7988-xfi-tphy";
1061 reg = <0 0x11f30000 0 0x10000>;
1062 resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
1063 clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
1064 clock-names = "xfipll", "topxtal";
1065 #phy-cells = <0>;
1066 };
1067
1068 xfi_pll: clock-controller@11f40000 {
1069 compatible = "mediatek,mt7988-xfi-pll";
1070 reg = <0 0x11f40000 0 0x1000>;
1071 resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
1072 #clock-cells = <1>;
1073 };
1074
1075 efuse: efuse@11f50000 {
1076 compatible = "mediatek,efuse";
1077 reg = <0 0x11f50000 0 0x1000>;
1078 #address-cells = <1>;
1079 #size-cells = <1>;
1080
1081 lvts_calibration: calib@918 {
1082 reg = <0x918 0x28>;
1083 };
1084
1085 phy_calibration_p0: calib@940 {
1086 reg = <0x940 0x10>;
1087 };
1088
1089 phy_calibration_p1: calib@954 {
1090 reg = <0x954 0x10>;
1091 };
1092
1093 phy_calibration_p2: calib@968 {
1094 reg = <0x968 0x10>;
1095 };
1096
1097 phy_calibration_p3: calib@97c {
1098 reg = <0x97c 0x10>;
1099 };
1100
1101 cpufreq_calibration: calib@278 {
1102 reg = <0x278 0x1>;
1103 };
1104 };
1105
1106 ethsys: syscon@15000000 {
1107 compatible = "mediatek,mt7988-ethsys", "syscon";
1108 reg = <0 0x15000000 0 0x1000>;
1109 #clock-cells = <1>;
1110 #reset-cells = <1>;
1111 #address-cells = <1>;
1112 #size-cells = <1>;
1113 };
1114
1115 switch: switch@15020000 {
1116 compatible = "mediatek,mt7988-switch";
1117 reg = <0 0x15020000 0 0x8000>;
1118 interrupt-controller;
1119 #interrupt-cells = <1>;
1120 interrupt-parent = <&gic>;
1121 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1122 resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
1123 #address-cells = <1>;
1124 #size-cells = <1>;
1125
1126 ports {
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1129
1130 port@0 {
1131 reg = <0>;
1132 label = "lan0";
1133 phy-mode = "internal";
1134 phy-handle = <&gsw_phy0>;
1135 };
1136
1137 port@1 {
1138 reg = <1>;
1139 label = "lan1";
1140 phy-mode = "internal";
1141 phy-handle = <&gsw_phy1>;
1142 };
1143
1144 port@2 {
1145 reg = <2>;
1146 label = "lan2";
1147 phy-mode = "internal";
1148 phy-handle = <&gsw_phy2>;
1149 };
1150
1151 port@3 {
1152 reg = <3>;
1153 label = "lan3";
1154 phy-mode = "internal";
1155 phy-handle = <&gsw_phy3>;
1156 };
1157
1158 port@6 {
1159 reg = <6>;
1160 ethernet = <&gmac0>;
1161 phy-mode = "internal";
1162
1163 fixed-link {
1164 speed = <10000>;
1165 full-duplex;
1166 pause;
1167 };
1168 };
1169 };
1170
1171 mdio {
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1174 mediatek,pio = <&pio>;
1175
1176 gsw_phy0: ethernet-phy@0 {
1177 compatible = "ethernet-phy-ieee802.3-c22";
1178 reg = <0>;
1179 phy-mode = "internal";
1180 nvmem-cells = <&phy_calibration_p0>;
1181 nvmem-cell-names = "phy-cal-data";
1182
1183 leds {
1184 #address-cells = <1>;
1185 #size-cells = <0>;
1186
1187 gsw_phy0_led0: gsw-phy0-led0@0 {
1188 reg = <0>;
1189 function = LED_FUNCTION_LAN;
1190 status = "disabled";
1191 };
1192
1193 gsw_phy0_led1: gsw-phy0-led1@1 {
1194 reg = <1>;
1195 function = LED_FUNCTION_LAN;
1196 status = "disabled";
1197 };
1198 };
1199 };
1200
1201 gsw_phy1: ethernet-phy@1 {
1202 compatible = "ethernet-phy-ieee802.3-c22";
1203 reg = <1>;
1204 phy-mode = "internal";
1205 nvmem-cells = <&phy_calibration_p1>;
1206 nvmem-cell-names = "phy-cal-data";
1207
1208 leds {
1209 #address-cells = <1>;
1210 #size-cells = <0>;
1211
1212 gsw_phy1_led0: gsw-phy1-led0@0 {
1213 reg = <0>;
1214 function = LED_FUNCTION_LAN;
1215 status = "disabled";
1216 };
1217
1218 gsw_phy1_led1: gsw-phy1-led1@1 {
1219 reg = <1>;
1220 function = LED_FUNCTION_LAN;
1221 status = "disabled";
1222 };
1223 };
1224 };
1225
1226 gsw_phy2: ethernet-phy@2 {
1227 compatible = "ethernet-phy-ieee802.3-c22";
1228 reg = <2>;
1229 phy-mode = "internal";
1230 nvmem-cells = <&phy_calibration_p2>;
1231 nvmem-cell-names = "phy-cal-data";
1232
1233 leds {
1234 #address-cells = <1>;
1235 #size-cells = <0>;
1236
1237 gsw_phy2_led0: gsw-phy2-led0@0 {
1238 reg = <0>;
1239 function = LED_FUNCTION_LAN;
1240 status = "disabled";
1241 };
1242
1243 gsw_phy2_led1: gsw-phy2-led1@1 {
1244 reg = <1>;
1245 function = LED_FUNCTION_LAN;
1246 status = "disabled";
1247 };
1248 };
1249 };
1250
1251 gsw_phy3: ethernet-phy@3 {
1252 compatible = "ethernet-phy-ieee802.3-c22";
1253 reg = <3>;
1254 phy-mode = "internal";
1255 nvmem-cells = <&phy_calibration_p3>;
1256 nvmem-cell-names = "phy-cal-data";
1257
1258 leds {
1259 #address-cells = <1>;
1260 #size-cells = <0>;
1261
1262 gsw_phy3_led0: gsw-phy3-led0@0 {
1263 reg = <0>;
1264 function = LED_FUNCTION_LAN;
1265 status = "disabled";
1266 };
1267
1268 gsw_phy3_led1: gsw-phy3-led1@1 {
1269 reg = <1>;
1270 function = LED_FUNCTION_LAN;
1271 status = "disabled";
1272 };
1273 };
1274 };
1275 };
1276 };
1277
1278 ethwarp: clock-controller@15031000 {
1279 compatible = "mediatek,mt7988-ethwarp";
1280 reg = <0 0x15031000 0 0x1000>;
1281 #clock-cells = <1>;
1282 #reset-cells = <1>;
1283 };
1284
1285 eth: ethernet@15100000 {
1286 compatible = "mediatek,mt7988-eth";
1287 reg = <0 0x15100000 0 0x80000>,
1288 <0 0x15400000 0 0x380000>;
1289 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1290 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1291 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1292 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
1294 <&ethsys CLK_ETHDMA_XGP2_EN>,
1295 <&ethsys CLK_ETHDMA_XGP3_EN>,
1296 <&ethsys CLK_ETHDMA_FE_EN>,
1297 <&ethsys CLK_ETHDMA_GP2_EN>,
1298 <&ethsys CLK_ETHDMA_GP1_EN>,
1299 <&ethsys CLK_ETHDMA_GP3_EN>,
1300 <&ethsys CLK_ETHDMA_ESW_EN>,
1301 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
1302 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
1303 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
1304 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
1305 <&topckgen CLK_TOP_ETH_GMII_SEL>,
1306 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1307 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1308 <&topckgen CLK_TOP_ETH_SYS_SEL>,
1309 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1310 <&topckgen CLK_TOP_ETH_MII_SEL>,
1311 <&topckgen CLK_TOP_NETSYS_SEL>,
1312 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1313 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1314 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1315 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1316 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1317 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1318 "gp3", "esw", "crypto",
1319 "ethwarp_wocpu2", "ethwarp_wocpu1",
1320 "ethwarp_wocpu0", "top_eth_gmii_sel",
1321 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1322 "top_eth_sys_sel", "top_eth_xgmii_sel",
1323 "top_eth_mii_sel", "top_netsys_sel",
1324 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1325 "top_netsys_sync_250m_sel",
1326 "top_netsys_ppefb_250m_sel",
1327 "top_netsys_warp_sel";
1328 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1329 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1330 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1331 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1332 <&topckgen CLK_TOP_SGM_0_SEL>,
1333 <&topckgen CLK_TOP_SGM_1_SEL>;
1334 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1335 <&topckgen CLK_TOP_NET1PLL_D4>,
1336 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1337 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1338 <&apmixedsys CLK_APMIXED_SGMPLL>,
1339 <&apmixedsys CLK_APMIXED_SGMPLL>;
1340 mediatek,ethsys = <&ethsys>;
1341 mediatek,infracfg = <&topmisc>;
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1344
1345 gmac0: mac@0 {
1346 compatible = "mediatek,eth-mac";
1347 reg = <0>;
1348 phy-mode = "internal";
1349 status = "disabled";
1350
1351 fixed-link {
1352 speed = <10000>;
1353 full-duplex;
1354 pause;
1355 };
1356 };
1357
1358 gmac1: mac@1 {
1359 compatible = "mediatek,eth-mac";
1360 reg = <1>;
1361 status = "disabled";
1362 pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
1363 phys = <&xfi_tphy1>;
1364 };
1365
1366 gmac2: mac@2 {
1367 compatible = "mediatek,eth-mac";
1368 reg = <2>;
1369 status = "disabled";
1370 pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
1371 phys = <&xfi_tphy0>;
1372 };
1373
1374 mdio_bus: mdio-bus {
1375 #address-cells = <1>;
1376 #size-cells = <0>;
1377
1378 /* internal 2.5G PHY */
1379 int_2p5g_phy: ethernet-phy@15 {
1380 compatible = "ethernet-phy-ieee802.3-c45";
1381 reg = <15>;
1382 phy-mode = "internal";
1383 };
1384 };
1385 };
1386
1387 crypto: crypto@15600000 {
1388 compatible = "inside-secure,safexcel-eip197b";
1389 reg = <0 0x15600000 0 0x180000>;
1390 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1391 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1394 interrupt-names = "ring0", "ring1", "ring2", "ring3";
1395 status = "okay";
1396 };
1397 };
1398
1399 thermal-zones {
1400 cpu_thermal: cpu-thermal {
1401 polling-delay-passive = <1000>;
1402 polling-delay = <1000>;
1403 thermal-sensors = <&lvts 0>;
1404
1405 trips {
1406 cpu_trip_crit: crit {
1407 temperature = <125000>;
1408 hysteresis = <2000>;
1409 type = "critical";
1410 };
1411
1412 cpu_trip_hot: hot {
1413 temperature = <120000>;
1414 hysteresis = <2000>;
1415 type = "hot";
1416 };
1417
1418 cpu_trip_active_high: active-high {
1419 temperature = <115000>;
1420 hysteresis = <2000>;
1421 type = "active";
1422 };
1423
1424 cpu_trip_active_med: active-med {
1425 temperature = <85000>;
1426 hysteresis = <2000>;
1427 type = "active";
1428 };
1429
1430 cpu_trip_active_low: active-low {
1431 temperature = <40000>;
1432 hysteresis = <2000>;
1433 type = "active";
1434 };
1435 };
1436
1437 cooling-maps {
1438 cpu-active-high {
1439 /* active: set fan to cooling level 2 */
1440 cooling-device = <&fan 3 3>;
1441 trip = <&cpu_trip_active_high>;
1442 };
1443
1444 cpu-active-low {
1445 /* active: set fan to cooling level 1 */
1446 cooling-device = <&fan 2 2>;
1447 trip = <&cpu_trip_active_med>;
1448 };
1449
1450 cpu-passive {
1451 /* passive: set fan to cooling level 0 */
1452 cooling-device = <&fan 1 1>;
1453 trip = <&cpu_trip_active_low>;
1454 };
1455 };
1456 };
1457 };
1458
1459 timer {
1460 compatible = "arm,armv8-timer";
1461 interrupt-parent = <&gic>;
1462 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1463 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1464 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1465 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1466 };
1467 };
OpenWrt Source Repository