1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/reset/ti-syscon.h>
14 #include <dt-bindings/thermal/thermal.h>
17 compatible = "mediatek,mt7988";
18 interrupt-parent = <&gic>;
23 compatible = "mediatek,mt7988-cci",
24 "mediatek,mt8183-cci";
25 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
26 <&topckgen CLK_TOP_XTAL>;
27 clock-names = "cci", "intermediate";
28 operating-points-v2 = <&cci_opp>;
36 compatible = "arm,cortex-a73";
39 enable-method = "psci";
40 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
41 <&topckgen CLK_TOP_XTAL>;
42 clock-names = "cpu", "intermediate";
43 operating-points-v2 = <&cluster0_opp>;
44 mediatek,cci = <&cci>;
48 compatible = "arm,cortex-a73";
51 enable-method = "psci";
52 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
53 <&topckgen CLK_TOP_XTAL>;
54 clock-names = "cpu", "intermediate";
55 operating-points-v2 = <&cluster0_opp>;
56 mediatek,cci = <&cci>;
60 compatible = "arm,cortex-a73";
63 enable-method = "psci";
64 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
65 <&topckgen CLK_TOP_XTAL>;
66 clock-names = "cpu", "intermediate";
67 operating-points-v2 = <&cluster0_opp>;
68 mediatek,cci = <&cci>;
72 compatible = "arm,cortex-a73";
75 enable-method = "psci";
76 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
77 <&topckgen CLK_TOP_XTAL>;
78 clock-names = "cpu", "intermediate";
79 operating-points-v2 = <&cluster0_opp>;
80 mediatek,cci = <&cci>;
83 cluster0_opp: opp_table0 {
84 compatible = "operating-points-v2";
88 opp-hz = /bits/ 64 <800000000>;
89 opp-microvolt = <850000>;
93 opp-hz = /bits/ 64 <1100000000>;
94 opp-microvolt = <850000>;
98 opp-hz = /bits/ 64 <1500000000>;
99 opp-microvolt = <850000>;
103 opp-hz = /bits/ 64 <1800000000>;
104 opp-microvolt = <900000>;
109 cci_opp: opp_table_cci {
110 compatible = "operating-points-v2";
114 opp-hz = /bits/ 64 <480000000>;
115 opp-microvolt = <850000>;
119 opp-hz = /bits/ 64 <660000000>;
120 opp-microvolt = <850000>;
124 opp-hz = /bits/ 64 <900000000>;
125 opp-microvolt = <850000>;
129 opp-hz = /bits/ 64 <1080000000>;
130 opp-microvolt = <900000>;
134 clk40m: oscillator@0 {
135 compatible = "fixed-clock";
136 clock-frequency = <40000000>;
138 clock-output-names = "clkxtal";
142 compatible = "pwm-fan";
143 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
144 cooling-levels = <0 128 255>;
145 #cooling-cells = <2>;
146 #thermal-sensor-cells = <1>;
151 compatible = "arm,cortex-a73-pmu";
152 interrupt-parent = <&gic>;
153 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
157 compatible = "arm,psci-0.2";
161 reg_1p8v: regulator-1p8v {
162 compatible = "regulator-fixed";
163 regulator-name = "fixed-1.8V";
164 regulator-min-microvolt = <1800000>;
165 regulator-max-microvolt = <1800000>;
170 reg_3p3v: regulator-3p3v {
171 compatible = "regulator-fixed";
172 regulator-name = "fixed-3.3V";
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
181 #address-cells = <2>;
184 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
185 secmon_reserved: secmon@43000000 {
186 reg = <0 0x43000000 0 0x50000>;
192 compatible = "simple-bus";
194 #address-cells = <2>;
197 gic: interrupt-controller@c000000 {
198 compatible = "arm,gic-v3";
199 reg = <0 0x0c000000 0 0x40000>, /* GICD */
200 <0 0x0c080000 0 0x200000>, /* GICR */
201 <0 0x0c400000 0 0x2000>, /* GICC */
202 <0 0x0c410000 0 0x1000>, /* GICH */
203 <0 0x0c420000 0 0x2000>; /* GICV */
204 interrupt-parent = <&gic>;
205 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
206 interrupt-controller;
207 #interrupt-cells = <3>;
210 phyfw: phy-firmware@f000000 {
211 compatible = "mediatek,2p5gphy-fw";
212 reg = <0 0x0f000000 0 0x8000>,
213 <0 0x0f100000 0 0x20000>,
214 <0 0x0f0f0000 0 0x200>;
217 infracfg: infracfg@10001000 {
218 compatible = "mediatek,mt7988-infracfg", "syscon";
219 reg = <0 0x10001000 0 0x1000>;
223 topckgen: topckgen@1001b000 {
224 compatible = "mediatek,mt7988-topckgen", "syscon";
225 reg = <0 0x1001b000 0 0x1000>;
229 watchdog: watchdog@1001c000 {
230 compatible = "mediatek,mt7988-wdt",
231 "mediatek,mt6589-wdt",
233 reg = <0 0x1001c000 0 0x1000>;
234 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
238 apmixedsys: apmixedsys@1001e000 {
239 compatible = "mediatek,mt7988-apmixedsys";
240 reg = <0 0x1001e000 0 0x1000>;
244 pio: pinctrl@1001f000 {
245 compatible = "mediatek,mt7988-pinctrl", "syscon";
246 reg = <0 0x1001f000 0 0x1000>,
247 <0 0x11c10000 0 0x1000>,
248 <0 0x11d00000 0 0x1000>,
249 <0 0x11d20000 0 0x1000>,
250 <0 0x11e00000 0 0x1000>,
251 <0 0x11f00000 0 0x1000>,
252 <0 0x1000b000 0 0x1000>;
253 reg-names = "gpio_base", "iocfg_tr_base",
254 "iocfg_br_base", "iocfg_rb_base",
255 "iocfg_lb_base", "iocfg_tl_base", "eint";
258 gpio-ranges = <&pio 0 0 84>;
259 interrupt-controller;
260 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-parent = <&gic>;
262 #interrupt-cells = <2>;
264 mdio0_pins: mdio0-pins {
267 groups = "mdc_mdio0";
271 groups = "mdc_mdio0";
272 drive-strength = <MTK_DRIVE_8mA>;
276 i2c0_pins: i2c0-pins-g0 {
283 i2c1_pins: i2c1-pins-g0 {
290 i2c1_sfp_pins: i2c1-sfp-pins-g0 {
297 i2c2_pins: i2c2-pins {
304 i2c2_0_pins: i2c2-pins-g0 {
311 i2c2_1_pins: i2c2-pins-g1 {
318 gbe0_led0_pins: gbe0-led0-pins {
321 groups = "gbe0_led0";
325 gbe1_led0_pins: gbe1-led0-pins {
328 groups = "gbe1_led0";
332 gbe2_led0_pins: gbe2-led0-pins {
335 groups = "gbe2_led0";
339 gbe3_led0_pins: gbe3-led0-pins {
342 groups = "gbe3_led0";
346 gbe0_led1_pins: gbe0-led1-pins {
349 groups = "gbe0_led1";
353 gbe1_led1_pins: gbe1-led1-pins {
356 groups = "gbe1_led1";
360 gbe2_led1_pins: gbe2-led1-pins {
363 groups = "gbe2_led1";
367 gbe3_led1_pins: gbe3-led1-pins {
370 groups = "gbe3_led1";
374 i2p5gbe_led0_pins: 2p5gbe-led0-pins {
377 groups = "2p5gbe_led0";
381 i2p5gbe_led1_pins: 2p5gbe-led1-pins {
384 groups = "2p5gbe_led1";
388 mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
395 mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
402 mmc0_pins_sdcard: mmc0-pins-sdcard {
409 uart0_pins: uart0-pins {
416 snfi_pins: snfi-pins {
423 spi0_pins: spi0-pins {
430 spi0_flash_pins: spi0-flash-pins {
433 groups = "spi0", "spi0_wp_hold";
437 spi1_pins: spi1-pins {
444 spi2_pins: spi2-pins {
451 spi2_flash_pins: spi2-flash-pins {
454 groups = "spi2", "spi2_wp_hold";
458 pcie0_pins: pcie0-pins {
461 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
466 pcie1_pins: pcie1-pins {
469 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
474 pcie2_pins: pcie2-pins {
477 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
482 pcie3_pins: pcie3-pins {
485 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
492 compatible = "mediatek,mt7988-pwm";
493 reg = <0 0x10048000 0 0x1000>;
495 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
496 <&infracfg CLK_INFRA_66M_PWM_HCK>,
497 <&infracfg CLK_INFRA_66M_PWM_CK1>,
498 <&infracfg CLK_INFRA_66M_PWM_CK2>,
499 <&infracfg CLK_INFRA_66M_PWM_CK3>,
500 <&infracfg CLK_INFRA_66M_PWM_CK4>,
501 <&infracfg CLK_INFRA_66M_PWM_CK5>,
502 <&infracfg CLK_INFRA_66M_PWM_CK6>,
503 <&infracfg CLK_INFRA_66M_PWM_CK7>,
504 <&infracfg CLK_INFRA_66M_PWM_CK8>;
505 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
506 "pwm4","pwm5","pwm6","pwm7","pwm8";
510 sgmiisys0: syscon@10060000 {
511 compatible = "mediatek,mt7988-sgmiisys",
512 "mediatek,mt7988-sgmiisys_0",
514 reg = <0 0x10060000 0 0x1000>;
518 sgmiisys1: syscon@10070000 {
519 compatible = "mediatek,mt7988-sgmiisys",
520 "mediatek,mt7988-sgmiisys_1",
522 reg = <0 0x10070000 0 0x1000>;
526 usxgmiisys0: usxgmiisys@10080000 {
527 compatible = "mediatek,mt7988-usxgmiisys",
528 "mediatek,mt7988-usxgmiisys_0",
530 reg = <0 0x10080000 0 0x1000>;
534 usxgmiisys1: usxgmiisys@10081000 {
535 compatible = "mediatek,mt7988-usxgmiisys",
536 "mediatek,mt7988-usxgmiisys_1",
538 reg = <0 0x10081000 0 0x1000>;
542 mcusys: mcusys@100e0000 {
543 compatible = "mediatek,mt7988-mcusys", "syscon";
544 reg = <0 0x100e0000 0 0x1000>;
548 uart0: serial@11000000 {
549 compatible = "mediatek,mt7986-uart",
550 "mediatek,mt6577-uart";
551 reg = <0 0x11000000 0 0x100>;
552 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
554 * 8250-mtk driver don't control "baud" clock since commit
555 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
556 * still need to be passed to the driver to prevent probe fail
558 clocks = <&topckgen CLK_TOP_UART_SEL>,
559 <&infracfg CLK_INFRA_52M_UART0_CK>;
560 clock-names = "baud", "bus";
561 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
562 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
563 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
564 <&topckgen CLK_TOP_UART_SEL>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&uart0_pins>;
570 snand: spi@11001000 {
571 compatible = "mediatek,mt7986-snand";
572 reg = <0 0x11001000 0 0x1000>;
573 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&infracfg CLK_INFRA_SPINFI>,
575 <&infracfg CLK_INFRA_NFI>;
576 clock-names = "pad_clk", "nfi_clk";
577 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
578 <&topckgen CLK_TOP_NFI1X_SEL>;
579 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
580 <&topckgen CLK_TOP_MPLL_D8>;
581 nand-ecc-engine = <&bch>;
583 #address-cells = <1>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&snfi_pins>;
591 compatible = "mediatek,mt7686-ecc";
592 reg = <0 0x11002000 0 0x1000>;
593 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
595 clock-names = "nfiecc_clk";
600 compatible = "mediatek,mt7988-i2c",
601 "mediatek,mt7981-i2c";
602 reg = <0 0x11003000 0 0x1000>,
603 <0 0x10217080 0 0x80>;
604 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
607 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
608 clock-names = "main", "dma";
609 #address-cells = <1>;
615 compatible = "mediatek,mt7988-i2c",
616 "mediatek,mt7981-i2c";
617 reg = <0 0x11004000 0 0x1000>,
618 <0 0x10217100 0 0x80>;
619 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
622 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
623 clock-names = "main", "dma";
624 #address-cells = <1>;
630 compatible = "mediatek,mt7988-i2c",
631 "mediatek,mt7981-i2c";
632 reg = <0 0x11005000 0 0x1000>,
633 <0 0x10217180 0 0x80>;
634 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
637 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
638 clock-names = "main", "dma";
639 #address-cells = <1>;
645 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
646 reg = <0 0x11007000 0 0x100>;
647 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&topckgen CLK_TOP_MPLL_D2>,
649 <&topckgen CLK_TOP_SPI_SEL>,
650 <&infracfg CLK_INFRA_104M_SPI0>,
651 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
652 clock-names = "parent-clk", "sel-clk", "spi-clk",
654 #address-cells = <1>;
660 compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
661 reg = <0 0x11008000 0 0x100>;
662 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&topckgen CLK_TOP_MPLL_D2>,
664 <&topckgen CLK_TOP_SPI_SEL>,
665 <&infracfg CLK_INFRA_104M_SPI1>,
666 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
667 clock-names = "parent-clk", "sel-clk", "spi-clk",
669 #address-cells = <1>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&spi1_pins>;
677 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
678 reg = <0 0x11009000 0 0x100>;
679 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&topckgen CLK_TOP_MPLL_D2>,
681 <&topckgen CLK_TOP_SPI_SEL>,
682 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
683 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
684 clock-names = "parent-clk", "sel-clk", "spi-clk",
686 #address-cells = <1>;
691 lvts: lvts@1100a000 {
692 compatible = "mediatek,mt7988-lvts-ap";
693 reg = <0 0x1100a000 0 0x1000>;
694 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
695 clock-names = "lvts_clk";
696 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
697 resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
698 nvmem-cells = <&lvts_calibration>;
699 nvmem-cell-names = "lvts-calib-data-1";
700 #thermal-sensor-cells = <1>;
703 ssusb0: usb@11190000 {
704 compatible = "mediatek,mt7988-xhci",
706 reg = <0 0x11190000 0 0x2e00>,
707 <0 0x11193e00 0 0x0100>;
708 reg-names = "mac", "ippc";
709 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
710 phys = <&xphyu2port0 PHY_TYPE_USB2>,
711 <&xphyu3port0 PHY_TYPE_USB3>;
712 clocks = <&infracfg CLK_INFRA_USB_SYS>,
713 <&infracfg CLK_INFRA_USB_XHCI>,
714 <&infracfg CLK_INFRA_USB_REF>,
715 <&infracfg CLK_INFRA_66M_USB_HCK>,
716 <&infracfg CLK_INFRA_133M_USB_HCK>;
717 clock-names = "sys_ck",
722 #address-cells = <2>;
724 mediatek,p0_speed_fixup;
728 ssusb1: usb@11200000 {
729 compatible = "mediatek,mt7988-xhci",
731 reg = <0 0x11200000 0 0x2e00>,
732 <0 0x11203e00 0 0x0100>;
733 reg-names = "mac", "ippc";
734 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
735 phys = <&tphyu2port0 PHY_TYPE_USB2>,
736 <&tphyu3port0 PHY_TYPE_USB3>;
737 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
738 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
739 <&infracfg CLK_INFRA_USB_CK_P1>,
740 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
741 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
742 clock-names = "sys_ck",
747 #address-cells = <2>;
752 afe: audio-controller@11210000 {
753 compatible = "mediatek,mt79xx-audio";
754 reg = <0 0x11210000 0 0x9000>;
755 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
757 <&infracfg CLK_INFRA_AUD_26M>,
758 <&infracfg CLK_INFRA_AUD_L>,
759 <&infracfg CLK_INFRA_AUD_AUD>,
760 <&infracfg CLK_INFRA_AUD_EG2>,
761 <&topckgen CLK_TOP_AUD_SEL>,
762 <&topckgen CLK_TOP_AUD_I2S_M>;
763 clock-names = "aud_bus_ck",
770 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
771 <&topckgen CLK_TOP_A1SYS_SEL>,
772 <&topckgen CLK_TOP_AUD_L_SEL>,
773 <&topckgen CLK_TOP_A_TUNER_SEL>;
774 assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
775 <&topckgen CLK_TOP_APLL2_D4>,
776 <&apmixedsys CLK_APMIXED_APLL2>,
777 <&topckgen CLK_TOP_APLL2_D4>;
782 compatible = "mediatek,mt7986-mmc",
783 "mediatek,mt7981-mmc";
784 reg = <0 0x11230000 0 0x1000>,
785 <0 0x11D60000 0 0x1000>;
786 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&infracfg CLK_INFRA_MSDC400>,
788 <&infracfg CLK_INFRA_MSDC2_HCK>,
789 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
790 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
791 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
792 <&topckgen CLK_TOP_EMMC_400M_SEL>;
793 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
794 <&apmixedsys CLK_APMIXED_MSDCPLL>;
795 clock-names = "source",
799 #address-cells = <1>;
804 pcie2: pcie@11280000 {
805 compatible = "mediatek,mt7988-pcie",
806 "mediatek,mt7986-pcie",
807 "mediatek,mt8192-pcie";
808 reg = <0 0x11280000 0 0x2000>;
809 reg-names = "pcie-mac";
810 ranges = <0x81000000 0x00 0x20000000 0x00
811 0x20000000 0x00 0x00200000>,
812 <0x82000000 0x00 0x20200000 0x00
813 0x20200000 0x00 0x07e00000>;
815 linux,pci-domain = <3>;
816 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
817 bus-range = <0x00 0xff>;
818 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
819 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
820 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
821 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
822 clock-names = "pl_250m", "tl_26m", "peri_26m",
824 pinctrl-names = "default";
825 pinctrl-0 = <&pcie2_pins>;
826 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
827 phy-names = "pcie-phy";
828 #interrupt-cells = <1>;
829 interrupt-map-mask = <0 0 0 0x7>;
830 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
831 <0 0 0 2 &pcie_intc2 1>,
832 <0 0 0 3 &pcie_intc2 2>,
833 <0 0 0 4 &pcie_intc2 3>;
834 #address-cells = <3>;
838 pcie_intc2: interrupt-controller {
839 #address-cells = <0>;
840 #interrupt-cells = <1>;
841 interrupt-controller;
845 pcie3: pcie@11290000 {
846 compatible = "mediatek,mt7988-pcie",
847 "mediatek,mt7986-pcie",
848 "mediatek,mt8192-pcie";
849 reg = <0 0x11290000 0 0x2000>;
850 reg-names = "pcie-mac";
851 ranges = <0x81000000 0x00 0x28000000 0x00
852 0x28000000 0x00 0x00200000>,
853 <0x82000000 0x00 0x28200000 0x00
854 0x28200000 0x00 0x07e00000>;
856 linux,pci-domain = <2>;
857 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
858 bus-range = <0x00 0xff>;
859 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
860 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
861 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
862 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
863 clock-names = "pl_250m", "tl_26m", "peri_26m",
865 pinctrl-names = "default";
866 pinctrl-0 = <&pcie3_pins>;
867 #interrupt-cells = <1>;
868 interrupt-map-mask = <0 0 0 0x7>;
869 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
870 <0 0 0 2 &pcie_intc3 1>,
871 <0 0 0 3 &pcie_intc3 2>,
872 <0 0 0 4 &pcie_intc3 3>;
873 #address-cells = <3>;
877 pcie_intc3: interrupt-controller {
878 #address-cells = <0>;
879 #interrupt-cells = <1>;
880 interrupt-controller;
884 pcie0: pcie@11300000 {
885 compatible = "mediatek,mt7988-pcie",
886 "mediatek,mt7986-pcie",
887 "mediatek,mt8192-pcie";
888 reg = <0 0x11300000 0 0x2000>;
889 reg-names = "pcie-mac";
890 ranges = <0x81000000 0x00 0x30000000 0x00
891 0x30000000 0x00 0x00200000>,
892 <0x82000000 0x00 0x30200000 0x00
893 0x30200000 0x00 0x07e00000>;
895 linux,pci-domain = <0>;
896 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
897 bus-range = <0x00 0xff>;
898 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
899 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
900 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
901 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
902 clock-names = "pl_250m", "tl_26m", "peri_26m",
904 pinctrl-names = "default";
905 pinctrl-0 = <&pcie0_pins>;
906 #interrupt-cells = <1>;
907 interrupt-map-mask = <0 0 0 0x7>;
908 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
909 <0 0 0 2 &pcie_intc0 1>,
910 <0 0 0 3 &pcie_intc0 2>,
911 <0 0 0 4 &pcie_intc0 3>;
912 #address-cells = <3>;
916 pcie_intc0: interrupt-controller {
917 #address-cells = <0>;
918 #interrupt-cells = <1>;
919 interrupt-controller;
923 pcie1: pcie@11310000 {
924 compatible = "mediatek,mt7988-pcie",
925 "mediatek,mt7986-pcie",
926 "mediatek,mt8192-pcie";
927 reg = <0 0x11310000 0 0x2000>;
928 reg-names = "pcie-mac";
929 ranges = <0x81000000 0x00 0x38000000 0x00
930 0x38000000 0x00 0x00200000>,
931 <0x82000000 0x00 0x38200000 0x00
932 0x38200000 0x00 0x07e00000>;
934 linux,pci-domain = <1>;
935 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
936 bus-range = <0x00 0xff>;
937 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
938 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
939 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
940 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
941 clock-names = "pl_250m", "tl_26m", "peri_26m",
943 pinctrl-names = "default";
944 pinctrl-0 = <&pcie1_pins>;
945 #interrupt-cells = <1>;
946 interrupt-map-mask = <0 0 0 0x7>;
947 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
948 <0 0 0 2 &pcie_intc1 1>,
949 <0 0 0 3 &pcie_intc1 2>,
950 <0 0 0 4 &pcie_intc1 3>;
951 #address-cells = <3>;
955 pcie_intc1: interrupt-controller {
956 #address-cells = <0>;
957 #interrupt-cells = <1>;
958 interrupt-controller;
962 tphy: tphy@11c50000 {
963 compatible = "mediatek,mt7988",
964 "mediatek,generic-tphy-v2";
966 #address-cells = <2>;
970 tphyu2port0: usb-phy@11c50000 {
971 reg = <0 0x11c50000 0 0x700>;
972 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
977 tphyu3port0: usb-phy@11c50700 {
978 reg = <0 0x11c50700 0 0x900>;
979 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
982 mediatek,usb3-pll-ssc-delta;
983 mediatek,usb3-pll-ssc-delta1;
987 topmisc: topmisc@11d10000 {
988 compatible = "mediatek,mt7988-topmisc", "syscon",
989 "mediatek,mt7988-power-controller";
990 reg = <0 0x11d10000 0 0x10000>;
992 #power-domain-cells = <1>;
993 #address-cells = <1>;
997 xphy: xphy@11e10000 {
998 compatible = "mediatek,mt7988",
1001 #address-cells = <2>;
1003 status = "disabled";
1005 xphyu2port0: usb-phy@11e10000 {
1006 reg = <0 0x11e10000 0 0x400>;
1007 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
1008 clock-names = "ref";
1012 xphyu3port0: usb-phy@11e13000 {
1013 reg = <0 0x11e13400 0 0x500>;
1014 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
1015 clock-names = "ref";
1017 mediatek,syscon-type = <&topmisc 0x218 0>;
1021 xfi_pextp0: xfi-pextp@11f20000 {
1022 compatible = "mediatek,mt7988-xfi-pextp",
1023 "mediatek,mt7988-xfi-pextp_0",
1025 reg = <0 0x11f20000 0 0x10000>;
1029 xfi_pextp1: xfi-pextp@11f30000 {
1030 compatible = "mediatek,mt7988-xfi-pextp",
1031 "mediatek,mt7988-xfi-pextp_1",
1033 reg = <0 0x11f30000 0 0x10000>;
1037 xfi_pll: xfi-pll@11f40000 {
1038 compatible = "mediatek,mt7988-xfi-pll", "syscon";
1039 reg = <0 0x11f40000 0 0x1000>;
1043 efuse: efuse@11f50000 {
1044 compatible = "mediatek,efuse";
1045 reg = <0 0x11f50000 0 0x1000>;
1046 #address-cells = <1>;
1049 lvts_calibration: calib@918 {
1053 phy_calibration_p0: calib@940 {
1057 phy_calibration_p1: calib@954 {
1061 phy_calibration_p2: calib@968 {
1065 phy_calibration_p3: calib@97c {
1069 cpufreq_calibration: calib@278 {
1074 ethsys: syscon@15000000 {
1075 compatible = "mediatek,mt7988-ethsys", "syscon";
1076 reg = <0 0x15000000 0 0x1000>;
1079 #address-cells = <1>;
1083 switch: switch@15020000 {
1084 compatible = "mediatek,mt7988-switch";
1085 reg = <0 0x15020000 0 0x8000>;
1086 interrupt-controller;
1087 #interrupt-cells = <1>;
1088 interrupt-parent = <&gic>;
1089 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1090 resets = <ðrst 0>;
1091 #address-cells = <1>;
1095 #address-cells = <1>;
1101 phy-mode = "internal";
1102 phy-handle = <&gsw_phy0>;
1108 phy-mode = "internal";
1109 phy-handle = <&gsw_phy1>;
1115 phy-mode = "internal";
1116 phy-handle = <&gsw_phy2>;
1122 phy-mode = "internal";
1123 phy-handle = <&gsw_phy3>;
1128 ethernet = <&gmac0>;
1129 phy-mode = "internal";
1140 #address-cells = <1>;
1142 mediatek,pio = <&pio>;
1144 gsw_phy0: ethernet-phy@0 {
1145 compatible = "ethernet-phy-ieee802.3-c22";
1147 phy-mode = "internal";
1148 nvmem-cells = <&phy_calibration_p0>;
1149 nvmem-cell-names = "phy-cal-data";
1152 #address-cells = <1>;
1155 gsw_phy0_led0: gsw-phy0-led0@0 {
1157 function = LED_FUNCTION_LAN;
1158 status = "disabled";
1161 gsw_phy0_led1: gsw-phy0-led1@1 {
1163 function = LED_FUNCTION_LAN;
1164 status = "disabled";
1169 gsw_phy1: ethernet-phy@1 {
1170 compatible = "ethernet-phy-ieee802.3-c22";
1172 phy-mode = "internal";
1173 nvmem-cells = <&phy_calibration_p1>;
1174 nvmem-cell-names = "phy-cal-data";
1177 #address-cells = <1>;
1180 gsw_phy1_led0: gsw-phy1-led0@0 {
1182 function = LED_FUNCTION_LAN;
1183 status = "disabled";
1186 gsw_phy1_led1: gsw-phy1-led1@1 {
1188 function = LED_FUNCTION_LAN;
1189 status = "disabled";
1194 gsw_phy2: ethernet-phy@2 {
1195 compatible = "ethernet-phy-ieee802.3-c22";
1197 phy-mode = "internal";
1198 nvmem-cells = <&phy_calibration_p2>;
1199 nvmem-cell-names = "phy-cal-data";
1202 #address-cells = <1>;
1205 gsw_phy2_led0: gsw-phy2-led0@0 {
1207 function = LED_FUNCTION_LAN;
1208 status = "disabled";
1211 gsw_phy2_led1: gsw-phy2-led1@1 {
1213 function = LED_FUNCTION_LAN;
1214 status = "disabled";
1219 gsw_phy3: ethernet-phy@3 {
1220 compatible = "ethernet-phy-ieee802.3-c22";
1222 phy-mode = "internal";
1223 nvmem-cells = <&phy_calibration_p3>;
1224 nvmem-cell-names = "phy-cal-data";
1227 #address-cells = <1>;
1230 gsw_phy3_led0: gsw-phy3-led0@0 {
1232 function = LED_FUNCTION_LAN;
1233 status = "disabled";
1236 gsw_phy3_led1: gsw-phy3-led1@1 {
1238 function = LED_FUNCTION_LAN;
1239 status = "disabled";
1246 ethwarp: syscon@15031000 {
1247 compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
1248 reg = <0 0x15031000 0 0x1000>;
1251 ethrst: reset-controller {
1252 compatible = "ti,syscon-reset";
1255 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
1260 eth: ethernet@15100000 {
1261 compatible = "mediatek,mt7988-eth";
1262 reg = <0 0x15100000 0 0x80000>,
1263 <0 0x15400000 0 0x380000>;
1264 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <ðsys CLK_ETHDMA_XGP1_EN>,
1269 <ðsys CLK_ETHDMA_XGP2_EN>,
1270 <ðsys CLK_ETHDMA_XGP3_EN>,
1271 <ðsys CLK_ETHDMA_FE_EN>,
1272 <ðsys CLK_ETHDMA_GP2_EN>,
1273 <ðsys CLK_ETHDMA_GP1_EN>,
1274 <ðsys CLK_ETHDMA_GP3_EN>,
1275 <ðsys CLK_ETHDMA_ESW_EN>,
1276 <ðsys CLK_ETHDMA_CRYPT0_EN>,
1277 <&sgmiisys0 CLK_SGM0_TX_EN>,
1278 <&sgmiisys0 CLK_SGM0_RX_EN>,
1279 <&sgmiisys1 CLK_SGM1_TX_EN>,
1280 <&sgmiisys1 CLK_SGM1_RX_EN>,
1281 <ðwarp CLK_ETHWARP_WOCPU2_EN>,
1282 <ðwarp CLK_ETHWARP_WOCPU1_EN>,
1283 <ðwarp CLK_ETHWARP_WOCPU0_EN>,
1284 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1285 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1286 <&topckgen CLK_TOP_SGM_0_SEL>,
1287 <&topckgen CLK_TOP_SGM_1_SEL>,
1288 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
1289 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
1290 <&topckgen CLK_TOP_ETH_GMII_SEL>,
1291 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1292 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1293 <&topckgen CLK_TOP_ETH_SYS_SEL>,
1294 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1295 <&topckgen CLK_TOP_ETH_MII_SEL>,
1296 <&topckgen CLK_TOP_NETSYS_SEL>,
1297 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1298 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1299 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1300 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1301 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1302 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1303 "gp3", "esw", "crypto", "sgmii_tx250m",
1304 "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
1305 "ethwarp_wocpu2", "ethwarp_wocpu1",
1306 "ethwarp_wocpu0", "top_usxgmii0_sel",
1307 "top_usxgmii1_sel", "top_sgm0_sel",
1308 "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
1309 "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
1310 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1311 "top_eth_sys_sel", "top_eth_xgmii_sel",
1312 "top_eth_mii_sel", "top_netsys_sel",
1313 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1314 "top_netsys_sync_250m_sel",
1315 "top_netsys_ppefb_250m_sel",
1316 "top_netsys_warp_sel";
1317 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1318 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1319 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1320 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1321 <&topckgen CLK_TOP_SGM_0_SEL>,
1322 <&topckgen CLK_TOP_SGM_1_SEL>;
1323 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1324 <&topckgen CLK_TOP_NET1PLL_D4>,
1325 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1326 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1327 <&apmixedsys CLK_APMIXED_SGMPLL>,
1328 <&apmixedsys CLK_APMIXED_SGMPLL>;
1329 mediatek,ethsys = <ðsys>;
1330 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
1331 mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
1332 mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
1333 mediatek,xfi-pll = <&xfi_pll>;
1334 mediatek,infracfg = <&topmisc>;
1335 mediatek,toprgu = <&watchdog>;
1337 #address-cells = <1>;
1341 compatible = "mediatek,eth-mac";
1343 phy-mode = "internal";
1344 status = "disabled";
1354 compatible = "mediatek,eth-mac";
1356 status = "disabled";
1360 compatible = "mediatek,eth-mac";
1362 status = "disabled";
1365 mdio_bus: mdio-bus {
1366 #address-cells = <1>;
1369 /* internal 2.5G PHY */
1370 int_2p5g_phy: ethernet-phy@15 {
1371 compatible = "ethernet-phy-ieee802.3-c45";
1373 phy-mode = "internal";
1378 crypto: crypto@15600000 {
1379 compatible = "inside-secure,safexcel-eip197b";
1380 reg = <0 0x15600000 0 0x180000>;
1381 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1385 interrupt-names = "ring0", "ring1", "ring2", "ring3";
1391 cpu_thermal: cpu-thermal {
1392 polling-delay-passive = <1000>;
1393 polling-delay = <1000>;
1394 thermal-sensors = <&lvts 0>;
1397 cpu_trip_crit: crit {
1398 temperature = <125000>;
1399 hysteresis = <2000>;
1404 temperature = <120000>;
1405 hysteresis = <2000>;
1409 cpu_trip_active_high: active-high {
1410 temperature = <115000>;
1411 hysteresis = <2000>;
1415 cpu_trip_active_med: active-med {
1416 temperature = <85000>;
1417 hysteresis = <2000>;
1421 cpu_trip_active_low: active-low {
1422 temperature = <40000>;
1423 hysteresis = <2000>;
1430 /* active: set fan to cooling level 2 */
1431 cooling-device = <&fan 3 3>;
1432 trip = <&cpu_trip_active_high>;
1436 /* active: set fan to cooling level 1 */
1437 cooling-device = <&fan 2 2>;
1438 trip = <&cpu_trip_active_med>;
1442 /* passive: set fan to cooling level 0 */
1443 cooling-device = <&fan 1 1>;
1444 trip = <&cpu_trip_active_low>;
1451 compatible = "arm,armv8-timer";
1452 interrupt-parent = <&gic>;
1453 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1454 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1455 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1456 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;