1 // SPDX-License-Identifier: GPL-2.0+
2 #include <linux/bitfield.h>
3 #include <linux/firmware.h>
4 #include <linux/module.h>
5 #include <linux/nvmem-consumer.h>
6 #include <linux/of_address.h>
7 #include <linux/of_platform.h>
8 #include <linux/pinctrl/consumer.h>
11 #define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin"
12 #define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin"
14 #define MD32_EN_CFG 0x18
15 #define MD32_EN BIT(0)
17 #define BASE100T_STATUS_EXTEND 0x10
18 #define BASE1000T_STATUS_EXTEND 0x11
19 #define EXTEND_CTRL_AND_STATUS 0x16
21 #define PHY_AUX_CTRL_STATUS 0x1d
22 #define PHY_AUX_DPX_MASK GENMASK(5, 5)
23 #define PHY_AUX_SPEED_MASK GENMASK(4, 2)
25 /* Registers on MDIO_MMD_VEND1 */
26 #define MTK_PHY_LINK_STATUS_MISC 0xa2
27 #define MTK_PHY_FDX_ENABLE BIT(5)
29 /* Registers on MDIO_MMD_VEND2 */
30 #define MTK_PHY_LED0_ON_CTRL 0x24
31 #define MTK_PHY_LED0_ON_LINK1000 BIT(0)
32 #define MTK_PHY_LED0_ON_LINK100 BIT(1)
33 #define MTK_PHY_LED0_ON_LINK10 BIT(2)
34 #define MTK_PHY_LED0_ON_LINK2500 BIT(7)
35 #define MTK_PHY_LED0_POLARITY BIT(14)
37 #define MTK_PHY_LED1_ON_CTRL 0x26
38 #define MTK_PHY_LED1_ON_FDX BIT(4)
39 #define MTK_PHY_LED1_ON_HDX BIT(5)
40 #define MTK_PHY_LED1_POLARITY BIT(14)
49 static int mt798x_2p5ge_phy_config_init(struct phy_device
*phydev
)
53 const struct firmware
*fw
;
54 struct device
*dev
= &phydev
->mdio
.dev
;
55 struct device_node
*np
;
56 void __iomem
*dmb_addr
;
57 void __iomem
*pmb_addr
;
58 void __iomem
*mcucsr_base
;
60 struct pinctrl
*pinctrl
;
62 np
= of_find_compatible_node(NULL
, NULL
, "mediatek,2p5gphy-fw");
66 dmb_addr
= of_iomap(np
, 0);
69 pmb_addr
= of_iomap(np
, 1);
72 mcucsr_base
= of_iomap(np
, 2);
76 ret
= request_firmware(&fw
, MEDAITEK_2P5GE_PHY_DMB_FW
, dev
);
78 dev_err(dev
, "failed to load firmware: %s, ret: %d\n",
79 MEDAITEK_2P5GE_PHY_DMB_FW
, ret
);
82 for (i
= 0; i
< fw
->size
- 1; i
+= 4)
83 writel(*((uint32_t *)(fw
->data
+ i
)), dmb_addr
+ i
);
86 ret
= request_firmware(&fw
, MEDIATEK_2P5GE_PHY_PMB_FW
, dev
);
88 dev_err(dev
, "failed to load firmware: %s, ret: %d\n",
89 MEDIATEK_2P5GE_PHY_PMB_FW
, ret
);
92 for (i
= 0; i
< fw
->size
- 1; i
+= 4)
93 writel(*((uint32_t *)(fw
->data
+ i
)), pmb_addr
+ i
);
96 reg
= readw(mcucsr_base
+ MD32_EN_CFG
);
97 writew(reg
| MD32_EN
, mcucsr_base
+ MD32_EN_CFG
);
98 dev_dbg(dev
, "Firmware loading/trigger ok.\n");
101 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND2
, MTK_PHY_LED0_ON_CTRL
,
102 MTK_PHY_LED0_POLARITY
);
104 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND2
, MTK_PHY_LED0_ON_CTRL
,
105 MTK_PHY_LED0_ON_LINK10
|
106 MTK_PHY_LED0_ON_LINK100
|
107 MTK_PHY_LED0_ON_LINK1000
|
108 MTK_PHY_LED0_ON_LINK2500
);
110 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND2
, MTK_PHY_LED1_ON_CTRL
,
111 MTK_PHY_LED1_ON_FDX
| MTK_PHY_LED1_ON_HDX
);
113 pinctrl
= devm_pinctrl_get_select(&phydev
->mdio
.dev
, "i2p5gbe-led");
114 if (IS_ERR(pinctrl
)) {
115 dev_err(&phydev
->mdio
.dev
, "Fail to set LED pins!\n");
116 return PTR_ERR(pinctrl
);
122 static int mt798x_2p5ge_phy_config_aneg(struct phy_device
*phydev
)
124 bool changed
= false;
128 if (phydev
->autoneg
== AUTONEG_DISABLE
) {
129 /* Configure half duplex with genphy_setup_forced,
130 * because genphy_c45_pma_setup_forced does not support.
132 return phydev
->duplex
!= DUPLEX_FULL
133 ? genphy_setup_forced(phydev
)
134 : genphy_c45_pma_setup_forced(phydev
);
137 ret
= genphy_c45_an_config_aneg(phydev
);
143 adv
= linkmode_adv_to_mii_ctrl1000_t(phydev
->advertising
);
144 ret
= phy_modify_changed(phydev
, MII_CTRL1000
,
145 ADVERTISE_1000FULL
| ADVERTISE_1000HALF
,
152 return genphy_c45_check_and_restart_aneg(phydev
, changed
);
155 static int mt798x_2p5ge_phy_get_features(struct phy_device
*phydev
)
159 ret
= genphy_read_abilities(phydev
);
163 /* We don't support HDX at MAC layer on mt798x.
164 * So mask phy's HDX capabilities, too.
166 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT
,
168 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT
,
170 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT
,
172 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT
,
174 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT
, phydev
->supported
);
179 static int mt798x_2p5ge_phy_read_status(struct phy_device
*phydev
)
183 ret
= genphy_update_link(phydev
);
187 phydev
->speed
= SPEED_UNKNOWN
;
188 phydev
->duplex
= DUPLEX_UNKNOWN
;
190 phydev
->asym_pause
= 0;
195 if (phydev
->autoneg
== AUTONEG_ENABLE
&& phydev
->autoneg_complete
) {
196 ret
= genphy_c45_read_lpa(phydev
);
200 /* Read the link partner's 1G advertisement */
201 ret
= phy_read(phydev
, MII_STAT1000
);
204 mii_stat1000_mod_linkmode_lpa_t(phydev
->lp_advertising
, ret
);
205 } else if (phydev
->autoneg
== AUTONEG_DISABLE
) {
206 linkmode_zero(phydev
->lp_advertising
);
209 ret
= phy_read(phydev
, PHY_AUX_CTRL_STATUS
);
213 switch (FIELD_GET(PHY_AUX_SPEED_MASK
, ret
)) {
215 phydev
->speed
= SPEED_10
;
217 case PHY_AUX_SPD_100
:
218 phydev
->speed
= SPEED_100
;
220 case PHY_AUX_SPD_1000
:
221 phydev
->speed
= SPEED_1000
;
223 case PHY_AUX_SPD_2500
:
224 phydev
->speed
= SPEED_2500
;
225 phydev
->duplex
= DUPLEX_FULL
; /* 2.5G must be FDX */
229 ret
= phy_read_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_LINK_STATUS_MISC
);
233 phydev
->duplex
= (ret
& MTK_PHY_FDX_ENABLE
) ? DUPLEX_FULL
: DUPLEX_HALF
;
238 static struct phy_driver mtk_gephy_driver
[] = {
240 PHY_ID_MATCH_EXACT(0x00339c11),
241 .name
= "MediaTek MT798x 2.5GbE PHY",
242 .config_init
= mt798x_2p5ge_phy_config_init
,
243 .config_aneg
= mt798x_2p5ge_phy_config_aneg
,
244 .get_features
= mt798x_2p5ge_phy_get_features
,
245 .read_status
= mt798x_2p5ge_phy_read_status
,
249 module_phy_driver(mtk_gephy_driver
);
251 static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl
[] = {
252 { PHY_ID_MATCH_VENDOR(0x00339c00) },
256 MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
257 MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
258 MODULE_LICENSE("GPL");
260 MODULE_DEVICE_TABLE(mdio
, mtk_2p5ge_phy_tbl
);
261 MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW
);
262 MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW
);