ba19f69bbf07f5453b231ba076d16222c57642cc
[openwrt/openwrt.git] / target / linux / mediatek / files-6.6 / arch / arm64 / boot / dts / mediatek / mt7988a-bananapi-bpi-r4.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 /dts-v1/;
8 #include "mt7988a.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
13
14 / {
15 model = "Bananapi BPI-R4";
16 compatible = "bananapi,bpi-r4",
17 "mediatek,mt7988a";
18
19 aliases {
20 ethernet0 = &gmac0;
21 ethernet1 = &gmac1;
22 led-boot = &led_green;
23 led-failsafe = &led_green;
24 led-running = &led_green;
25 led-upgrade = &led_green;
26 serial0 = &uart0;
27 };
28
29 chosen {
30 stdout-path = &uart0;
31 bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0";
32 rootdisk-spim-nand = <&ubi_rootfs>;
33 };
34
35 memory {
36 reg = <0x00 0x40000000 0x00 0x10000000>;
37 };
38
39 /* SFP1 cage (WAN) */
40 sfp1: sfp1 {
41 compatible = "sff,sfp";
42 i2c-bus = <&i2c_sfp1>;
43 los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
44 mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
45 tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
46 tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
47 rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
48 maximum-power-milliwatt = <3000>;
49 };
50
51 gpio-keys {
52 compatible = "gpio-keys";
53
54 wps {
55 label = "WPS";
56 linux,code = <KEY_RESTART>;
57 gpios = <&pio 14 GPIO_ACTIVE_LOW>;
58 };
59 };
60
61 gpio-leds {
62 compatible = "gpio-leds";
63
64 led_green: led-green {
65 function = LED_FUNCTION_STATUS;
66 color = <LED_COLOR_ID_GREEN>;
67 gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
68 default-state = "on";
69 };
70
71 led_blue: led-blue {
72 function = LED_FUNCTION_WPS;
73 color = <LED_COLOR_ID_BLUE>;
74 gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
75 default-state = "off";
76 };
77 };
78 };
79
80 &eth {
81 status = "okay";
82 };
83
84 &gmac0 {
85 status = "okay";
86 };
87
88 &gmac2 {
89 sfp = <&sfp1>;
90 managed = "in-band-status";
91 phy-mode = "usxgmii";
92 status = "okay";
93 };
94
95 &switch {
96 status = "okay";
97 };
98
99 &gsw_phy0 {
100 pinctrl-names = "gbe-led";
101 pinctrl-0 = <&gbe0_led0_pins>;
102 };
103
104 &gsw_port0 {
105 label = "wan";
106 };
107
108 &gsw_phy0_led0 {
109 status = "okay";
110 color = <LED_COLOR_ID_GREEN>;
111 };
112
113 &gsw_phy1 {
114 pinctrl-names = "gbe-led";
115 pinctrl-0 = <&gbe1_led0_pins>;
116 };
117
118 &gsw_phy1_led0 {
119 status = "okay";
120 color = <LED_COLOR_ID_GREEN>;
121 };
122
123 &gsw_phy2 {
124 pinctrl-names = "gbe-led";
125 pinctrl-0 = <&gbe2_led0_pins>;
126 };
127
128 &gsw_phy2_led0 {
129 status = "okay";
130 color = <LED_COLOR_ID_GREEN>;
131 };
132
133 &gsw_phy3 {
134 pinctrl-names = "gbe-led";
135 pinctrl-0 = <&gbe3_led0_pins>;
136 };
137
138 &gsw_phy3_led0 {
139 status = "okay";
140 color = <LED_COLOR_ID_GREEN>;
141 };
142
143 &cpu0 {
144 proc-supply = <&rt5190_buck3>;
145 };
146
147 &cpu1 {
148 proc-supply = <&rt5190_buck3>;
149 };
150
151 &cpu2 {
152 proc-supply = <&rt5190_buck3>;
153 };
154
155 &cpu3 {
156 proc-supply = <&rt5190_buck3>;
157 };
158
159 &cci {
160 proc-supply = <&rt5190_buck3>;
161 };
162
163 &i2c0 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&i2c0_pins>;
166 status = "okay";
167
168 rt5190a_64: rt5190a@64 {
169 compatible = "richtek,rt5190a";
170 reg = <0x64>;
171 vin2-supply = <&rt5190_buck1>;
172 vin3-supply = <&rt5190_buck1>;
173 vin4-supply = <&rt5190_buck1>;
174
175 regulators {
176 rt5190_buck1: buck1 {
177 regulator-name = "rt5190a-buck1";
178 regulator-min-microvolt = <5090000>;
179 regulator-max-microvolt = <5090000>;
180 regulator-allowed-modes =
181 <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
182 regulator-boot-on;
183 regulator-always-on;
184 };
185 buck2 {
186 regulator-name = "vcore";
187 regulator-min-microvolt = <600000>;
188 regulator-max-microvolt = <1400000>;
189 regulator-boot-on;
190 regulator-always-on;
191 };
192 rt5190_buck3: buck3 {
193 regulator-name = "vproc";
194 regulator-min-microvolt = <600000>;
195 regulator-max-microvolt = <1400000>;
196 regulator-boot-on;
197 };
198 buck4 {
199 regulator-name = "rt5190a-buck4";
200 regulator-min-microvolt = <850000>;
201 regulator-max-microvolt = <850000>;
202 regulator-allowed-modes =
203 <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
204 regulator-boot-on;
205 regulator-always-on;
206 };
207 ldo {
208 regulator-name = "rt5190a-ldo";
209 regulator-min-microvolt = <1200000>;
210 regulator-max-microvolt = <1200000>;
211 regulator-boot-on;
212 regulator-always-on;
213 };
214 };
215 };
216 };
217
218 &i2c2 {
219 pinctrl-names = "default";
220 pinctrl-0 = <&i2c2_1_pins>;
221 status = "okay";
222
223 pca9545: i2c-switch@70 {
224 reg = <0x70>;
225 compatible = "nxp,pca9545";
226 reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
227 #address-cells = <1>;
228 #size-cells = <0>;
229
230 i2c_rtc: i2c@0 { //eeprom,rtc,ngff
231 #address-cells = <1>;
232 #size-cells = <0>;
233 reg = <0>;
234
235 eeprom@50 {
236 compatible = "atmel,24c02";
237 reg = <0x50>;
238 address-bits = <8>;
239 page-size = <8>;
240 size = <256>;
241 };
242
243 eeprom@57 {
244 compatible = "atmel,24c02";
245 reg = <0x57>;
246 address-bits = <8>;
247 page-size = <8>;
248 size = <256>;
249 };
250
251 pcf8563: rtc@51 {
252 compatible = "nxp,pcf8563";
253 reg = <0x51>;
254 status = "disabled";
255 };
256 };
257
258 i2c_sfp1: i2c@1 {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 reg = <1>;
262 };
263
264 i2c_wifi: i2c@3 {
265 #address-cells = <1>;
266 #size-cells = <0>;
267 reg = <3>;
268 };
269 };
270 };
271
272 /* mPCIe SIM2 */
273 &pcie0 {
274 pinctrl-names = "default";
275 pinctrl-0 = <&pcie0_pins>;
276 status = "okay";
277 };
278
279 /* mPCIe SIM3 */
280 &pcie1 {
281 pinctrl-names = "default";
282 pinctrl-0 = <&pcie1_pins>;
283 status = "okay";
284 };
285
286 /* M.2 key-B SIM1 */
287 &pcie2 {
288 pinctrl-names = "default";
289 pinctrl-0 = <&pcie2_pins>;
290 status = "okay";
291 };
292
293 /* M.2 key-M SSD */
294 &pcie3 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pcie3_pins>;
297 status = "okay";
298 };
299
300 &ssusb1 {
301 status = "okay";
302 };
303
304 &tphy {
305 status = "okay";
306 };
307
308 &spi0 {
309 pinctrl-names = "default";
310 pinctrl-0 = <&spi0_flash_pins>;
311 status = "okay";
312
313 spi_nand: spi_nand@0 {
314 compatible = "spi-nand";
315 reg = <0>;
316 spi-max-frequency = <52000000>;
317 spi-tx-buswidth = <4>;
318 spi-rx-buswidth = <4>;
319 };
320 };
321
322 &spi_nand {
323 partitions {
324 compatible = "fixed-partitions";
325 #address-cells = <1>;
326 #size-cells = <1>;
327
328 partition@0 {
329 label = "bl2";
330 reg = <0x0 0x200000>;
331 read-only;
332 };
333
334 partition@200000 {
335 label = "ubi";
336 reg = <0x200000 0x7e00000>;
337 compatible = "linux,ubi";
338
339 volumes {
340 ubi-volume-ubootenv {
341 volname = "ubootenv";
342 nvmem-layout {
343 compatible = "u-boot,env-redundant-bool-layout";
344 };
345 };
346
347 ubi-volume-ubootenv2 {
348 volname = "ubootenv2";
349 nvmem-layout {
350 compatible = "u-boot,env-redundant-bool-layout";
351 };
352 };
353
354 ubi_rootfs: ubi-volume-fit {
355 volname = "fit";
356 };
357 };
358 };
359 };
360 };
361
362 &uart0 {
363 status = "okay";
364 };
365
366 &uart1 {
367 status = "okay";
368 pinctrl-names = "default";
369 pinctrl-0 = <&uart1_2_lite_pins>;
370 };
371
372 &uart2 {
373 status = "okay";
374 pinctrl-names = "default";
375 pinctrl-0 = <&uart2_3_pins>;
376 };
377
378 &watchdog {
379 status = "okay";
380 };
381
382 &xphy {
383 status = "okay";
384 };