1 From 014330a304100782a26bc7df02778c8c386b2857 Mon Sep 17 00:00:00 2001
2 From: Sascha Hauer <s.hauer@pengutronix.de>
3 Date: Wed, 13 May 2015 10:52:42 +0200
4 Subject: [PATCH 23/76] thermal: Add Mediatek thermal controller support
6 This adds support for the Mediatek thermal controller found on MT8173
8 The controller is a bit special. It does not have its own ADC, instead
9 it controls the on-SoC AUXADC via AHB bus accesses. For this reason
10 we need the physical address of the AUXADC. Also it controls a mux
11 using AHB bus accesses, so we need the APMIXEDSYS physical address aswell.
13 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
15 drivers/thermal/Kconfig | 8 +
16 drivers/thermal/Makefile | 1 +
17 drivers/thermal/mtk_thermal.c | 728 +++++++++++++++++++++++++++++++++++++++++
18 3 files changed, 737 insertions(+)
19 create mode 100644 drivers/thermal/mtk_thermal.c
21 --- a/drivers/thermal/Kconfig
22 +++ b/drivers/thermal/Kconfig
23 @@ -285,6 +285,14 @@ config ACPI_THERMAL_REL
28 + tristate "Temperature sensor driver for mediatek SoCs"
29 + depends on ARCH_MEDIATEK || COMPILE_TEST
32 + Enable this option if you want to have support for thermal management
33 + controller present in Mediatek SoCs
35 menu "Texas Instruments thermal drivers"
36 source "drivers/thermal/ti-soc-thermal/Kconfig"
38 --- a/drivers/thermal/Makefile
39 +++ b/drivers/thermal/Makefile
40 @@ -39,3 +39,4 @@ obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-t
41 obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/
42 obj-$(CONFIG_ST_THERMAL) += st/
43 obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o
44 +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
46 +++ b/drivers/thermal/mtk_thermal.c
49 + * Copyright (c) 2014 MediaTek Inc.
50 + * Author: Hanyi.Wu <hanyi.wu@mediatek.com>
52 + * This program is free software; you can redistribute it and/or modify
53 + * it under the terms of the GNU General Public License version 2 as
54 + * published by the Free Software Foundation.
56 + * This program is distributed in the hope that it will be useful,
57 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
58 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
59 + * GNU General Public License for more details.
62 +#include <linux/kernel.h>
63 +#include <linux/module.h>
64 +#include <linux/dmi.h>
65 +#include <linux/thermal.h>
66 +#include <linux/platform_device.h>
67 +#include <linux/types.h>
68 +#include <linux/delay.h>
69 +#include <linux/slab.h>
70 +#include <linux/clk.h>
71 +#include <linux/time.h>
72 +#include <linux/of.h>
73 +#include <linux/of_irq.h>
74 +#include <linux/of_address.h>
75 +#include <linux/interrupt.h>
76 +#include <linux/reset.h>
78 +/* AUXADC Registers */
79 +#define AUXADC_CON0_V 0x000
80 +#define AUXADC_CON1_V 0x004
81 +#define AUXADC_CON1_SET_V 0x008
82 +#define AUXADC_CON1_CLR_V 0x00c
83 +#define AUXADC_CON2_V 0x010
84 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
85 +#define AUXADC_MISC_V 0x094
87 +#define AUXADC_CON1_CHANNEL(x) (1 << (x))
89 +/* Thermal Controller Registers */
90 +#define TEMPMONCTL0 0x000
91 +#define TEMPMONCTL1 0x004
92 +#define TEMPMONCTL2 0x008
93 +#define TEMPMONINT 0x00c
94 +#define TEMPMONINTSTS 0x010
95 +#define TEMPMONIDET0 0x014
96 +#define TEMPMONIDET1 0x018
97 +#define TEMPMONIDET2 0x01c
98 +#define TEMPH2NTHRE 0x024
99 +#define TEMPHTHRE 0x028
100 +#define TEMPCTHRE 0x02c
101 +#define TEMPOFFSETH 0x030
102 +#define TEMPOFFSETL 0x034
103 +#define TEMPMSRCTL0 0x038
104 +#define TEMPMSRCTL1 0x03c
105 +#define TEMPAHBPOLL 0x040
106 +#define TEMPAHBTO 0x044
107 +#define TEMPADCPNP0 0x048
108 +#define TEMPADCPNP1 0x04c
109 +#define TEMPADCPNP2 0x050
110 +#define TEMPADCPNP3 0x0b4
112 +#define TEMPADCMUX 0x054
113 +#define TEMPADCEXT 0x058
114 +#define TEMPADCEXT1 0x05c
115 +#define TEMPADCEN 0x060
116 +#define TEMPPNPMUXADDR 0x064
117 +#define TEMPADCMUXADDR 0x068
118 +#define TEMPADCEXTADDR 0x06c
119 +#define TEMPADCEXT1ADDR 0x070
120 +#define TEMPADCENADDR 0x074
121 +#define TEMPADCVALIDADDR 0x078
122 +#define TEMPADCVOLTADDR 0x07c
123 +#define TEMPRDCTRL 0x080
124 +#define TEMPADCVALIDMASK 0x084
125 +#define TEMPADCVOLTAGESHIFT 0x088
126 +#define TEMPADCWRITECTRL 0x08c
127 +#define TEMPMSR0 0x090
128 +#define TEMPMSR1 0x094
129 +#define TEMPMSR2 0x098
130 +#define TEMPMSR3 0x0B8
132 +#define TEMPIMMD0 0x0a0
133 +#define TEMPIMMD1 0x0a4
134 +#define TEMPIMMD2 0x0a8
136 +#define TEMPPROTCTL 0x0c0
137 +#define TEMPPROTTA 0x0c4
138 +#define TEMPPROTTB 0x0c8
139 +#define TEMPPROTTC 0x0cc
141 +#define TEMPSPARE0 0x0f0
142 +#define TEMPSPARE1 0x0f4
143 +#define TEMPSPARE2 0x0f8
144 +#define TEMPSPARE3 0x0fc
146 +#define PTPCORESEL 0x400
147 +#define THERMINTST 0x404
148 +#define PTPODINTST 0x408
149 +#define THSTAGE0ST 0x40c
150 +#define THSTAGE1ST 0x410
151 +#define THSTAGE2ST 0x414
152 +#define THAHBST0 0x418
153 +#define THAHBST1 0x41c /* Only for DE debug */
154 +#define PTPSPARE0 0x420
155 +#define PTPSPARE1 0x424
156 +#define PTPSPARE2 0x428
157 +#define PTPSPARE3 0x42c
158 +#define THSLPEVEB 0x430
160 +#define TEMPMONINT_COLD(sp) ((1 << 0) << ((sp) * 5))
161 +#define TEMPMONINT_HOT(sp) ((1 << 1) << ((sp) * 5))
162 +#define TEMPMONINT_LOW_OFS(sp) ((1 << 2) << ((sp) * 5))
163 +#define TEMPMONINT_HIGH_OFS(sp) ((1 << 3) << ((sp) * 5))
164 +#define TEMPMONINT_HOT_TO_NORM(sp) ((1 << 4) << ((sp) * 5))
165 +#define TEMPMONINT_TIMEOUT (1 << 15)
166 +#define TEMPMONINT_IMMEDIATE_SENSE(sp) (1 << (16 + (sp)))
167 +#define TEMPMONINT_FILTER_SENSE(sp) (1 << (19 + (sp)))
169 +#define TEMPADCWRITECTRL_ADC_PNP_WRITE (1 << 0)
170 +#define TEMPADCWRITECTRL_ADC_MUX_WRITE (1 << 1)
171 +#define TEMPADCWRITECTRL_ADC_EXTRA_WRITE (1 << 2)
172 +#define TEMPADCWRITECTRL_ADC_EXTRA1_WRITE (1 << 3)
174 +#define TEMPADCVALIDMASK_VALID_HIGH (1 << 5)
175 +#define TEMPADCVALIDMASK_VALID_POS(bit) (bit)
177 +#define TEMPPROTCTL_AVERAGE (0 << 16)
178 +#define TEMPPROTCTL_MAXIMUM (1 << 16)
179 +#define TEMPPROTCTL_SELECTED (2 << 16)
181 +#define MT8173_THERMAL_ZONE_CA57 0
182 +#define MT8173_THERMAL_ZONE_CA53 1
183 +#define MT8173_THERMAL_ZONE_GPU 2
184 +#define MT8173_THERMAL_ZONE_CORE 3
186 +#define MT8173_TS1 0
187 +#define MT8173_TS2 1
188 +#define MT8173_TS3 2
189 +#define MT8173_TS4 3
190 +#define MT8173_TSABB 4
192 +/* AUXADC channel 11 is used for the temperature sensors */
193 +#define MT8173_TEMP_AUXADC_CHANNEL 11
195 +/* The total number of temperature sensors in the MT8173 */
196 +#define MT8173_NUM_SENSORS 5
198 +/* The number of banks in the MT8173 */
199 +#define MT8173_NUM_BANKS 4
201 +/* The number of sensing points per bank */
202 +#define MT8173_NUM_SENSING_POINTS 4
204 +#define THERMAL_NAME "mtk-thermal"
208 +struct mtk_thermal_bank {
209 + struct mtk_thermal *mt;
210 + struct thermal_zone_device *tz;
214 +struct mtk_thermal {
215 + struct device *dev;
216 + void __iomem *thermal_base;
217 + void __iomem *auxadc_base;
219 + u64 auxadc_phys_base;
220 + u64 apmixed_phys_base;
221 + struct reset_control *reset;
222 + struct clk *clk_peri_therm;
223 + struct clk *clk_auxadc;
225 + struct mtk_thermal_bank banks[MT8173_NUM_BANKS];
229 + /* Calibration values */
237 +struct mtk_thermal_bank_cfg {
238 + unsigned int enable_mask;
239 + unsigned int sensors[4];
242 +static int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
245 + * The MT8173 thermal controller has four banks. Each bank can read up to
246 + * four temperature sensors simultaneously. The MT8173 has a total of 5
247 + * temperature sensors. We use each bank to measure a certain area of the
248 + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
249 + * areas, hence is used in different banks.
251 +static struct mtk_thermal_bank_cfg bank_data[] = {
254 + .sensors = { MT8173_TS2, MT8173_TS3 },
257 + .sensors = { MT8173_TS2, MT8173_TS4 },
260 + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
263 + .sensors = { MT8173_TS2 },
267 +static int tempmsr_ofs[MT8173_NUM_SENSING_POINTS] = {
268 + TEMPMSR0, TEMPMSR1, TEMPMSR2, TEMPMSR3
271 +static int tempadcpnp_ofs[MT8173_NUM_SENSING_POINTS] = {
272 + TEMPADCPNP0, TEMPADCPNP1, TEMPADCPNP2, TEMPADCPNP3
276 + * raw_to_mcelsius - convert a raw ADC value to mcelsius
277 + * @mt: The thermal controller
278 + * @raw: raw ADC value
280 + * This converts the raw ADC value to mcelsius using the SoC specific
281 + * calibration constants
283 +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw)
285 + s32 format_1, format_2, format_3, format_4;
291 + gain = (10000 + mt->adc_ge);
293 + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) /
296 + format_1 = ((mt->degc_cali * 10) >> 1);
297 + format_2 = (raw - mt->adc_oe);
298 + format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt;
299 + format_3 = format_3 * 15 / 18;
300 + format_4 = ((format_3 * 100) / (165 + mt->o_slope));
301 + format_4 = format_4 - (format_4 << 1);
303 + return (format_1 + format_4) * 100;
307 + * mcelsius_to_raw - convert mcelsius to raw ADC value
308 + * @mt: The thermal controller
309 + * @temp: The temperature in mcelsius
311 + * This converts a temperature in mcelsius to a raw ADC value, needed to
312 + * calculate the trigger values for interrupt generation.
314 +static u32 mcelsius_to_raw(struct mtk_thermal *mt, int temp)
316 + s32 format_1, format_2, format_3, format_4;
320 + gain = (10000 + mt->adc_ge);
322 + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) /
325 + format_1 = temp - (mt->degc_cali * 1000 / 2);
326 + format_2 = format_1 * (165 + mt->o_slope) * 18 / 15;
327 + format_2 = format_2 - 2 * format_2;
328 + format_3 = format_2 / 1000 + xtoomt * 10;
329 + format_4 = (format_3 * 4096 / 10000 * gain) / 100000 + mt->adc_oe;
335 + * mtk_thermal_get_bank - get bank
338 + * The bank registers are banked, we have to select a bank in the
339 + * PTPCORESEL register to access it.
341 +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
343 + struct mtk_thermal *mt = bank->mt;
346 + mutex_lock(&mt->lock);
348 + val = readl(mt->thermal_base + PTPCORESEL);
351 + writel(val, mt->thermal_base + PTPCORESEL);
355 + * mtk_thermal_put_bank - release bank
358 + * release a bank previously taken with mtk_thermal_get_bank,
360 +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
362 + struct mtk_thermal *mt = bank->mt;
364 + mutex_unlock(&mt->lock);
368 + * mtk_thermal_bank_temperature - get the temperature of a bank
371 + * The temperature of a bank is considered the maximum temperature of
372 + * the sensors associated to the bank.
374 +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
376 + struct mtk_thermal *mt = bank->mt;
380 + temp = max = -INT_MAX;
382 + for (i = 0; i < 4; i++) {
385 + if (!(bank_data[bank->id].enable_mask & (1 << i)))
388 + raw = readl(mt->thermal_base + tempmsr_ofs[i]);
390 + sensno = bank_data[bank->id].sensors[i];
391 + temp = raw_to_mcelsius(mt, raw);
400 +static void mtk_thermal_irq_bank(struct mtk_thermal_bank *bank)
402 + struct mtk_thermal *mt = bank->mt;
405 + bool update = false;
407 + mtk_thermal_get_bank(bank);
409 + irqstat = readl(mt->thermal_base + TEMPMONINTSTS);
411 + mtk_thermal_put_bank(bank);
413 + for (sp = 0; sp < 3; sp++) {
414 + if (irqstat & TEMPMONINT_LOW_OFS(sp)) {
416 + dev_vdbg(mt->dev, "bank %d sensor %d low offset interrupt\n",
420 + if (irqstat & TEMPMONINT_HIGH_OFS(sp)) {
422 + dev_vdbg(mt->dev, "bank %d sensor %d high offset interrupt\n",
428 + thermal_zone_device_update(bank->tz);
431 +static irqreturn_t mtk_thermal_irq(int irq, void *dev_id)
433 + struct mtk_thermal *mt = dev_id;
437 + irqstat = readl(mt->thermal_base + THERMINTST);
439 + dev_vdbg(mt->dev, "thermal_interrupt_handler : THERMINTST = 0x%x\n",
442 + for (i = 0; i < MT8173_NUM_BANKS; i++) {
443 + if (!(irqstat & (1 << i)))
444 + mtk_thermal_irq_bank(&mt->banks[i]);
447 + return IRQ_HANDLED;
450 +static int mtk_read_temp(void *data, int *temp)
452 + struct mtk_thermal_bank *bank = data;
454 + mtk_thermal_get_bank(bank);
456 + *temp = mtk_thermal_bank_temperature(bank);
458 + mtk_thermal_put_bank(bank);
463 +static int mtk_set_trips(void *data, int low, int high)
465 + struct mtk_thermal_bank *bank = data;
466 + struct mtk_thermal *mt = bank->mt;
468 + u32 val, enable_mask;
469 + u32 raw_low, raw_high;
471 + raw_low = mcelsius_to_raw(mt, low);
472 + raw_high = mcelsius_to_raw(mt, high);
474 + mtk_thermal_get_bank(bank);
476 + writel(0x0, mt->thermal_base + TEMPMONINT);
478 + writel(TEMPPROTCTL_SELECTED, mt->thermal_base + TEMPPROTCTL);
480 + writel(raw_low, mt->thermal_base + TEMPOFFSETL);
481 + writel(raw_high, mt->thermal_base + TEMPOFFSETH);
483 + enable_mask = readl(mt->thermal_base + TEMPMONCTL0);
486 + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++)
487 + if (enable_mask & (1 << i))
488 + val |= TEMPMONINT_LOW_OFS(i) | TEMPMONINT_HIGH_OFS(i);
490 + writel(val, mt->thermal_base + TEMPMONINT);
492 + mtk_thermal_put_bank(bank);
494 + dev_dbg(mt->dev, "new boundaries: %d (0x%04x) < x < %d (0x%04x)\n",
495 + low, mcelsius_to_raw(mt, low),
496 + high, mcelsius_to_raw(mt, high));
501 +static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
502 + .get_temp = mtk_read_temp,
503 + .set_trips = mtk_set_trips,
506 +static void mtk_thermal_init_bank(struct mtk_thermal_bank *bank)
508 + struct mtk_thermal *mt = bank->mt;
509 + struct mtk_thermal_bank_cfg *cfg = &bank_data[bank->id];
512 + mtk_thermal_get_bank(bank);
514 + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
515 + writel(0x0000000c, mt->thermal_base + TEMPMONCTL1);
518 + * filt interval is 1 * 46.540us = 46.54us,
519 + * sen interval is 429 * 46.540us = 19.96ms
521 + writel(0x000101ad, mt->thermal_base + TEMPMONCTL2);
523 + /* poll is set to 10u */
524 + writel(0x00000300, mt->thermal_base + TEMPAHBPOLL);
526 + /* temperature sampling control, 1 sample */
527 + writel(0x00000000, mt->thermal_base + TEMPMSRCTL0);
529 + /* exceed this polling time, IRQ would be inserted */
530 + writel(0xffffffff, mt->thermal_base + TEMPAHBTO);
532 + /* number of interrupts per event, 1 is enough */
533 + writel(0x0, mt->thermal_base + TEMPMONIDET0);
534 + writel(0x0, mt->thermal_base + TEMPMONIDET1);
537 + * The MT8173 thermal controller does not have its own ADC. Instead it
538 + * uses AHB bus accesses to control the AUXADC. To do this the thermal
539 + * controller has to be programmed with the physical addresses of the
540 + * AUXADC registers and with the various bit positions in the AUXADC.
541 + * Also the thermal controller controls a mux in the APMIXEDSYS register
546 + * this value will be stored to TEMPPNPMUXADDR (TEMPSPARE0)
547 + * automatically by hw
549 + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCMUX);
551 + /* AHB address for auxadc mux selection */
552 + writel(mt->auxadc_phys_base + 0x00c,
553 + mt->thermal_base + TEMPADCMUXADDR);
555 + /* AHB address for pnp sensor mux selection */
556 + writel(mt->apmixed_phys_base + 0x0604,
557 + mt->thermal_base + TEMPPNPMUXADDR);
559 + /* AHB value for auxadc enable */
560 + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCEN);
562 + /* AHB address for auxadc enable (channel 0 immediate mode selected) */
563 + writel(mt->auxadc_phys_base + AUXADC_CON1_SET_V,
564 + mt->thermal_base + TEMPADCENADDR);
566 + /* AHB address for auxadc valid bit */
567 + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
568 + mt->thermal_base + TEMPADCVALIDADDR);
570 + /* AHB address for auxadc voltage output */
571 + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
572 + mt->thermal_base + TEMPADCVOLTADDR);
574 + /* read valid & voltage are at the same register */
575 + writel(0x0, mt->thermal_base + TEMPRDCTRL);
577 + /* indicate where the valid bit is */
578 + writel(TEMPADCVALIDMASK_VALID_HIGH | TEMPADCVALIDMASK_VALID_POS(12),
579 + mt->thermal_base + TEMPADCVALIDMASK);
582 + writel(0x0, mt->thermal_base + TEMPADCVOLTAGESHIFT);
584 + /* enable auxadc mux write transaction */
585 + writel(TEMPADCWRITECTRL_ADC_MUX_WRITE,
586 + mt->thermal_base + TEMPADCWRITECTRL);
588 + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++)
589 + writel(sensor_mux_values[cfg->sensors[i]],
590 + mt->thermal_base + tempadcpnp_ofs[i]);
592 + writel(cfg->enable_mask, mt->thermal_base + TEMPMONCTL0);
594 + writel(TEMPADCWRITECTRL_ADC_PNP_WRITE | TEMPADCWRITECTRL_ADC_MUX_WRITE,
595 + mt->thermal_base + TEMPADCWRITECTRL);
597 + mtk_thermal_put_bank(bank);
600 +static u64 of_get_phys_base(struct device_node *np)
603 + const __be32 *regaddr_p;
605 + regaddr_p = of_get_address(np, 0, &size64, NULL);
607 + return OF_BAD_ADDR;
609 + return of_translate_address(np, regaddr_p);
612 +static int mtk_thermal_probe(struct platform_device *pdev)
615 + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
617 + struct mtk_thermal *mt;
618 + struct resource *res;
620 + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
624 + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
625 + if (IS_ERR(mt->clk_peri_therm))
626 + return PTR_ERR(mt->clk_peri_therm);
628 + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
629 + if (IS_ERR(mt->clk_auxadc))
630 + return PTR_ERR(mt->clk_auxadc);
632 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
633 + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
634 + if (IS_ERR(mt->thermal_base))
635 + return PTR_ERR(mt->thermal_base);
637 + mt->reset = devm_reset_control_get(&pdev->dev, "therm");
638 + if (IS_ERR(mt->reset)) {
639 + ret = PTR_ERR(mt->reset);
640 + dev_err(&pdev->dev, "cannot get reset: %d\n", ret);
644 + mutex_init(&mt->lock);
646 + mt->dev = &pdev->dev;
648 + auxadc = of_parse_phandle(np, "auxadc", 0);
650 + dev_err(&pdev->dev, "missing auxadc node\n");
654 + mt->auxadc_phys_base = of_get_phys_base(auxadc);
655 + if (mt->auxadc_phys_base == OF_BAD_ADDR) {
656 + dev_err(&pdev->dev, "Can't get auxadc phys address\n");
660 + apmixedsys = of_parse_phandle(np, "apmixedsys", 0);
662 + dev_err(&pdev->dev, "missing apmixedsys node\n");
666 + mt->apmixed_phys_base = of_get_phys_base(apmixedsys);
667 + if (mt->apmixed_phys_base == OF_BAD_ADDR) {
668 + dev_err(&pdev->dev, "Can't get auxadc phys address\n");
672 + irq = platform_get_irq(pdev, 0);
674 + dev_err(&pdev->dev, "Can't find irq\n");
678 + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, mtk_thermal_irq,
679 + IRQF_ONESHOT, THERMAL_NAME, mt);
681 + dev_err(&pdev->dev, "Can't request irq %d: %d\n", irq, ret);
685 + ret = clk_prepare_enable(mt->clk_auxadc);
687 + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
691 + reset_control_reset(mt->reset);
693 + ret = clk_prepare_enable(mt->clk_peri_therm);
695 + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
696 + goto err_enable_clk;
700 + * These calibration values should finally be provided by the
701 + * firmware or fuses. For now use default values.
703 + mt->adc_ge = ((512 - 512) * 10000) / 4096;
704 + mt->adc_oe = 512 - 512;
705 + mt->degc_cali = 40;
709 + for (i = 0; i < MT8173_NUM_BANKS; i++) {
710 + struct mtk_thermal_bank *bank = &mt->banks[i];
714 + mtk_thermal_init_bank(&mt->banks[i]);
717 + platform_set_drvdata(pdev, mt);
720 + * This is needed after initialising the banks because otherwise
721 + * the first temperature read contains bogus high temperatures which
722 + * immediately cause a system shutdown.
726 + for (i = 0; i < MT8173_NUM_BANKS; i++) {
727 + struct mtk_thermal_bank *bank = &mt->banks[i];
729 + bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank,
736 + clk_disable_unprepare(mt->clk_peri_therm);
741 +static int mtk_thermal_remove(struct platform_device *pdev)
743 + struct mtk_thermal *mt = platform_get_drvdata(pdev);
746 + for (i = 0; i < MT8173_NUM_BANKS; i++) {
747 + struct mtk_thermal_bank *bank = &mt->banks[i];
750 + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz);
753 + clk_disable_unprepare(mt->clk_peri_therm);
754 + clk_disable_unprepare(mt->clk_auxadc);
759 +static const struct of_device_id mtk_thermal_of_match[] = {
761 + .compatible = "mediatek,mt8173-thermal",
766 +static struct platform_driver mtk_thermal_driver = {
767 + .probe = mtk_thermal_probe,
768 + .remove = mtk_thermal_remove,
770 + .name = THERMAL_NAME,
771 + .of_match_table = mtk_thermal_of_match,
775 +module_platform_driver(mtk_thermal_driver);