target/linux/mediatek/patches/0032-dt-bindings-mediatek-Add-MT8173-cpufreq-driver-bindi.patch

   1 From d83532fe7eb9cc7b8cc39dd9f2bbd9873d4e390b Mon Sep 17 00:00:00 2001
   2 From: "pi-cheng.chen" <pi-cheng.chen@linaro.org>
   3 Date: Mon, 8 Jun 2015 20:29:20 +0800
   4 Subject: [PATCH 32/76] dt-bindings: mediatek: Add MT8173 cpufreq driver
   5  binding
   6
   7 This patch adds device tree binding document for MT8173 cpufreq driver.
   8
   9 Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  10 ---
  11  .../devicetree/bindings/cpufreq/cpufreq-mt8173.txt |  127 ++++++++++++++++++++
  12  1 file changed, 127 insertions(+)
  13  create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt
  14
  15 diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt
  16 new file mode 100644
  17 index 0000000..7708a65
  18 --- /dev/null
  19 +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt
  20 @@ -0,0 +1,127 @@
  21 +
  22 +Mediatek MT8173 cpufreq driver
  23 +-------------------
  24 +
  25 +Mediatek MT8173 cpufreq driver for CPU frequency scaling.
  26 +
  27 +Required properties:
  28 +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
  29 +- clock-names: Should contain the following:
  30 +       "cpu"           - The multiplexer for clock input of CPU cluster.
  31 +       "intermediate"  - A parent of "cpu" clock which is used as "intermediate" clock
  32 +                         source (usually MAINPLL) when the original CPU PLL is under
  33 +                         transition and not stable yet.
  34 +- operating-points: Table of frequencies and voltage CPU could be transitioned into,
  35 +                   Frequency should be in KHz units and voltage should be in microvolts.
  36 +- proc-supply: Regulator for Vproc of CPU cluster.
  37 +
  38 +Optional properties:
  39 +- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
  40 +              needs to do "voltage trace" to step by step scale up/down Vproc and
  41 +              Vsram to fit SoC specific needs. When absent, the voltage scaling
  42 +              flow is handled by hardware, hence no software "voltage trace" is
  43 +              needed.
  44 +
  45 +Example:
  46 +--------
  47 +       cpu0: cpu@0 {
  48 +               device_type = "cpu";
  49 +               compatible = "arm,cortex-a53";
  50 +               reg = <0x000>;
  51 +               enable-method = "psci";
  52 +               cpu-idle-states = <&CPU_SLEEP_0>;
  53 +               clocks = <&infracfg CLK_INFRA_CA53SEL>,
  54 +                        <&apmixedsys CLK_APMIXED_MAINPLL>;
  55 +               clock-names = "cpu", "intermediate";
  56 +               operating-points = <
  57 +                       507000  859000
  58 +                       702000  908000
  59 +                       1001000 983000
  60 +                       1105000 1009000
  61 +                       1183000 1028000
  62 +                       1404000 1083000
  63 +                       1508000 1109000
  64 +                       1573000 1125000
  65 +               >;
  66 +       };
  67 +
  68 +       cpu1: cpu@1 {
  69 +               device_type = "cpu";
  70 +               compatible = "arm,cortex-a53";
  71 +               reg = <0x001>;
  72 +               enable-method = "psci";
  73 +               cpu-idle-states = <&CPU_SLEEP_0>;
  74 +               clocks = <&infracfg CLK_INFRA_CA53SEL>,
  75 +                        <&apmixedsys CLK_APMIXED_MAINPLL>;
  76 +               clock-names = "cpu", "intermediate";
  77 +               operating-points = <
  78 +                       507000  859000
  79 +                       702000  908000
  80 +                       1001000 983000
  81 +                       1105000 1009000
  82 +                       1183000 1028000
  83 +                       1404000 1083000
  84 +                       1508000 1109000
  85 +                       1573000 1125000
  86 +               >;
  87 +       };
  88 +
  89 +       cpu2: cpu@100 {
  90 +               device_type = "cpu";
  91 +               compatible = "arm,cortex-a57";
  92 +               reg = <0x100>;
  93 +               enable-method = "psci";
  94 +               cpu-idle-states = <&CPU_SLEEP_0>;
  95 +               clocks = <&infracfg CLK_INFRA_CA57SEL>,
  96 +                        <&apmixedsys CLK_APMIXED_MAINPLL>;
  97 +               clock-names = "cpu", "intermediate";
  98 +               operating-points = <
  99 +                       507000  828000
 100 +                       702000  867000
 101 +                       1001000 927000
 102 +                       1209000 968000
 103 +                       1404000 1007000
 104 +                       1612000 1049000
 105 +                       1807000 1089000
 106 +                       1989000 1125000
 107 +               >;
 108 +       };
 109 +
 110 +       cpu3: cpu@101 {
 111 +               device_type = "cpu";
 112 +               compatible = "arm,cortex-a57";
 113 +               reg = <0x101>;
 114 +               enable-method = "psci";
 115 +               cpu-idle-states = <&CPU_SLEEP_0>;
 116 +               clocks = <&infracfg CLK_INFRA_CA57SEL>,
 117 +                        <&apmixedsys CLK_APMIXED_MAINPLL>;
 118 +               clock-names = "cpu", "intermediate";
 119 +               operating-points = <
 120 +                       507000  828000
 121 +                       702000  867000
 122 +                       1001000 927000
 123 +                       1209000 968000
 124 +                       1404000 1007000
 125 +                       1612000 1049000
 126 +                       1807000 1089000
 127 +                       1989000 1125000
 128 +               >;
 129 +       };
 130 +
 131 +       &cpu0 {
 132 +               proc-supply = <&mt6397_vpca15_reg>;
 133 +       };
 134 +
 135 +       &cpu1 {
 136 +               proc-supply = <&mt6397_vpca15_reg>;
 137 +       };
 138 +
 139 +       &cpu2 {
 140 +               proc-supply = <&da9211_vcpu_reg>;
 141 +               sram-supply = <&mt6397_vsramca7_reg>;
 142 +       };
 143 +
 144 +       &cpu3 {
 145 +               proc-supply = <&da9211_vcpu_reg>;
 146 +               sram-supply = <&mt6397_vsramca7_reg>;
 147 +       };
 148 --
 149 1.7.10.4
 150