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linux: add support of Synopsys ARCHS38-based boards
[openwrt/openwrt.git] / target / linux / mediatek / patches / 0035-mmc-mediatek-Add-Mediatek-MMC-driver.patch
1 From 0b71d2f1ee40313f58a3c6e9ed95add6f5a8192d Mon Sep 17 00:00:00 2001
2 From: Chaotian Jing <chaotian.jing@mediatek.com>
3 Date: Mon, 15 Jun 2015 19:20:48 +0800
4 Subject: [PATCH 35/76] mmc: mediatek: Add Mediatek MMC driver
5
6 Add Mediatek MMC driver code
7 Support eMMC/SD/SDIO
8
9 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
10 ---
11 drivers/mmc/host/Kconfig | 8 +
12 drivers/mmc/host/Makefile | 1 +
13 drivers/mmc/host/mtk-sd.c | 1378 +++++++++++++++++++++++++++++++++++++++++++++
14 include/linux/mmc/core.h | 1 +
15 4 files changed, 1388 insertions(+)
16 create mode 100644 drivers/mmc/host/mtk-sd.c
17
18 --- a/drivers/mmc/host/Kconfig
19 +++ b/drivers/mmc/host/Kconfig
20 @@ -800,3 +800,11 @@ config MMC_TOSHIBA_PCI
21 tristate "Toshiba Type A SD/MMC Card Interface Driver"
22 depends on PCI
23 help
24 +
25 +config MMC_MTK
26 + tristate "MediaTek SD/MMC Card Interface support"
27 + help
28 + This selects the MediaTek(R) Secure digital and Multimedia card Interface.
29 + If you have a machine with a integrated SD/MMC card reader, say Y or M here.
30 + This is needed if support for any SD/SDIO/MMC devices is required.
31 + If unsure, say N.
32 --- a/drivers/mmc/host/Makefile
33 +++ b/drivers/mmc/host/Makefile
34 @@ -20,6 +20,7 @@ obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci
35 obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
36 obj-$(CONFIG_MMC_WBSD) += wbsd.o
37 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
38 +obj-$(CONFIG_MMC_MTK) += mtk-sd.o
39 obj-$(CONFIG_MMC_OMAP) += omap.o
40 obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o
41 obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
42 --- /dev/null
43 +++ b/drivers/mmc/host/mtk-sd.c
44 @@ -0,0 +1,1378 @@
45 +/*
46 + * Copyright (c) 2014-2015 MediaTek Inc.
47 + * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
48 + *
49 + * This program is free software; you can redistribute it and/or modify
50 + * it under the terms of the GNU General Public License version 2 as
51 + * published by the Free Software Foundation.
52 + *
53 + * This program is distributed in the hope that it will be useful,
54 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
55 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
56 + * GNU General Public License for more details.
57 + */
58 +
59 +#include <linux/clk.h>
60 +#include <linux/delay.h>
61 +#include <linux/dma-mapping.h>
62 +#include <linux/ioport.h>
63 +#include <linux/irq.h>
64 +#include <linux/of_address.h>
65 +#include <linux/of_irq.h>
66 +#include <linux/of_gpio.h>
67 +#include <linux/pinctrl/consumer.h>
68 +#include <linux/platform_device.h>
69 +#include <linux/regulator/consumer.h>
70 +#include <linux/spinlock.h>
71 +
72 +#include <linux/mmc/card.h>
73 +#include <linux/mmc/core.h>
74 +#include <linux/mmc/host.h>
75 +#include <linux/mmc/mmc.h>
76 +#include <linux/mmc/sd.h>
77 +#include <linux/mmc/sdio.h>
78 +
79 +#define MAX_BD_NUM 1024
80 +
81 +/*--------------------------------------------------------------------------*/
82 +/* Common Definition */
83 +/*--------------------------------------------------------------------------*/
84 +#define MSDC_BUS_1BITS 0x0
85 +#define MSDC_BUS_4BITS 0x1
86 +#define MSDC_BUS_8BITS 0x2
87 +
88 +#define MSDC_BURST_64B 0x6
89 +
90 +/*--------------------------------------------------------------------------*/
91 +/* Register Offset */
92 +/*--------------------------------------------------------------------------*/
93 +#define MSDC_CFG 0x0
94 +#define MSDC_IOCON 0x04
95 +#define MSDC_PS 0x08
96 +#define MSDC_INT 0x0c
97 +#define MSDC_INTEN 0x10
98 +#define MSDC_FIFOCS 0x14
99 +#define SDC_CFG 0x30
100 +#define SDC_CMD 0x34
101 +#define SDC_ARG 0x38
102 +#define SDC_STS 0x3c
103 +#define SDC_RESP0 0x40
104 +#define SDC_RESP1 0x44
105 +#define SDC_RESP2 0x48
106 +#define SDC_RESP3 0x4c
107 +#define SDC_BLK_NUM 0x50
108 +#define SDC_ACMD_RESP 0x80
109 +#define MSDC_DMA_SA 0x90
110 +#define MSDC_DMA_CTRL 0x98
111 +#define MSDC_DMA_CFG 0x9c
112 +#define MSDC_PATCH_BIT 0xb0
113 +#define MSDC_PATCH_BIT1 0xb4
114 +#define MSDC_PAD_TUNE 0xec
115 +
116 +/*--------------------------------------------------------------------------*/
117 +/* Register Mask */
118 +/*--------------------------------------------------------------------------*/
119 +
120 +/* MSDC_CFG mask */
121 +#define MSDC_CFG_MODE (0x1 << 0) /* RW */
122 +#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
123 +#define MSDC_CFG_RST (0x1 << 2) /* RW */
124 +#define MSDC_CFG_PIO (0x1 << 3) /* RW */
125 +#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
126 +#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
127 +#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
128 +#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
129 +#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
130 +#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
131 +
132 +/* MSDC_IOCON mask */
133 +#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
134 +#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
135 +#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
136 +#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
137 +#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
138 +#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
139 +#define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
140 +#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
141 +#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
142 +#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
143 +#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
144 +#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
145 +#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
146 +#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
147 +#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
148 +#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
149 +
150 +/* MSDC_PS mask */
151 +#define MSDC_PS_CDEN (0x1 << 0) /* RW */
152 +#define MSDC_PS_CDSTS (0x1 << 1) /* R */
153 +#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
154 +#define MSDC_PS_DAT (0xff << 16) /* R */
155 +#define MSDC_PS_CMD (0x1 << 24) /* R */
156 +#define MSDC_PS_WP (0x1 << 31) /* R */
157 +
158 +/* MSDC_INT mask */
159 +#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
160 +#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
161 +#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
162 +#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
163 +#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
164 +#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
165 +#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
166 +#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
167 +#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
168 +#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
169 +#define MSDC_INT_CSTA (0x1 << 11) /* R */
170 +#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
171 +#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
172 +#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
173 +#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
174 +#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
175 +#define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
176 +#define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
177 +#define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
178 +
179 +/* MSDC_INTEN mask */
180 +#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
181 +#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
182 +#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
183 +#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
184 +#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
185 +#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
186 +#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
187 +#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
188 +#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
189 +#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
190 +#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
191 +#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
192 +#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
193 +#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
194 +#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
195 +#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
196 +#define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
197 +#define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
198 +#define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
199 +
200 +/* MSDC_FIFOCS mask */
201 +#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
202 +#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
203 +#define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
204 +
205 +/* SDC_CFG mask */
206 +#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
207 +#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
208 +#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
209 +#define SDC_CFG_SDIO (0x1 << 19) /* RW */
210 +#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
211 +#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
212 +#define SDC_CFG_DTOC (0xff << 24) /* RW */
213 +
214 +/* SDC_STS mask */
215 +#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
216 +#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
217 +#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
218 +
219 +/* MSDC_DMA_CTRL mask */
220 +#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
221 +#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
222 +#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
223 +#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
224 +#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
225 +#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
226 +
227 +/* MSDC_DMA_CFG mask */
228 +#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
229 +#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
230 +#define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
231 +#define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
232 +#define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
233 +
234 +/* MSDC_PATCH_BIT mask */
235 +#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
236 +#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
237 +#define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
238 +#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
239 +#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
240 +#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
241 +#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
242 +#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
243 +#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
244 +#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
245 +#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
246 +#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
247 +
248 +#define REQ_CMD_EIO (0x1 << 0)
249 +#define REQ_CMD_TMO (0x1 << 1)
250 +#define REQ_DAT_ERR (0x1 << 2)
251 +#define REQ_STOP_EIO (0x1 << 3)
252 +#define REQ_STOP_TMO (0x1 << 4)
253 +#define REQ_CMD_BUSY (0x1 << 5)
254 +
255 +#define MSDC_PREPARE_FLAG (0x1 << 0)
256 +#define MSDC_ASYNC_FLAG (0x1 << 1)
257 +#define MSDC_MMAP_FLAG (0x1 << 2)
258 +
259 +#define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
260 +#define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
261 +
262 +/*--------------------------------------------------------------------------*/
263 +/* Descriptor Structure */
264 +/*--------------------------------------------------------------------------*/
265 +struct mt_gpdma_desc {
266 + u32 gpd_info;
267 +#define GPDMA_DESC_HWO (0x1 << 0)
268 +#define GPDMA_DESC_BDP (0x1 << 1)
269 +#define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
270 +#define GPDMA_DESC_INT (0x1 << 16)
271 + u32 next;
272 + u32 ptr;
273 + u32 gpd_data_len;
274 +#define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
275 +#define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
276 + u32 arg;
277 + u32 blknum;
278 + u32 cmd;
279 +};
280 +
281 +struct mt_bdma_desc {
282 + u32 bd_info;
283 +#define BDMA_DESC_EOL (0x1 << 0)
284 +#define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
285 +#define BDMA_DESC_BLKPAD (0x1 << 17)
286 +#define BDMA_DESC_DWPAD (0x1 << 18)
287 + u32 next;
288 + u32 ptr;
289 + u32 bd_data_len;
290 +#define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
291 +};
292 +
293 +struct msdc_dma {
294 + struct scatterlist *sg; /* I/O scatter list */
295 + struct mt_gpdma_desc *gpd; /* pointer to gpd array */
296 + struct mt_bdma_desc *bd; /* pointer to bd array */
297 + dma_addr_t gpd_addr; /* the physical address of gpd array */
298 + dma_addr_t bd_addr; /* the physical address of bd array */
299 +};
300 +
301 +struct msdc_host {
302 + struct device *dev;
303 + struct mmc_host *mmc; /* mmc structure */
304 + int cmd_rsp;
305 +
306 + spinlock_t lock;
307 + struct mmc_request *mrq;
308 + struct mmc_command *cmd;
309 + struct mmc_data *data;
310 + int error;
311 +
312 + void __iomem *base; /* host base address */
313 +
314 + struct msdc_dma dma; /* dma channel */
315 + u64 dma_mask;
316 +
317 + u32 timeout_ns; /* data timeout ns */
318 + u32 timeout_clks; /* data timeout clks */
319 +
320 + struct pinctrl *pinctrl;
321 + struct pinctrl_state *pins_default;
322 + struct pinctrl_state *pins_uhs;
323 + struct delayed_work req_timeout;
324 + int irq; /* host interrupt */
325 +
326 + struct clk *src_clk; /* msdc source clock */
327 + struct clk *h_clk; /* msdc h_clk */
328 + u32 mclk; /* mmc subsystem clock frequency */
329 + u32 src_clk_freq; /* source clock frequency */
330 + u32 sclk; /* SD/MS bus clock frequency */
331 + bool ddr;
332 + bool vqmmc_enabled;
333 +};
334 +
335 +static void sdr_set_bits(void __iomem *reg, u32 bs)
336 +{
337 + u32 val = readl(reg);
338 +
339 + val |= bs;
340 + writel(val, reg);
341 +}
342 +
343 +static void sdr_clr_bits(void __iomem *reg, u32 bs)
344 +{
345 + u32 val = readl(reg);
346 +
347 + val &= ~bs;
348 + writel(val, reg);
349 +}
350 +
351 +static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
352 +{
353 + unsigned int tv = readl(reg);
354 +
355 + tv &= ~field;
356 + tv |= ((val) << (ffs((unsigned int)field) - 1));
357 + writel(tv, reg);
358 +}
359 +
360 +static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
361 +{
362 + unsigned int tv = readl(reg);
363 +
364 + *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
365 +}
366 +
367 +static void msdc_reset_hw(struct msdc_host *host)
368 +{
369 + u32 val;
370 +
371 + sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
372 + while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
373 + cpu_relax();
374 +
375 + sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
376 + while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
377 + cpu_relax();
378 +
379 + val = readl(host->base + MSDC_INT);
380 + writel(val, host->base + MSDC_INT);
381 +}
382 +
383 +static void msdc_cmd_next(struct msdc_host *host,
384 + struct mmc_request *mrq, struct mmc_command *cmd);
385 +
386 +static u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
387 + MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
388 + MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
389 +
390 +static u8 msdc_dma_calcs(u8 *buf, u32 len)
391 +{
392 + u32 i, sum = 0;
393 +
394 + for (i = 0; i < len; i++)
395 + sum += buf[i];
396 + return 0xff - (u8) sum;
397 +}
398 +
399 +static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
400 + struct mmc_data *data)
401 +{
402 + unsigned int j, dma_len;
403 + dma_addr_t dma_address;
404 + u32 dma_ctrl;
405 + struct scatterlist *sg;
406 + struct mt_gpdma_desc *gpd;
407 + struct mt_bdma_desc *bd;
408 +
409 + sg = data->sg;
410 +
411 + gpd = dma->gpd;
412 + bd = dma->bd;
413 +
414 + /* modify gpd */
415 + gpd->gpd_info |= GPDMA_DESC_HWO;
416 + gpd->gpd_info |= GPDMA_DESC_BDP;
417 + /* need to clear first. use these bits to calc checksum */
418 + gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
419 + gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
420 +
421 + /* modify bd */
422 + for_each_sg(data->sg, sg, data->sg_count, j) {
423 + dma_address = sg_dma_address(sg);
424 + dma_len = sg_dma_len(sg);
425 +
426 + /* init bd */
427 + bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
428 + bd[j].bd_info &= ~BDMA_DESC_DWPAD;
429 + bd[j].ptr = (u32)dma_address;
430 + bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
431 + bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
432 +
433 + if (j == data->sg_count - 1) /* the last bd */
434 + bd[j].bd_info |= BDMA_DESC_EOL;
435 + else
436 + bd[j].bd_info &= ~BDMA_DESC_EOL;
437 +
438 + /* checksume need to clear first */
439 + bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
440 + bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
441 + }
442 +
443 + sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
444 + dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
445 + dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
446 + dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
447 + writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
448 + writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA);
449 +}
450 +
451 +static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
452 +{
453 + struct mmc_data *data = mrq->data;
454 +
455 + if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
456 + bool read = (data->flags & MMC_DATA_READ) != 0;
457 +
458 + data->host_cookie |= MSDC_PREPARE_FLAG;
459 + data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
460 + read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
461 + }
462 +}
463 +
464 +static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
465 +{
466 + struct mmc_data *data = mrq->data;
467 +
468 + if (data->host_cookie & MSDC_ASYNC_FLAG)
469 + return;
470 +
471 + if (data->host_cookie & MSDC_PREPARE_FLAG) {
472 + bool read = (data->flags & MMC_DATA_READ) != 0;
473 +
474 + dma_unmap_sg(host->dev, data->sg, data->sg_len,
475 + read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
476 + data->host_cookie &= ~MSDC_PREPARE_FLAG;
477 + }
478 +}
479 +
480 +/* clock control primitives */
481 +static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
482 +{
483 + u32 timeout, clk_ns;
484 + u32 mode = 0;
485 +
486 + host->timeout_ns = ns;
487 + host->timeout_clks = clks;
488 + if (host->sclk == 0) {
489 + timeout = 0;
490 + } else {
491 + clk_ns = 1000000000UL / host->sclk;
492 + timeout = (ns + clk_ns - 1) / clk_ns + clks;
493 + /* in 1048576 sclk cycle unit */
494 + timeout = (timeout + (0x1 << 20) - 1) >> 20;
495 + sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
496 + /*DDR mode will double the clk cycles for data timeout */
497 + timeout = mode >= 2 ? timeout * 2 : timeout;
498 + timeout = timeout > 1 ? timeout - 1 : 0;
499 + timeout = timeout > 255 ? 255 : timeout;
500 + }
501 + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
502 +}
503 +
504 +static void msdc_gate_clock(struct msdc_host *host)
505 +{
506 + clk_disable_unprepare(host->src_clk);
507 + clk_disable_unprepare(host->h_clk);
508 +}
509 +
510 +static void msdc_ungate_clock(struct msdc_host *host)
511 +{
512 + clk_prepare_enable(host->h_clk);
513 + clk_prepare_enable(host->src_clk);
514 + while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
515 + cpu_relax();
516 +}
517 +
518 +static void msdc_set_mclk(struct msdc_host *host, int ddr, u32 hz)
519 +{
520 + u32 mode;
521 + u32 flags;
522 + u32 div;
523 + u32 sclk;
524 +
525 + if (!hz) {
526 + dev_dbg(host->dev, "set mclk to 0\n");
527 + host->mclk = 0;
528 + sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
529 + return;
530 + }
531 +
532 + flags = readl(host->base + MSDC_INTEN);
533 + sdr_clr_bits(host->base + MSDC_INTEN, flags);
534 + if (ddr) { /* may need to modify later */
535 + mode = 0x2; /* ddr mode and use divisor */
536 + if (hz >= (host->src_clk_freq >> 2)) {
537 + div = 0; /* mean div = 1/4 */
538 + sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
539 + } else {
540 + div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
541 + sclk = (host->src_clk_freq >> 2) / div;
542 + div = (div >> 1);
543 + }
544 + } else if (hz >= host->src_clk_freq) {
545 + mode = 0x1; /* no divisor */
546 + div = 0;
547 + sclk = host->src_clk_freq;
548 + } else {
549 + mode = 0x0; /* use divisor */
550 + if (hz >= (host->src_clk_freq >> 1)) {
551 + div = 0; /* mean div = 1/2 */
552 + sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
553 + } else {
554 + div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
555 + sclk = (host->src_clk_freq >> 2) / div;
556 + }
557 + }
558 + sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
559 + (mode << 8) | (div % 0xff));
560 + sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
561 + while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
562 + cpu_relax();
563 + host->sclk = sclk;
564 + host->mclk = hz;
565 + host->ddr = ddr;
566 + /* need because clk changed. */
567 + msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
568 + sdr_set_bits(host->base + MSDC_INTEN, flags);
569 +
570 + dev_dbg(host->dev, "sclk: %d, ddr: %d\n", host->sclk, ddr);
571 +}
572 +
573 +static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
574 + struct mmc_request *mrq, struct mmc_command *cmd)
575 +{
576 + u32 resp;
577 +
578 + switch (mmc_resp_type(cmd)) {
579 + /* Actually, R1, R5, R6, R7 are the same */
580 + case MMC_RSP_R1:
581 + resp = 0x1;
582 + break;
583 + case MMC_RSP_R1B:
584 + resp = 0x7;
585 + break;
586 + case MMC_RSP_R2:
587 + resp = 0x2;
588 + break;
589 + case MMC_RSP_R3:
590 + resp = 0x3;
591 + break;
592 + case MMC_RSP_NONE:
593 + default:
594 + resp = 0x0;
595 + break;
596 + }
597 +
598 + return resp;
599 +}
600 +
601 +static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
602 + struct mmc_request *mrq, struct mmc_command *cmd)
603 +{
604 + /* rawcmd :
605 + * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
606 + * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
607 + */
608 + u32 opcode = cmd->opcode;
609 + u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
610 + u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
611 +
612 + host->cmd_rsp = resp;
613 +
614 + if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
615 + opcode == MMC_STOP_TRANSMISSION)
616 + rawcmd |= (0x1 << 14);
617 + else if (opcode == SD_SWITCH_VOLTAGE)
618 + rawcmd |= (0x1 << 30);
619 + else if (opcode == SD_APP_SEND_SCR ||
620 + opcode == SD_APP_SEND_NUM_WR_BLKS ||
621 + (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
622 + (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
623 + (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
624 + rawcmd |= (0x1 << 11);
625 +
626 + if (cmd->data) {
627 + struct mmc_data *data = cmd->data;
628 +
629 + if (mmc_op_multi(opcode)) {
630 + if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
631 + !(mrq->sbc->arg & 0xFFFF0000))
632 + rawcmd |= 0x2 << 28; /* AutoCMD23 */
633 + }
634 +
635 + rawcmd |= ((data->blksz & 0xFFF) << 16);
636 + if (data->flags & MMC_DATA_WRITE)
637 + rawcmd |= (0x1 << 13);
638 + if (data->blocks > 1)
639 + rawcmd |= (0x2 << 11);
640 + else
641 + rawcmd |= (0x1 << 11);
642 + /* Always use dma mode */
643 + sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
644 +
645 + if (host->timeout_ns != data->timeout_ns ||
646 + host->timeout_clks != data->timeout_clks)
647 + msdc_set_timeout(host, data->timeout_ns,
648 + data->timeout_clks);
649 +
650 + writel(data->blocks, host->base + SDC_BLK_NUM);
651 + }
652 + return rawcmd;
653 +}
654 +
655 +static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
656 + struct mmc_command *cmd, struct mmc_data *data)
657 +{
658 + bool read;
659 +
660 + WARN_ON(host->data);
661 + host->data = data;
662 + read = data->flags & MMC_DATA_READ;
663 +
664 + mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
665 + msdc_dma_setup(host, &host->dma, data);
666 + sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
667 + sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
668 + dev_dbg(host->dev, "DMA start\n");
669 + dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
670 + __func__, cmd->opcode, data->blocks, read);
671 +}
672 +
673 +static int msdc_auto_cmd_done(struct msdc_host *host, int events,
674 + struct mmc_command *cmd)
675 +{
676 + u32 *rsp = cmd->resp;
677 +
678 + rsp[0] = readl(host->base + SDC_ACMD_RESP);
679 +
680 + if (events & MSDC_INT_ACMDRDY) {
681 + cmd->error = 0;
682 + } else {
683 + msdc_reset_hw(host);
684 + if (events & MSDC_INT_ACMDCRCERR) {
685 + cmd->error = -EILSEQ;
686 + host->error |= REQ_STOP_EIO;
687 + } else if (events & MSDC_INT_ACMDTMO) {
688 + cmd->error = -ETIMEDOUT;
689 + host->error |= REQ_STOP_TMO;
690 + }
691 + dev_err(host->dev,
692 + "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
693 + __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
694 + }
695 + return cmd->error;
696 +}
697 +
698 +static void msdc_track_cmd_data(struct msdc_host *host,
699 + struct mmc_command *cmd, struct mmc_data *data)
700 +{
701 + if (host->error)
702 + dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
703 + __func__, cmd->opcode, cmd->arg, host->error);
704 +}
705 +
706 +static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
707 +{
708 + unsigned long flags;
709 + bool ret;
710 +
711 + ret = cancel_delayed_work(&host->req_timeout);
712 + if (!ret) {
713 + /* delay work already running */
714 + return;
715 + }
716 + spin_lock_irqsave(&host->lock, flags);
717 + host->mrq = NULL;
718 + spin_unlock_irqrestore(&host->lock, flags);
719 +
720 + msdc_track_cmd_data(host, mrq->cmd, mrq->data);
721 + if (mrq->data)
722 + msdc_unprepare_data(host, mrq);
723 + mmc_request_done(host->mmc, mrq);
724 +}
725 +
726 +/* returns true if command is fully handled; returns false otherwise */
727 +static bool msdc_cmd_done(struct msdc_host *host, int events,
728 + struct mmc_request *mrq, struct mmc_command *cmd)
729 +{
730 + bool done = false;
731 + bool sbc_error;
732 + unsigned long flags;
733 + u32 *rsp = cmd->resp;
734 +
735 + if (mrq->sbc && cmd == mrq->cmd &&
736 + (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
737 + | MSDC_INT_ACMDTMO)))
738 + msdc_auto_cmd_done(host, events, mrq->sbc);
739 +
740 + sbc_error = mrq->sbc && mrq->sbc->error;
741 +
742 + if (!sbc_error && !(events & (MSDC_INT_CMDRDY
743 + | MSDC_INT_RSPCRCERR
744 + | MSDC_INT_CMDTMO)))
745 + return done;
746 +
747 + spin_lock_irqsave(&host->lock, flags);
748 + done = !host->cmd;
749 + host->cmd = NULL;
750 + spin_unlock_irqrestore(&host->lock, flags);
751 +
752 + if (done)
753 + return true;
754 +
755 + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CMDRDY |
756 + MSDC_INTEN_RSPCRCERR | MSDC_INTEN_CMDTMO |
757 + MSDC_INTEN_ACMDRDY | MSDC_INTEN_ACMDCRCERR |
758 + MSDC_INTEN_ACMDTMO);
759 + writel(cmd->arg, host->base + SDC_ARG);
760 +
761 + if (cmd->flags & MMC_RSP_PRESENT) {
762 + if (cmd->flags & MMC_RSP_136) {
763 + rsp[0] = readl(host->base + SDC_RESP3);
764 + rsp[1] = readl(host->base + SDC_RESP2);
765 + rsp[2] = readl(host->base + SDC_RESP1);
766 + rsp[3] = readl(host->base + SDC_RESP0);
767 + } else {
768 + rsp[0] = readl(host->base + SDC_RESP0);
769 + }
770 + }
771 +
772 + if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
773 + msdc_reset_hw(host);
774 + if (events & MSDC_INT_RSPCRCERR) {
775 + cmd->error = -EILSEQ;
776 + host->error |= REQ_CMD_EIO;
777 + } else if (events & MSDC_INT_CMDTMO) {
778 + cmd->error = -ETIMEDOUT;
779 + host->error |= REQ_CMD_TMO;
780 + }
781 + }
782 + if (cmd->error)
783 + dev_dbg(host->dev,
784 + "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
785 + __func__, cmd->opcode, cmd->arg, rsp[0],
786 + cmd->error);
787 +
788 + msdc_cmd_next(host, mrq, cmd);
789 + return true;
790 +}
791 +
792 +/* It is the core layer's responsibility to ensure card status
793 + * is correct before issue a request. but host design do below
794 + * checks recommended.
795 + */
796 +static inline bool msdc_cmd_is_ready(struct msdc_host *host,
797 + struct mmc_request *mrq, struct mmc_command *cmd)
798 +{
799 + /* The max busy time we can endure is 20ms */
800 + unsigned long tmo = jiffies + msecs_to_jiffies(20);
801 +
802 + while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
803 + time_before(jiffies, tmo))
804 + cpu_relax();
805 + if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
806 + dev_err(host->dev, "CMD bus busy detected\n");
807 + host->error |= REQ_CMD_BUSY;
808 + msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
809 + return false;
810 + }
811 +
812 + if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
813 + tmo = jiffies + msecs_to_jiffies(20);
814 + /* R1B or with data, should check SDCBUSY */
815 + while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
816 + time_before(jiffies, tmo))
817 + cpu_relax();
818 + if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
819 + dev_err(host->dev, "Controller busy detected\n");
820 + host->error |= REQ_CMD_BUSY;
821 + msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
822 + return false;
823 + }
824 + }
825 + return true;
826 +}
827 +
828 +static void msdc_start_command(struct msdc_host *host,
829 + struct mmc_request *mrq, struct mmc_command *cmd)
830 +{
831 + u32 rawcmd;
832 +
833 + WARN_ON(host->cmd);
834 + host->cmd = cmd;
835 +
836 + if (!msdc_cmd_is_ready(host, mrq, cmd))
837 + return;
838 +
839 + if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
840 + readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
841 + dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
842 + msdc_reset_hw(host);
843 + }
844 +
845 + cmd->error = 0;
846 + rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
847 + mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
848 +
849 + sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CMDRDY |
850 + MSDC_INTEN_RSPCRCERR | MSDC_INTEN_CMDTMO |
851 + MSDC_INTEN_ACMDRDY | MSDC_INTEN_ACMDCRCERR |
852 + MSDC_INTEN_ACMDTMO);
853 + writel(cmd->arg, host->base + SDC_ARG);
854 + writel(rawcmd, host->base + SDC_CMD);
855 +}
856 +
857 +static void msdc_cmd_next(struct msdc_host *host,
858 + struct mmc_request *mrq, struct mmc_command *cmd)
859 +{
860 + if (cmd->error || (mrq->sbc && mrq->sbc->error))
861 + msdc_request_done(host, mrq);
862 + else if (cmd == mrq->sbc)
863 + msdc_start_command(host, mrq, mrq->cmd);
864 + else if (!cmd->data)
865 + msdc_request_done(host, mrq);
866 + else
867 + msdc_start_data(host, mrq, cmd, cmd->data);
868 +}
869 +
870 +static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
871 +{
872 + struct msdc_host *host = mmc_priv(mmc);
873 +
874 + host->error = 0;
875 + WARN_ON(host->mrq);
876 + host->mrq = mrq;
877 +
878 + if (mrq->data)
879 + msdc_prepare_data(host, mrq);
880 +
881 + /* if SBC is required, we have HW option and SW option.
882 + * if HW option is enabled, and SBC does not have "special" flags,
883 + * use HW option, otherwise use SW option
884 + */
885 + if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
886 + (mrq->sbc->arg & 0xFFFF0000)))
887 + msdc_start_command(host, mrq, mrq->sbc);
888 + else
889 + msdc_start_command(host, mrq, mrq->cmd);
890 +}
891 +
892 +static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
893 + bool is_first_req)
894 +{
895 + struct msdc_host *host = mmc_priv(mmc);
896 + struct mmc_data *data = mrq->data;
897 +
898 + if (!data)
899 + return;
900 +
901 + msdc_prepare_data(host, mrq);
902 + data->host_cookie |= MSDC_ASYNC_FLAG;
903 +}
904 +
905 +static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
906 + int err)
907 +{
908 + struct msdc_host *host = mmc_priv(mmc);
909 + struct mmc_data *data;
910 +
911 + data = mrq->data;
912 + if (!data)
913 + return;
914 + if (data->host_cookie) {
915 + data->host_cookie &= ~MSDC_ASYNC_FLAG;
916 + msdc_unprepare_data(host, mrq);
917 + }
918 +}
919 +
920 +static void msdc_data_xfer_next(struct msdc_host *host,
921 + struct mmc_request *mrq, struct mmc_data *data)
922 +{
923 + if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
924 + (!data->bytes_xfered || !mrq->sbc))
925 + msdc_start_command(host, mrq, mrq->stop);
926 + else
927 + msdc_request_done(host, mrq);
928 +}
929 +
930 +static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
931 + struct mmc_request *mrq, struct mmc_data *data)
932 +{
933 + struct mmc_command *stop = data->stop;
934 + unsigned long flags;
935 + bool done;
936 + unsigned int check_data = events &
937 + (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
938 + | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
939 + | MSDC_INT_DMA_PROTECT);
940 +
941 + spin_lock_irqsave(&host->lock, flags);
942 + done = !host->data;
943 + if (check_data)
944 + host->data = NULL;
945 + spin_unlock_irqrestore(&host->lock, flags);
946 +
947 + if (done)
948 + return true;
949 +
950 + if (check_data || (stop && stop->error)) {
951 + dev_dbg(host->dev, "DMA status: 0x%8X\n",
952 + readl(host->base + MSDC_DMA_CFG));
953 + sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
954 + 1);
955 + while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
956 + cpu_relax();
957 + sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
958 + dev_dbg(host->dev, "DMA stop\n");
959 +
960 + if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
961 + data->bytes_xfered = data->blocks * data->blksz;
962 + } else {
963 + dev_err(host->dev, "interrupt events: %x\n", events);
964 + msdc_reset_hw(host);
965 + host->error |= REQ_DAT_ERR;
966 + data->bytes_xfered = 0;
967 +
968 + if (events & MSDC_INT_DATTMO)
969 + data->error = -ETIMEDOUT;
970 +
971 + dev_err(host->dev, "%s: cmd=%d; blocks=%d",
972 + __func__, mrq->cmd->opcode, data->blocks);
973 + dev_err(host->dev, "data_error=%d xfer_size=%d\n",
974 + (int)data->error, data->bytes_xfered);
975 + }
976 +
977 + msdc_data_xfer_next(host, mrq, data);
978 + done = true;
979 + }
980 + return done;
981 +}
982 +
983 +static void msdc_set_buswidth(struct msdc_host *host, u32 width)
984 +{
985 + u32 val = readl(host->base + SDC_CFG);
986 +
987 + val &= ~SDC_CFG_BUSWIDTH;
988 +
989 + switch (width) {
990 + default:
991 + case MMC_BUS_WIDTH_1:
992 + val |= (MSDC_BUS_1BITS << 16);
993 + break;
994 + case MMC_BUS_WIDTH_4:
995 + val |= (MSDC_BUS_4BITS << 16);
996 + break;
997 + case MMC_BUS_WIDTH_8:
998 + val |= (MSDC_BUS_8BITS << 16);
999 + break;
1000 + }
1001 +
1002 + writel(val, host->base + SDC_CFG);
1003 + dev_dbg(host->dev, "Bus Width = %d", width);
1004 +}
1005 +
1006 +static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1007 +{
1008 + struct msdc_host *host = mmc_priv(mmc);
1009 + int min_uv, max_uv;
1010 + int ret = 0;
1011 +
1012 + if (!IS_ERR(mmc->supply.vqmmc)) {
1013 + if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1014 + min_uv = 3300000;
1015 + max_uv = 3300000;
1016 + } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1017 + min_uv = 1800000;
1018 + max_uv = 1800000;
1019 + } else {
1020 + dev_err(host->dev, "Unsupported signal voltage!\n");
1021 + return -EINVAL;
1022 + }
1023 +
1024 + ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1025 + if (ret) {
1026 + dev_err(host->dev,
1027 + "Regulator set error %d: %d - %d\n",
1028 + ret, min_uv, max_uv);
1029 + } else {
1030 + /* Apply different pinctrl settings for different signal voltage */
1031 + if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1032 + pinctrl_select_state(host->pinctrl, host->pins_uhs);
1033 + else
1034 + pinctrl_select_state(host->pinctrl, host->pins_default);
1035 + }
1036 + }
1037 + return ret;
1038 +}
1039 +
1040 +static int msdc_card_busy(struct mmc_host *mmc)
1041 +{
1042 + struct msdc_host *host = mmc_priv(mmc);
1043 + u32 status = readl(host->base + MSDC_PS);
1044 +
1045 + /* check if any pin between dat[0:3] is low */
1046 + if (((status >> 16) & 0xf) != 0xf)
1047 + return 1;
1048 +
1049 + return 0;
1050 +}
1051 +
1052 +static void msdc_request_timeout(struct work_struct *work)
1053 +{
1054 + struct msdc_host *host = container_of(work, struct msdc_host,
1055 + req_timeout.work);
1056 +
1057 + /* simulate HW timeout status */
1058 + dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1059 + if (host->mrq) {
1060 + dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1061 + host->mrq, host->mrq->cmd->opcode);
1062 + if (host->cmd) {
1063 + dev_err(host->dev, "%s: aborting cmd=%d\n",
1064 + __func__, host->cmd->opcode);
1065 + msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1066 + host->cmd);
1067 + } else if (host->data) {
1068 + dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1069 + __func__, host->mrq->cmd->opcode,
1070 + host->data->blocks);
1071 + msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1072 + host->data);
1073 + }
1074 + }
1075 +}
1076 +
1077 +static irqreturn_t msdc_irq(int irq, void *dev_id)
1078 +{
1079 + struct msdc_host *host = (struct msdc_host *) dev_id;
1080 +
1081 + while (true) {
1082 + unsigned long flags;
1083 + struct mmc_request *mrq;
1084 + struct mmc_command *cmd;
1085 + struct mmc_data *data;
1086 + u32 events, event_mask;
1087 +
1088 + spin_lock_irqsave(&host->lock, flags);
1089 + events = readl(host->base + MSDC_INT);
1090 + event_mask = readl(host->base + MSDC_INTEN);
1091 + /* clear interrupts */
1092 + writel(events & event_mask, host->base + MSDC_INT);
1093 +
1094 + mrq = host->mrq;
1095 + cmd = host->cmd;
1096 + data = host->data;
1097 + spin_unlock_irqrestore(&host->lock, flags);
1098 +
1099 + if (!(events & event_mask))
1100 + break;
1101 +
1102 + if (!mrq) {
1103 + dev_err(host->dev,
1104 + "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1105 + __func__, events, event_mask);
1106 + WARN_ON(1);
1107 + break;
1108 + }
1109 +
1110 + dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1111 +
1112 + if (cmd)
1113 + msdc_cmd_done(host, events, mrq, cmd);
1114 + else if (data)
1115 + msdc_data_xfer_done(host, events, mrq, data);
1116 + }
1117 +
1118 + return IRQ_HANDLED;
1119 +}
1120 +
1121 +static void msdc_init_hw(struct msdc_host *host)
1122 +{
1123 + u32 val;
1124 +
1125 + /* Configure to MMC/SD mode, clock free running */
1126 + sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1127 +
1128 + /* Reset */
1129 + msdc_reset_hw(host);
1130 +
1131 + /* Disable card detection */
1132 + sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1133 +
1134 + /* Disable and clear all interrupts */
1135 + writel(0, host->base + MSDC_INTEN);
1136 + val = readl(host->base + MSDC_INT);
1137 + writel(val, host->base + MSDC_INT);
1138 +
1139 + writel(0, host->base + MSDC_PAD_TUNE);
1140 + writel(0, host->base + MSDC_IOCON);
1141 + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
1142 + writel(0x403c004f, host->base + MSDC_PATCH_BIT);
1143 + sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1144 + writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
1145 + /* Configure to enable SDIO mode.
1146 + * it's must otherwise sdio cmd5 failed
1147 + */
1148 + sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1149 +
1150 + /* disable detect SDIO device interrupt function */
1151 + sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1152 +
1153 + /* Configure to default data timeout */
1154 + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1155 +
1156 + dev_dbg(host->dev, "init hardware done!");
1157 +}
1158 +
1159 +static void msdc_deinit_hw(struct msdc_host *host)
1160 +{
1161 + u32 val;
1162 + /* Disable and clear all interrupts */
1163 + writel(0, host->base + MSDC_INTEN);
1164 +
1165 + val = readl(host->base + MSDC_INT);
1166 + writel(val, host->base + MSDC_INT);
1167 +}
1168 +
1169 +/* init gpd and bd list in msdc_drv_probe */
1170 +static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1171 +{
1172 + struct mt_gpdma_desc *gpd = dma->gpd;
1173 + struct mt_bdma_desc *bd = dma->bd;
1174 + int i;
1175 +
1176 + memset(gpd, 0, sizeof(struct mt_gpdma_desc));
1177 +
1178 + gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1179 + gpd->ptr = (u32)dma->bd_addr; /* physical address */
1180 +
1181 + memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1182 + for (i = 0; i < (MAX_BD_NUM - 1); i++)
1183 + bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1);
1184 +}
1185 +
1186 +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1187 +{
1188 + struct msdc_host *host = mmc_priv(mmc);
1189 + int ret;
1190 + u32 ddr = 0;
1191 +
1192 + if (ios->timing == MMC_TIMING_UHS_DDR50 ||
1193 + ios->timing == MMC_TIMING_MMC_DDR52)
1194 + ddr = 1;
1195 +
1196 + msdc_set_buswidth(host, ios->bus_width);
1197 +
1198 + /* Suspend/Resume will do power off/on */
1199 + switch (ios->power_mode) {
1200 + case MMC_POWER_UP:
1201 + if (!IS_ERR(mmc->supply.vmmc)) {
1202 + ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1203 + ios->vdd);
1204 + if (ret) {
1205 + dev_err(host->dev, "Failed to set vmmc power!\n");
1206 + return;
1207 + }
1208 + }
1209 + break;
1210 + case MMC_POWER_ON:
1211 + if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1212 + ret = regulator_enable(mmc->supply.vqmmc);
1213 + if (ret)
1214 + dev_err(host->dev, "Failed to set vqmmc power!\n");
1215 + else
1216 + host->vqmmc_enabled = true;
1217 + }
1218 + break;
1219 + case MMC_POWER_OFF:
1220 + if (!IS_ERR(mmc->supply.vmmc))
1221 + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1222 +
1223 + if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1224 + regulator_disable(mmc->supply.vqmmc);
1225 + host->vqmmc_enabled = false;
1226 + }
1227 + break;
1228 + default:
1229 + break;
1230 + }
1231 +
1232 + if (host->mclk != ios->clock || host->ddr != ddr)
1233 + msdc_set_mclk(host, ddr, ios->clock);
1234 +}
1235 +
1236 +static struct mmc_host_ops mt_msdc_ops = {
1237 + .post_req = msdc_post_req,
1238 + .pre_req = msdc_pre_req,
1239 + .request = msdc_ops_request,
1240 + .set_ios = msdc_ops_set_ios,
1241 + .start_signal_voltage_switch = msdc_ops_switch_volt,
1242 + .card_busy = msdc_card_busy,
1243 +};
1244 +
1245 +static int msdc_drv_probe(struct platform_device *pdev)
1246 +{
1247 + struct mmc_host *mmc;
1248 + struct msdc_host *host;
1249 + struct resource *res;
1250 + int ret;
1251 +
1252 + if (!pdev->dev.of_node) {
1253 + dev_err(&pdev->dev, "No DT found\n");
1254 + return -EINVAL;
1255 + }
1256 + /* Allocate MMC host for this device */
1257 + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
1258 + if (!mmc)
1259 + return -ENOMEM;
1260 +
1261 + host = mmc_priv(mmc);
1262 + ret = mmc_of_parse(mmc);
1263 + if (ret)
1264 + goto host_free;
1265 +
1266 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1267 + host->base = devm_ioremap_resource(&pdev->dev, res);
1268 + if (IS_ERR(host->base)) {
1269 + ret = PTR_ERR(host->base);
1270 + goto host_free;
1271 + }
1272 +
1273 + ret = mmc_regulator_get_supply(mmc);
1274 + if (ret == -EPROBE_DEFER)
1275 + goto host_free;
1276 +
1277 + host->src_clk = devm_clk_get(&pdev->dev, "source");
1278 + if (IS_ERR(host->src_clk)) {
1279 + ret = PTR_ERR(host->src_clk);
1280 + goto host_free;
1281 + }
1282 +
1283 + host->h_clk = devm_clk_get(&pdev->dev, "hclk");
1284 + if (IS_ERR(host->h_clk)) {
1285 + ret = PTR_ERR(host->h_clk);
1286 + goto host_free;
1287 + }
1288 +
1289 + host->irq = platform_get_irq(pdev, 0);
1290 + if (host->irq < 0) {
1291 + ret = -EINVAL;
1292 + goto host_free;
1293 + }
1294 +
1295 + host->pinctrl = devm_pinctrl_get(&pdev->dev);
1296 + if (IS_ERR(host->pinctrl)) {
1297 + ret = PTR_ERR(host->pinctrl);
1298 + dev_err(&pdev->dev, "Cannot find pinctrl!\n");
1299 + goto host_free;
1300 + }
1301 +
1302 + host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
1303 + if (IS_ERR(host->pins_default)) {
1304 + ret = PTR_ERR(host->pins_default);
1305 + dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
1306 + goto host_free;
1307 + }
1308 +
1309 + host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
1310 + if (IS_ERR(host->pins_uhs)) {
1311 + ret = PTR_ERR(host->pins_uhs);
1312 + dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
1313 + goto host_free;
1314 + }
1315 +
1316 + host->dev = &pdev->dev;
1317 + host->mmc = mmc;
1318 + host->src_clk_freq = clk_get_rate(host->src_clk);
1319 + /* Set host parameters to mmc */
1320 + mmc->ops = &mt_msdc_ops;
1321 + mmc->f_min = host->src_clk_freq / (4 * 255);
1322 +
1323 + mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
1324 + /* MMC core transfer sizes tunable parameters */
1325 + mmc->max_segs = MAX_BD_NUM;
1326 + mmc->max_seg_size = BDMA_DESC_BUFLEN;
1327 + mmc->max_blk_size = 2048;
1328 + mmc->max_req_size = 512 * 1024;
1329 + mmc->max_blk_count = mmc->max_req_size / 512;
1330 + host->dma_mask = DMA_BIT_MASK(32);
1331 + mmc_dev(mmc)->dma_mask = &host->dma_mask;
1332 +
1333 + host->timeout_clks = 3 * 1048576;
1334 + host->dma.gpd = dma_alloc_coherent(&pdev->dev,
1335 + sizeof(struct mt_gpdma_desc),
1336 + &host->dma.gpd_addr, GFP_KERNEL);
1337 + host->dma.bd = dma_alloc_coherent(&pdev->dev,
1338 + MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1339 + &host->dma.bd_addr, GFP_KERNEL);
1340 + if (!host->dma.gpd || !host->dma.bd) {
1341 + ret = -ENOMEM;
1342 + goto release_mem;
1343 + }
1344 + msdc_init_gpd_bd(host, &host->dma);
1345 + INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
1346 + spin_lock_init(&host->lock);
1347 +
1348 + platform_set_drvdata(pdev, mmc);
1349 + msdc_ungate_clock(host);
1350 + msdc_init_hw(host);
1351 +
1352 + ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
1353 + IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host);
1354 + if (ret)
1355 + goto release;
1356 +
1357 + ret = mmc_add_host(mmc);
1358 + if (ret)
1359 + goto release;
1360 +
1361 + return 0;
1362 +
1363 +release:
1364 + platform_set_drvdata(pdev, NULL);
1365 + msdc_deinit_hw(host);
1366 + msdc_gate_clock(host);
1367 +release_mem:
1368 + if (host->dma.gpd)
1369 + dma_free_coherent(&pdev->dev,
1370 + sizeof(struct mt_gpdma_desc),
1371 + host->dma.gpd, host->dma.gpd_addr);
1372 + if (host->dma.bd)
1373 + dma_free_coherent(&pdev->dev,
1374 + MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1375 + host->dma.bd, host->dma.bd_addr);
1376 +host_free:
1377 + mmc_free_host(mmc);
1378 +
1379 + return ret;
1380 +}
1381 +
1382 +static int msdc_drv_remove(struct platform_device *pdev)
1383 +{
1384 + struct mmc_host *mmc;
1385 + struct msdc_host *host;
1386 +
1387 + mmc = platform_get_drvdata(pdev);
1388 + host = mmc_priv(mmc);
1389 +
1390 + platform_set_drvdata(pdev, NULL);
1391 + mmc_remove_host(host->mmc);
1392 + msdc_deinit_hw(host);
1393 + msdc_gate_clock(host);
1394 +
1395 + dma_free_coherent(&pdev->dev,
1396 + sizeof(struct mt_gpdma_desc),
1397 + host->dma.gpd, host->dma.gpd_addr);
1398 + dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1399 + host->dma.bd, host->dma.bd_addr);
1400 +
1401 + mmc_free_host(host->mmc);
1402 +
1403 + return 0;
1404 +}
1405 +
1406 +static const struct of_device_id msdc_of_ids[] = {
1407 + { .compatible = "mediatek,mt8135-mmc", },
1408 + {}
1409 +};
1410 +
1411 +static struct platform_driver mt_msdc_driver = {
1412 + .probe = msdc_drv_probe,
1413 + .remove = msdc_drv_remove,
1414 + .driver = {
1415 + .name = "mtk-msdc",
1416 + .of_match_table = msdc_of_ids,
1417 + },
1418 +};
1419 +
1420 +module_platform_driver(mt_msdc_driver);
1421 +MODULE_LICENSE("GPL v2");
1422 +MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
OpenWrt Source Repository