target/linux/mediatek/patches/0043-ARM-dts-mt8127-enable-basic-SMP-bringup-for-mt8127.patch

   1 From e75f8b666c976aff2aa30b967f74df021d800993 Mon Sep 17 00:00:00 2001
   2 From: "Joe.C" <yingjoe.chen@mediatek.com>
   3 Date: Fri, 1 May 2015 15:43:30 +0800
   4 Subject: [PATCH 43/76] ARM: dts: mt8127: enable basic SMP bringup for mt8127
   5
   6 Add arch timer node to enable arch-timer support. MT8127 firmware
   7 doesn't correctly setup arch-timer frequency and CNTVOFF, add
   8 properties to workaround this.
   9
  10 This also set cpu enable-method to enable SMP.
  11
  12 Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
  13 ---
  14  arch/arm/boot/dts/mt8127.dtsi |   16 ++++++++++++++++
  15  1 file changed, 16 insertions(+)
  16
  17 diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
  18 index aaa7862..7c2090d 100644
  19 --- a/arch/arm/boot/dts/mt8127.dtsi
  20 +++ b/arch/arm/boot/dts/mt8127.dtsi
  21 @@ -23,6 +23,7 @@
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25 +               enable-method = "mediatek,mt81xx-tz-smp";
  26
  27                 cpu@0 {
  28                         device_type = "cpu";
  29 @@ -72,6 +73,21 @@
  30                  };
  31         };
  32
  33 +       timer {
  34 +               compatible = "arm,armv7-timer";
  35 +               interrupt-parent = <&gic>;
  36 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
  37 +                                         IRQ_TYPE_LEVEL_LOW)>,
  38 +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
  39 +                                         IRQ_TYPE_LEVEL_LOW)>,
  40 +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
  41 +                                         IRQ_TYPE_LEVEL_LOW)>,
  42 +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
  43 +                                         IRQ_TYPE_LEVEL_LOW)>;
  44 +               clock-frequency = <13000000>;
  45 +               arm,cpu-registers-not-fw-configured;
  46 +       };
  47 +
  48         soc {
  49                 #address-cells = <2>;
  50                 #size-cells = <2>;
  51 --
  52 1.7.10.4
  53