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kernel: update 4.1 to 4.1.13
[openwrt/staging/mkresin.git] / target / linux / mediatek / patches / 0059-arm-mediatek-basic-mt6323-pmic-support.patch
1 From 7f157285f2a01921917e0eed79b5d8cf734f5d27 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 24 Jun 2015 15:24:45 +0200
4 Subject: [PATCH 59/76] arm: mediatek: basic mt6323 pmic support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/mfd/Kconfig | 10 +
9 drivers/mfd/Makefile | 1 +
10 drivers/mfd/mt6323-core.c | 230 +++++++++++++++++++++
11 drivers/regulator/Kconfig | 9 +
12 drivers/regulator/Makefile | 1 +
13 drivers/regulator/mt6323-regulator.c | 332 +++++++++++++++++++++++++++++++
14 include/linux/mfd/mt6323/core.h | 64 ++++++
15 include/linux/mfd/mt6323/registers.h | 362 ++++++++++++++++++++++++++++++++++
16 8 files changed, 1009 insertions(+)
17 create mode 100644 drivers/mfd/mt6323-core.c
18 create mode 100644 drivers/regulator/mt6323-regulator.c
19 create mode 100644 include/linux/mfd/mt6323/core.h
20 create mode 100644 include/linux/mfd/mt6323/registers.h
21
22 --- a/drivers/mfd/Kconfig
23 +++ b/drivers/mfd/Kconfig
24 @@ -529,6 +529,16 @@ config MFD_MAX8998
25 additional drivers must be enabled in order to use the functionality
26 of the device.
27
28 +config MFD_MT6323
29 + tristate "MediaTek MT6323 PMIC Support"
30 + select MFD_CORE
31 + select IRQ_DOMAIN
32 + help
33 + Say yes here to add support for MediaTek MT6323 PMIC. This is
34 + a Power Management IC. This driver provides common support for
35 + accessing the device; additional drivers must be enabled in order
36 + to use the functionality of the device.
37 +
38 config MFD_MT6397
39 tristate "MediaTek MT6397 PMIC Support"
40 select MFD_CORE
41 --- a/drivers/mfd/Makefile
42 +++ b/drivers/mfd/Makefile
43 @@ -184,4 +184,5 @@ obj-$(CONFIG_MFD_SKY81452) += sky81452.o
44
45 intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
46 obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
47 +obj-$(CONFIG_MFD_MT6323) += mt6323-core.o
48 obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
49 --- /dev/null
50 +++ b/drivers/mfd/mt6323-core.c
51 @@ -0,0 +1,230 @@
52 +/*
53 + * Copyright (c) 2014 MediaTek Inc.
54 + * Author: Flora Fu, MediaTek
55 + *
56 + * This program is free software; you can redistribute it and/or modify
57 + * it under the terms of the GNU General Public License version 2 as
58 + * published by the Free Software Foundation.
59 + *
60 + * This program is distributed in the hope that it will be useful,
61 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
62 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
63 + * GNU General Public License for more details.
64 + */
65 +
66 +#include <linux/interrupt.h>
67 +#include <linux/module.h>
68 +#include <linux/of_device.h>
69 +#include <linux/of_irq.h>
70 +#include <linux/regmap.h>
71 +#include <linux/mfd/core.h>
72 +#include <linux/mfd/mt6397/core.h>
73 +#include <linux/mfd/mt6397/registers.h>
74 +
75 +static const struct mfd_cell mt6397_devs[] = {
76 + {
77 + .name = "mt6397-rtc",
78 + .of_compatible = "mediatek,mt6397-rtc",
79 + }, {
80 + .name = "mt6397-regulator",
81 + .of_compatible = "mediatek,mt6397-regulator",
82 + }, {
83 + .name = "mt6397-codec",
84 + .of_compatible = "mediatek,mt6397-codec",
85 + }, {
86 + .name = "mt6397-clk",
87 + .of_compatible = "mediatek,mt6397-clk",
88 + }, {
89 + .name = "mediatek-mt6397-pinctrl",
90 + .of_compatible = "mediatek,mt6397-pinctrl",
91 + },
92 +};
93 +
94 +static void mt6397_irq_lock(struct irq_data *data)
95 +{
96 + struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
97 +
98 + mutex_lock(&mt6397->irqlock);
99 +}
100 +
101 +static void mt6397_irq_sync_unlock(struct irq_data *data)
102 +{
103 + struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
104 +
105 + regmap_write(mt6397->regmap, MT6397_INT_CON0, mt6397->irq_masks_cur[0]);
106 + regmap_write(mt6397->regmap, MT6397_INT_CON1, mt6397->irq_masks_cur[1]);
107 +
108 + mutex_unlock(&mt6397->irqlock);
109 +}
110 +
111 +static void mt6397_irq_disable(struct irq_data *data)
112 +{
113 + struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
114 + int shift = data->hwirq & 0xf;
115 + int reg = data->hwirq >> 4;
116 +
117 + mt6397->irq_masks_cur[reg] &= ~BIT(shift);
118 +}
119 +
120 +static void mt6397_irq_enable(struct irq_data *data)
121 +{
122 + struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
123 + int shift = data->hwirq & 0xf;
124 + int reg = data->hwirq >> 4;
125 +
126 + mt6397->irq_masks_cur[reg] |= BIT(shift);
127 +}
128 +
129 +static struct irq_chip mt6397_irq_chip = {
130 + .name = "mt6397-irq",
131 + .irq_bus_lock = mt6397_irq_lock,
132 + .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
133 + .irq_enable = mt6397_irq_enable,
134 + .irq_disable = mt6397_irq_disable,
135 +};
136 +
137 +static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
138 + int irqbase)
139 +{
140 + unsigned int status;
141 + int i, irq, ret;
142 +
143 + ret = regmap_read(mt6397->regmap, reg, &status);
144 + if (ret) {
145 + dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
146 + return;
147 + }
148 +
149 + for (i = 0; i < 16; i++) {
150 + if (status & BIT(i)) {
151 + irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
152 + if (irq)
153 + handle_nested_irq(irq);
154 + }
155 + }
156 +
157 + regmap_write(mt6397->regmap, reg, status);
158 +}
159 +
160 +static irqreturn_t mt6397_irq_thread(int irq, void *data)
161 +{
162 + struct mt6397_chip *mt6397 = data;
163 +
164 + mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS0, 0);
165 + mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS1, 16);
166 +
167 + return IRQ_HANDLED;
168 +}
169 +
170 +static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
171 + irq_hw_number_t hw)
172 +{
173 + struct mt6397_chip *mt6397 = d->host_data;
174 +
175 + irq_set_chip_data(irq, mt6397);
176 + irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
177 + irq_set_nested_thread(irq, 1);
178 +#ifdef CONFIG_ARM
179 + set_irq_flags(irq, IRQF_VALID);
180 +#else
181 + irq_set_noprobe(irq);
182 +#endif
183 +
184 + return 0;
185 +}
186 +
187 +static struct irq_domain_ops mt6397_irq_domain_ops = {
188 + .map = mt6397_irq_domain_map,
189 +};
190 +
191 +static int mt6397_irq_init(struct mt6397_chip *mt6397)
192 +{
193 + int ret;
194 +
195 + mutex_init(&mt6397->irqlock);
196 +
197 + /* Mask all interrupt sources */
198 + regmap_write(mt6397->regmap, MT6397_INT_CON0, 0x0);
199 + regmap_write(mt6397->regmap, MT6397_INT_CON1, 0x0);
200 +
201 + mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
202 + MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
203 + if (!mt6397->irq_domain) {
204 + dev_err(mt6397->dev, "could not create irq domain\n");
205 + return -ENOMEM;
206 + }
207 +
208 + ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
209 + mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
210 + if (ret) {
211 + dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
212 + mt6397->irq, ret);
213 + return ret;
214 + }
215 +
216 + return 0;
217 +}
218 +
219 +static int mt6397_probe(struct platform_device *pdev)
220 +{
221 + int ret;
222 + struct mt6397_chip *mt6397;
223 +
224 + mt6397 = devm_kzalloc(&pdev->dev, sizeof(*mt6397), GFP_KERNEL);
225 + if (!mt6397)
226 + return -ENOMEM;
227 +
228 + mt6397->dev = &pdev->dev;
229 + /*
230 + * mt6397 MFD is child device of soc pmic wrapper.
231 + * Regmap is set from its parent.
232 + */
233 + mt6397->regmap = dev_get_regmap(pdev->dev.parent, NULL);
234 + if (!mt6397->regmap)
235 + return -ENODEV;
236 +
237 + platform_set_drvdata(pdev, mt6397);
238 +
239 + mt6397->irq = platform_get_irq(pdev, 0);
240 + if (mt6397->irq > 0) {
241 + ret = mt6397_irq_init(mt6397);
242 + if (ret)
243 + return ret;
244 + }
245 +
246 + ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
247 + ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
248 + if (ret)
249 + dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
250 +
251 + return ret;
252 +}
253 +
254 +static int mt6397_remove(struct platform_device *pdev)
255 +{
256 + mfd_remove_devices(&pdev->dev);
257 +
258 + return 0;
259 +}
260 +
261 +static const struct of_device_id mt6397_of_match[] = {
262 + { .compatible = "mediatek,mt6397" },
263 + { }
264 +};
265 +MODULE_DEVICE_TABLE(of, mt6397_of_match);
266 +
267 +static struct platform_driver mt6397_driver = {
268 + .probe = mt6397_probe,
269 + .remove = mt6397_remove,
270 + .driver = {
271 + .name = "mt6397",
272 + .of_match_table = of_match_ptr(mt6397_of_match),
273 + },
274 +};
275 +
276 +module_platform_driver(mt6397_driver);
277 +
278 +MODULE_AUTHOR("Flora Fu, MediaTek");
279 +MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
280 +MODULE_LICENSE("GPL");
281 +MODULE_ALIAS("platform:mt6397");
282 --- a/drivers/regulator/Kconfig
283 +++ b/drivers/regulator/Kconfig
284 @@ -441,6 +441,15 @@ config REGULATOR_MC13892
285 Say y here to support the regulators found on the Freescale MC13892
286 PMIC.
287
288 +config REGULATOR_MT6323
289 + tristate "MediaTek MT6323 PMIC"
290 + depends on MFD_MT6323
291 + help
292 + Say y here to select this option to enable the power regulator of
293 + MediaTek MT6323 PMIC.
294 + This driver supports the control of different power rails of device
295 + through regulator interface.
296 +
297 config REGULATOR_MT6397
298 tristate "MediaTek MT6397 PMIC"
299 depends on MFD_MT6397
300 --- a/drivers/regulator/Makefile
301 +++ b/drivers/regulator/Makefile
302 @@ -59,6 +59,7 @@ obj-$(CONFIG_REGULATOR_MAX77843) += max7
303 obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o
304 obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
305 obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o
306 +obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o
307 obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o
308 obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
309 obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o
310 --- /dev/null
311 +++ b/drivers/regulator/mt6323-regulator.c
312 @@ -0,0 +1,332 @@
313 +/*
314 + * Copyright (c) 2014 MediaTek Inc.
315 + * Author: Flora Fu <flora.fu@mediatek.com>
316 + *
317 + * This program is free software; you can redistribute it and/or modify
318 + * it under the terms of the GNU General Public License version 2 as
319 + * published by the Free Software Foundation.
320 + *
321 + * This program is distributed in the hope that it will be useful,
322 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
323 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
324 + * GNU General Public License for more details.
325 + */
326 +
327 +#include <linux/module.h>
328 +#include <linux/of.h>
329 +#include <linux/platform_device.h>
330 +#include <linux/regmap.h>
331 +#include <linux/mfd/mt6397/core.h>
332 +#include <linux/mfd/mt6397/registers.h>
333 +#include <linux/regulator/driver.h>
334 +#include <linux/regulator/machine.h>
335 +#include <linux/regulator/mt6397-regulator.h>
336 +#include <linux/regulator/of_regulator.h>
337 +
338 +/*
339 + * MT6397 regulators' information
340 + *
341 + * @desc: standard fields of regulator description.
342 + * @qi: Mask for query enable signal status of regulators
343 + * @vselon_reg: Register sections for hardware control mode of bucks
344 + * @vselctrl_reg: Register for controlling the buck control mode.
345 + * @vselctrl_mask: Mask for query buck's voltage control mode.
346 + */
347 +struct mt6397_regulator_info {
348 + struct regulator_desc desc;
349 + u32 qi;
350 + u32 vselon_reg;
351 + u32 vselctrl_reg;
352 + u32 vselctrl_mask;
353 +};
354 +
355 +#define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
356 + vosel, vosel_mask, voselon, vosel_ctrl) \
357 +[MT6397_ID_##vreg] = { \
358 + .desc = { \
359 + .name = #vreg, \
360 + .of_match = of_match_ptr(match), \
361 + .ops = &mt6397_volt_range_ops, \
362 + .type = REGULATOR_VOLTAGE, \
363 + .id = MT6397_ID_##vreg, \
364 + .owner = THIS_MODULE, \
365 + .n_voltages = (max - min)/step + 1, \
366 + .linear_ranges = volt_ranges, \
367 + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
368 + .vsel_reg = vosel, \
369 + .vsel_mask = vosel_mask, \
370 + .enable_reg = enreg, \
371 + .enable_mask = BIT(0), \
372 + }, \
373 + .qi = BIT(13), \
374 + .vselon_reg = voselon, \
375 + .vselctrl_reg = vosel_ctrl, \
376 + .vselctrl_mask = BIT(1), \
377 +}
378 +
379 +#define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \
380 + vosel_mask) \
381 +[MT6397_ID_##vreg] = { \
382 + .desc = { \
383 + .name = #vreg, \
384 + .of_match = of_match_ptr(match), \
385 + .ops = &mt6397_volt_table_ops, \
386 + .type = REGULATOR_VOLTAGE, \
387 + .id = MT6397_ID_##vreg, \
388 + .owner = THIS_MODULE, \
389 + .n_voltages = ARRAY_SIZE(ldo_volt_table), \
390 + .volt_table = ldo_volt_table, \
391 + .vsel_reg = vosel, \
392 + .vsel_mask = vosel_mask, \
393 + .enable_reg = enreg, \
394 + .enable_mask = BIT(enbit), \
395 + }, \
396 + .qi = BIT(15), \
397 +}
398 +
399 +#define MT6397_REG_FIXED(match, vreg, enreg, enbit, volt) \
400 +[MT6397_ID_##vreg] = { \
401 + .desc = { \
402 + .name = #vreg, \
403 + .of_match = of_match_ptr(match), \
404 + .ops = &mt6397_volt_fixed_ops, \
405 + .type = REGULATOR_VOLTAGE, \
406 + .id = MT6397_ID_##vreg, \
407 + .owner = THIS_MODULE, \
408 + .n_voltages = 1, \
409 + .enable_reg = enreg, \
410 + .enable_mask = BIT(enbit), \
411 + .min_uV = volt, \
412 + }, \
413 + .qi = BIT(15), \
414 +}
415 +
416 +static const struct regulator_linear_range buck_volt_range1[] = {
417 + REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250),
418 +};
419 +
420 +static const struct regulator_linear_range buck_volt_range2[] = {
421 + REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250),
422 +};
423 +
424 +static const struct regulator_linear_range buck_volt_range3[] = {
425 + REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000),
426 +};
427 +
428 +static const u32 ldo_volt_table1[] = {
429 + 1500000, 1800000, 2500000, 2800000,
430 +};
431 +
432 +static const u32 ldo_volt_table2[] = {
433 + 1800000, 3300000,
434 +};
435 +
436 +static const u32 ldo_volt_table3[] = {
437 + 3000000, 3300000,
438 +};
439 +
440 +static const u32 ldo_volt_table4[] = {
441 + 1220000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
442 +};
443 +
444 +static const u32 ldo_volt_table5[] = {
445 + 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
446 +};
447 +
448 +static const u32 ldo_volt_table5_v2[] = {
449 + 1200000, 1000000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
450 +};
451 +
452 +static const u32 ldo_volt_table6[] = {
453 + 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000,
454 +};
455 +
456 +static const u32 ldo_volt_table7[] = {
457 + 1300000, 1500000, 1800000, 2000000, 2500000, 2800000, 3000000, 3300000,
458 +};
459 +
460 +static int mt6397_get_status(struct regulator_dev *rdev)
461 +{
462 + int ret;
463 + u32 regval;
464 + struct mt6397_regulator_info *info = rdev_get_drvdata(rdev);
465 +
466 + ret = regmap_read(rdev->regmap, info->desc.enable_reg, &regval);
467 + if (ret != 0) {
468 + dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
469 + return ret;
470 + }
471 +
472 + return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
473 +}
474 +
475 +static struct regulator_ops mt6397_volt_range_ops = {
476 + .list_voltage = regulator_list_voltage_linear_range,
477 + .map_voltage = regulator_map_voltage_linear_range,
478 + .set_voltage_sel = regulator_set_voltage_sel_regmap,
479 + .get_voltage_sel = regulator_get_voltage_sel_regmap,
480 + .set_voltage_time_sel = regulator_set_voltage_time_sel,
481 + .enable = regulator_enable_regmap,
482 + .disable = regulator_disable_regmap,
483 + .is_enabled = regulator_is_enabled_regmap,
484 + .get_status = mt6397_get_status,
485 +};
486 +
487 +static struct regulator_ops mt6397_volt_table_ops = {
488 + .list_voltage = regulator_list_voltage_table,
489 + .map_voltage = regulator_map_voltage_iterate,
490 + .set_voltage_sel = regulator_set_voltage_sel_regmap,
491 + .get_voltage_sel = regulator_get_voltage_sel_regmap,
492 + .set_voltage_time_sel = regulator_set_voltage_time_sel,
493 + .enable = regulator_enable_regmap,
494 + .disable = regulator_disable_regmap,
495 + .is_enabled = regulator_is_enabled_regmap,
496 + .get_status = mt6397_get_status,
497 +};
498 +
499 +static struct regulator_ops mt6397_volt_fixed_ops = {
500 + .list_voltage = regulator_list_voltage_linear,
501 + .enable = regulator_enable_regmap,
502 + .disable = regulator_disable_regmap,
503 + .is_enabled = regulator_is_enabled_regmap,
504 + .get_status = mt6397_get_status,
505 +};
506 +
507 +/* The array is indexed by id(MT6397_ID_XXX) */
508 +static struct mt6397_regulator_info mt6397_regulators[] = {
509 + MT6397_BUCK("buck_vpca15", VPCA15, 700000, 1493750, 6250,
510 + buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f,
511 + MT6397_VCA15_CON10, MT6397_VCA15_CON5),
512 + MT6397_BUCK("buck_vpca7", VPCA7, 700000, 1493750, 6250,
513 + buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f,
514 + MT6397_VPCA7_CON10, MT6397_VPCA7_CON5),
515 + MT6397_BUCK("buck_vsramca15", VSRAMCA15, 700000, 1493750, 6250,
516 + buck_volt_range1, MT6397_VSRMCA15_CON7, MT6397_VSRMCA15_CON9,
517 + 0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5),
518 + MT6397_BUCK("buck_vsramca7", VSRAMCA7, 700000, 1493750, 6250,
519 + buck_volt_range1, MT6397_VSRMCA7_CON7, MT6397_VSRMCA7_CON9,
520 + 0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5),
521 + MT6397_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250,
522 + buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f,
523 + MT6397_VCORE_CON10, MT6397_VCORE_CON5),
524 + MT6397_BUCK("buck_vgpu", VGPU, 700000, 1493750, 6250, buck_volt_range1,
525 + MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f,
526 + MT6397_VGPU_CON10, MT6397_VGPU_CON5),
527 + MT6397_BUCK("buck_vdrm", VDRM, 800000, 1593750, 6250, buck_volt_range2,
528 + MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f,
529 + MT6397_VDRM_CON10, MT6397_VDRM_CON5),
530 + MT6397_BUCK("buck_vio18", VIO18, 1500000, 2120000, 20000,
531 + buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f,
532 + MT6397_VIO18_CON10, MT6397_VIO18_CON5),
533 + MT6397_REG_FIXED("ldo_vtcxo", VTCXO, MT6397_ANALDO_CON0, 10, 2800000),
534 + MT6397_REG_FIXED("ldo_va28", VA28, MT6397_ANALDO_CON1, 14, 2800000),
535 + MT6397_LDO("ldo_vcama", VCAMA, ldo_volt_table1,
536 + MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0),
537 + MT6397_REG_FIXED("ldo_vio28", VIO28, MT6397_DIGLDO_CON0, 14, 2800000),
538 + MT6397_REG_FIXED("ldo_vusb", VUSB, MT6397_DIGLDO_CON1, 14, 3300000),
539 + MT6397_LDO("ldo_vmc", VMC, ldo_volt_table2,
540 + MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10),
541 + MT6397_LDO("ldo_vmch", VMCH, ldo_volt_table3,
542 + MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80),
543 + MT6397_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table3,
544 + MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10),
545 + MT6397_LDO("ldo_vgp1", VGP1, ldo_volt_table4,
546 + MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0),
547 + MT6397_LDO("ldo_vgp2", VGP2, ldo_volt_table5,
548 + MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0),
549 + MT6397_LDO("ldo_vgp3", VGP3, ldo_volt_table5,
550 + MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0),
551 + MT6397_LDO("ldo_vgp4", VGP4, ldo_volt_table5,
552 + MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0),
553 + MT6397_LDO("ldo_vgp5", VGP5, ldo_volt_table6,
554 + MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0),
555 + MT6397_LDO("ldo_vgp6", VGP6, ldo_volt_table5,
556 + MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0),
557 + MT6397_LDO("ldo_vibr", VIBR, ldo_volt_table7,
558 + MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00),
559 +};
560 +
561 +static int mt6397_set_buck_vosel_reg(struct platform_device *pdev)
562 +{
563 + struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
564 + int i;
565 + u32 regval;
566 +
567 + for (i = 0; i < MT6397_MAX_REGULATOR; i++) {
568 + if (mt6397_regulators[i].vselctrl_reg) {
569 + if (regmap_read(mt6397->regmap,
570 + mt6397_regulators[i].vselctrl_reg,
571 + &regval) < 0) {
572 + dev_err(&pdev->dev,
573 + "Failed to read buck ctrl\n");
574 + return -EIO;
575 + }
576 +
577 + if (regval & mt6397_regulators[i].vselctrl_mask) {
578 + mt6397_regulators[i].desc.vsel_reg =
579 + mt6397_regulators[i].vselon_reg;
580 + }
581 + }
582 + }
583 +
584 + return 0;
585 +}
586 +
587 +static int mt6397_regulator_probe(struct platform_device *pdev)
588 +{
589 + struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
590 + struct regulator_config config = {};
591 + struct regulator_dev *rdev;
592 + int i;
593 + u32 reg_value, version;
594 +
595 + /* Query buck controller to select activated voltage register part */
596 + if (mt6397_set_buck_vosel_reg(pdev))
597 + return -EIO;
598 +
599 + /* Read PMIC chip revision to update constraints and voltage table */
600 + if (regmap_read(mt6397->regmap, MT6397_CID, &reg_value) < 0) {
601 + dev_err(&pdev->dev, "Failed to read Chip ID\n");
602 + return -EIO;
603 + }
604 + dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);
605 +
606 + version = (reg_value & 0xFF);
607 + switch (version) {
608 + case MT6397_REGULATOR_ID91:
609 + mt6397_regulators[MT6397_ID_VGP2].desc.volt_table =
610 + ldo_volt_table5_v2;
611 + break;
612 + default:
613 + break;
614 + }
615 +
616 + for (i = 0; i < MT6397_MAX_REGULATOR; i++) {
617 + config.dev = &pdev->dev;
618 + config.driver_data = &mt6397_regulators[i];
619 + config.regmap = mt6397->regmap;
620 + rdev = devm_regulator_register(&pdev->dev,
621 + &mt6397_regulators[i].desc, &config);
622 + if (IS_ERR(rdev)) {
623 + dev_err(&pdev->dev, "failed to register %s\n",
624 + mt6397_regulators[i].desc.name);
625 + return PTR_ERR(rdev);
626 + }
627 + }
628 +
629 + return 0;
630 +}
631 +
632 +static struct platform_driver mt6397_regulator_driver = {
633 + .driver = {
634 + .name = "mt6397-regulator",
635 + },
636 + .probe = mt6397_regulator_probe,
637 +};
638 +
639 +module_platform_driver(mt6397_regulator_driver);
640 +
641 +MODULE_AUTHOR("Flora Fu <flora.fu@mediatek.com>");
642 +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC");
643 +MODULE_LICENSE("GPL");
644 +MODULE_ALIAS("platform:mt6397-regulator");
645 --- /dev/null
646 +++ b/include/linux/mfd/mt6323/core.h
647 @@ -0,0 +1,64 @@
648 +/*
649 + * Copyright (c) 2014 MediaTek Inc.
650 + * Author: Flora Fu, MediaTek
651 + *
652 + * This program is free software; you can redistribute it and/or modify
653 + * it under the terms of the GNU General Public License version 2 as
654 + * published by the Free Software Foundation.
655 + *
656 + * This program is distributed in the hope that it will be useful,
657 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
658 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
659 + * GNU General Public License for more details.
660 + */
661 +
662 +#ifndef __MFD_MT6397_CORE_H__
663 +#define __MFD_MT6397_CORE_H__
664 +
665 +enum mt6397_irq_numbers {
666 + MT6397_IRQ_SPKL_AB = 0,
667 + MT6397_IRQ_SPKR_AB,
668 + MT6397_IRQ_SPKL,
669 + MT6397_IRQ_SPKR,
670 + MT6397_IRQ_BAT_L,
671 + MT6397_IRQ_BAT_H,
672 + MT6397_IRQ_FG_BAT_L,
673 + MT6397_IRQ_FG_BAT_H,
674 + MT6397_IRQ_WATCHDOG,
675 + MT6397_IRQ_PWRKEY,
676 + MT6397_IRQ_THR_L,
677 + MT6397_IRQ_THR_H,
678 + MT6397_IRQ_VBATON_UNDET,
679 + MT6397_IRQ_BVALID_DET,
680 + MT6397_IRQ_CHRDET,
681 + MT6397_IRQ_OV,
682 + MT6397_IRQ_LDO,
683 + MT6397_IRQ_HOMEKEY,
684 + MT6397_IRQ_ACCDET,
685 + MT6397_IRQ_AUDIO,
686 + MT6397_IRQ_RTC,
687 + MT6397_IRQ_PWRKEY_RSTB,
688 + MT6397_IRQ_HDMI_SIFM,
689 + MT6397_IRQ_HDMI_CEC,
690 + MT6397_IRQ_VCA15,
691 + MT6397_IRQ_VSRMCA15,
692 + MT6397_IRQ_VCORE,
693 + MT6397_IRQ_VGPU,
694 + MT6397_IRQ_VIO18,
695 + MT6397_IRQ_VPCA7,
696 + MT6397_IRQ_VSRMCA7,
697 + MT6397_IRQ_VDRM,
698 + MT6397_IRQ_NR,
699 +};
700 +
701 +struct mt6397_chip {
702 + struct device *dev;
703 + struct regmap *regmap;
704 + int irq;
705 + struct irq_domain *irq_domain;
706 + struct mutex irqlock;
707 + u16 irq_masks_cur[2];
708 + u16 irq_masks_cache[2];
709 +};
710 +
711 +#endif /* __MFD_MT6397_CORE_H__ */
712 --- /dev/null
713 +++ b/include/linux/mfd/mt6323/registers.h
714 @@ -0,0 +1,362 @@
715 +/*
716 + * Copyright (c) 2014 MediaTek Inc.
717 + * Author: Flora Fu, MediaTek
718 + *
719 + * This program is free software; you can redistribute it and/or modify
720 + * it under the terms of the GNU General Public License version 2 as
721 + * published by the Free Software Foundation.
722 + *
723 + * This program is distributed in the hope that it will be useful,
724 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
725 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
726 + * GNU General Public License for more details.
727 + */
728 +
729 +#ifndef __MFD_MT6397_REGISTERS_H__
730 +#define __MFD_MT6397_REGISTERS_H__
731 +
732 +/* PMIC Registers */
733 +#define MT6397_CID 0x0100
734 +#define MT6397_TOP_CKPDN 0x0102
735 +#define MT6397_TOP_CKPDN_SET 0x0104
736 +#define MT6397_TOP_CKPDN_CLR 0x0106
737 +#define MT6397_TOP_CKPDN2 0x0108
738 +#define MT6397_TOP_CKPDN2_SET 0x010A
739 +#define MT6397_TOP_CKPDN2_CLR 0x010C
740 +#define MT6397_TOP_GPIO_CKPDN 0x010E
741 +#define MT6397_TOP_RST_CON 0x0114
742 +#define MT6397_WRP_CKPDN 0x011A
743 +#define MT6397_WRP_RST_CON 0x0120
744 +#define MT6397_TOP_RST_MISC 0x0126
745 +#define MT6397_TOP_CKCON1 0x0128
746 +#define MT6397_TOP_CKCON2 0x012A
747 +#define MT6397_TOP_CKTST1 0x012C
748 +#define MT6397_TOP_CKTST2 0x012E
749 +#define MT6397_OC_DEG_EN 0x0130
750 +#define MT6397_OC_CTL0 0x0132
751 +#define MT6397_OC_CTL1 0x0134
752 +#define MT6397_OC_CTL2 0x0136
753 +#define MT6397_INT_RSV 0x0138
754 +#define MT6397_TEST_CON0 0x013A
755 +#define MT6397_TEST_CON1 0x013C
756 +#define MT6397_STATUS0 0x013E
757 +#define MT6397_STATUS1 0x0140
758 +#define MT6397_PGSTATUS 0x0142
759 +#define MT6397_CHRSTATUS 0x0144
760 +#define MT6397_OCSTATUS0 0x0146
761 +#define MT6397_OCSTATUS1 0x0148
762 +#define MT6397_OCSTATUS2 0x014A
763 +#define MT6397_HDMI_PAD_IE 0x014C
764 +#define MT6397_TEST_OUT_L 0x014E
765 +#define MT6397_TEST_OUT_H 0x0150
766 +#define MT6397_TDSEL_CON 0x0152
767 +#define MT6397_RDSEL_CON 0x0154
768 +#define MT6397_GPIO_SMT_CON0 0x0156
769 +#define MT6397_GPIO_SMT_CON1 0x0158
770 +#define MT6397_GPIO_SMT_CON2 0x015A
771 +#define MT6397_GPIO_SMT_CON3 0x015C
772 +#define MT6397_DRV_CON0 0x015E
773 +#define MT6397_DRV_CON1 0x0160
774 +#define MT6397_DRV_CON2 0x0162
775 +#define MT6397_DRV_CON3 0x0164
776 +#define MT6397_DRV_CON4 0x0166
777 +#define MT6397_DRV_CON5 0x0168
778 +#define MT6397_DRV_CON6 0x016A
779 +#define MT6397_DRV_CON7 0x016C
780 +#define MT6397_DRV_CON8 0x016E
781 +#define MT6397_DRV_CON9 0x0170
782 +#define MT6397_DRV_CON10 0x0172
783 +#define MT6397_DRV_CON11 0x0174
784 +#define MT6397_DRV_CON12 0x0176
785 +#define MT6397_INT_CON0 0x0178
786 +#define MT6397_INT_CON1 0x017E
787 +#define MT6397_INT_STATUS0 0x0184
788 +#define MT6397_INT_STATUS1 0x0186
789 +#define MT6397_FQMTR_CON0 0x0188
790 +#define MT6397_FQMTR_CON1 0x018A
791 +#define MT6397_FQMTR_CON2 0x018C
792 +#define MT6397_EFUSE_DOUT_0_15 0x01C4
793 +#define MT6397_EFUSE_DOUT_16_31 0x01C6
794 +#define MT6397_EFUSE_DOUT_32_47 0x01C8
795 +#define MT6397_EFUSE_DOUT_48_63 0x01CA
796 +#define MT6397_SPI_CON 0x01CC
797 +#define MT6397_TOP_CKPDN3 0x01CE
798 +#define MT6397_TOP_CKCON3 0x01D4
799 +#define MT6397_EFUSE_DOUT_64_79 0x01D6
800 +#define MT6397_EFUSE_DOUT_80_95 0x01D8
801 +#define MT6397_EFUSE_DOUT_96_111 0x01DA
802 +#define MT6397_EFUSE_DOUT_112_127 0x01DC
803 +#define MT6397_EFUSE_DOUT_128_143 0x01DE
804 +#define MT6397_EFUSE_DOUT_144_159 0x01E0
805 +#define MT6397_EFUSE_DOUT_160_175 0x01E2
806 +#define MT6397_EFUSE_DOUT_176_191 0x01E4
807 +#define MT6397_EFUSE_DOUT_192_207 0x01E6
808 +#define MT6397_EFUSE_DOUT_208_223 0x01E8
809 +#define MT6397_EFUSE_DOUT_224_239 0x01EA
810 +#define MT6397_EFUSE_DOUT_240_255 0x01EC
811 +#define MT6397_EFUSE_DOUT_256_271 0x01EE
812 +#define MT6397_EFUSE_DOUT_272_287 0x01F0
813 +#define MT6397_EFUSE_DOUT_288_300 0x01F2
814 +#define MT6397_EFUSE_DOUT_304_319 0x01F4
815 +#define MT6397_BUCK_CON0 0x0200
816 +#define MT6397_BUCK_CON1 0x0202
817 +#define MT6397_BUCK_CON2 0x0204
818 +#define MT6397_BUCK_CON3 0x0206
819 +#define MT6397_BUCK_CON4 0x0208
820 +#define MT6397_BUCK_CON5 0x020A
821 +#define MT6397_BUCK_CON6 0x020C
822 +#define MT6397_BUCK_CON7 0x020E
823 +#define MT6397_BUCK_CON8 0x0210
824 +#define MT6397_BUCK_CON9 0x0212
825 +#define MT6397_VCA15_CON0 0x0214
826 +#define MT6397_VCA15_CON1 0x0216
827 +#define MT6397_VCA15_CON2 0x0218
828 +#define MT6397_VCA15_CON3 0x021A
829 +#define MT6397_VCA15_CON4 0x021C
830 +#define MT6397_VCA15_CON5 0x021E
831 +#define MT6397_VCA15_CON6 0x0220
832 +#define MT6397_VCA15_CON7 0x0222
833 +#define MT6397_VCA15_CON8 0x0224
834 +#define MT6397_VCA15_CON9 0x0226
835 +#define MT6397_VCA15_CON10 0x0228
836 +#define MT6397_VCA15_CON11 0x022A
837 +#define MT6397_VCA15_CON12 0x022C
838 +#define MT6397_VCA15_CON13 0x022E
839 +#define MT6397_VCA15_CON14 0x0230
840 +#define MT6397_VCA15_CON15 0x0232
841 +#define MT6397_VCA15_CON16 0x0234
842 +#define MT6397_VCA15_CON17 0x0236
843 +#define MT6397_VCA15_CON18 0x0238
844 +#define MT6397_VSRMCA15_CON0 0x023A
845 +#define MT6397_VSRMCA15_CON1 0x023C
846 +#define MT6397_VSRMCA15_CON2 0x023E
847 +#define MT6397_VSRMCA15_CON3 0x0240
848 +#define MT6397_VSRMCA15_CON4 0x0242
849 +#define MT6397_VSRMCA15_CON5 0x0244
850 +#define MT6397_VSRMCA15_CON6 0x0246
851 +#define MT6397_VSRMCA15_CON7 0x0248
852 +#define MT6397_VSRMCA15_CON8 0x024A
853 +#define MT6397_VSRMCA15_CON9 0x024C
854 +#define MT6397_VSRMCA15_CON10 0x024E
855 +#define MT6397_VSRMCA15_CON11 0x0250
856 +#define MT6397_VSRMCA15_CON12 0x0252
857 +#define MT6397_VSRMCA15_CON13 0x0254
858 +#define MT6397_VSRMCA15_CON14 0x0256
859 +#define MT6397_VSRMCA15_CON15 0x0258
860 +#define MT6397_VSRMCA15_CON16 0x025A
861 +#define MT6397_VSRMCA15_CON17 0x025C
862 +#define MT6397_VSRMCA15_CON18 0x025E
863 +#define MT6397_VSRMCA15_CON19 0x0260
864 +#define MT6397_VSRMCA15_CON20 0x0262
865 +#define MT6397_VSRMCA15_CON21 0x0264
866 +#define MT6397_VCORE_CON0 0x0266
867 +#define MT6397_VCORE_CON1 0x0268
868 +#define MT6397_VCORE_CON2 0x026A
869 +#define MT6397_VCORE_CON3 0x026C
870 +#define MT6397_VCORE_CON4 0x026E
871 +#define MT6397_VCORE_CON5 0x0270
872 +#define MT6397_VCORE_CON6 0x0272
873 +#define MT6397_VCORE_CON7 0x0274
874 +#define MT6397_VCORE_CON8 0x0276
875 +#define MT6397_VCORE_CON9 0x0278
876 +#define MT6397_VCORE_CON10 0x027A
877 +#define MT6397_VCORE_CON11 0x027C
878 +#define MT6397_VCORE_CON12 0x027E
879 +#define MT6397_VCORE_CON13 0x0280
880 +#define MT6397_VCORE_CON14 0x0282
881 +#define MT6397_VCORE_CON15 0x0284
882 +#define MT6397_VCORE_CON16 0x0286
883 +#define MT6397_VCORE_CON17 0x0288
884 +#define MT6397_VCORE_CON18 0x028A
885 +#define MT6397_VGPU_CON0 0x028C
886 +#define MT6397_VGPU_CON1 0x028E
887 +#define MT6397_VGPU_CON2 0x0290
888 +#define MT6397_VGPU_CON3 0x0292
889 +#define MT6397_VGPU_CON4 0x0294
890 +#define MT6397_VGPU_CON5 0x0296
891 +#define MT6397_VGPU_CON6 0x0298
892 +#define MT6397_VGPU_CON7 0x029A
893 +#define MT6397_VGPU_CON8 0x029C
894 +#define MT6397_VGPU_CON9 0x029E
895 +#define MT6397_VGPU_CON10 0x02A0
896 +#define MT6397_VGPU_CON11 0x02A2
897 +#define MT6397_VGPU_CON12 0x02A4
898 +#define MT6397_VGPU_CON13 0x02A6
899 +#define MT6397_VGPU_CON14 0x02A8
900 +#define MT6397_VGPU_CON15 0x02AA
901 +#define MT6397_VGPU_CON16 0x02AC
902 +#define MT6397_VGPU_CON17 0x02AE
903 +#define MT6397_VGPU_CON18 0x02B0
904 +#define MT6397_VIO18_CON0 0x0300
905 +#define MT6397_VIO18_CON1 0x0302
906 +#define MT6397_VIO18_CON2 0x0304
907 +#define MT6397_VIO18_CON3 0x0306
908 +#define MT6397_VIO18_CON4 0x0308
909 +#define MT6397_VIO18_CON5 0x030A
910 +#define MT6397_VIO18_CON6 0x030C
911 +#define MT6397_VIO18_CON7 0x030E
912 +#define MT6397_VIO18_CON8 0x0310
913 +#define MT6397_VIO18_CON9 0x0312
914 +#define MT6397_VIO18_CON10 0x0314
915 +#define MT6397_VIO18_CON11 0x0316
916 +#define MT6397_VIO18_CON12 0x0318
917 +#define MT6397_VIO18_CON13 0x031A
918 +#define MT6397_VIO18_CON14 0x031C
919 +#define MT6397_VIO18_CON15 0x031E
920 +#define MT6397_VIO18_CON16 0x0320
921 +#define MT6397_VIO18_CON17 0x0322
922 +#define MT6397_VIO18_CON18 0x0324
923 +#define MT6397_VPCA7_CON0 0x0326
924 +#define MT6397_VPCA7_CON1 0x0328
925 +#define MT6397_VPCA7_CON2 0x032A
926 +#define MT6397_VPCA7_CON3 0x032C
927 +#define MT6397_VPCA7_CON4 0x032E
928 +#define MT6397_VPCA7_CON5 0x0330
929 +#define MT6397_VPCA7_CON6 0x0332
930 +#define MT6397_VPCA7_CON7 0x0334
931 +#define MT6397_VPCA7_CON8 0x0336
932 +#define MT6397_VPCA7_CON9 0x0338
933 +#define MT6397_VPCA7_CON10 0x033A
934 +#define MT6397_VPCA7_CON11 0x033C
935 +#define MT6397_VPCA7_CON12 0x033E
936 +#define MT6397_VPCA7_CON13 0x0340
937 +#define MT6397_VPCA7_CON14 0x0342
938 +#define MT6397_VPCA7_CON15 0x0344
939 +#define MT6397_VPCA7_CON16 0x0346
940 +#define MT6397_VPCA7_CON17 0x0348
941 +#define MT6397_VPCA7_CON18 0x034A
942 +#define MT6397_VSRMCA7_CON0 0x034C
943 +#define MT6397_VSRMCA7_CON1 0x034E
944 +#define MT6397_VSRMCA7_CON2 0x0350
945 +#define MT6397_VSRMCA7_CON3 0x0352
946 +#define MT6397_VSRMCA7_CON4 0x0354
947 +#define MT6397_VSRMCA7_CON5 0x0356
948 +#define MT6397_VSRMCA7_CON6 0x0358
949 +#define MT6397_VSRMCA7_CON7 0x035A
950 +#define MT6397_VSRMCA7_CON8 0x035C
951 +#define MT6397_VSRMCA7_CON9 0x035E
952 +#define MT6397_VSRMCA7_CON10 0x0360
953 +#define MT6397_VSRMCA7_CON11 0x0362
954 +#define MT6397_VSRMCA7_CON12 0x0364
955 +#define MT6397_VSRMCA7_CON13 0x0366
956 +#define MT6397_VSRMCA7_CON14 0x0368
957 +#define MT6397_VSRMCA7_CON15 0x036A
958 +#define MT6397_VSRMCA7_CON16 0x036C
959 +#define MT6397_VSRMCA7_CON17 0x036E
960 +#define MT6397_VSRMCA7_CON18 0x0370
961 +#define MT6397_VSRMCA7_CON19 0x0372
962 +#define MT6397_VSRMCA7_CON20 0x0374
963 +#define MT6397_VSRMCA7_CON21 0x0376
964 +#define MT6397_VDRM_CON0 0x0378
965 +#define MT6397_VDRM_CON1 0x037A
966 +#define MT6397_VDRM_CON2 0x037C
967 +#define MT6397_VDRM_CON3 0x037E
968 +#define MT6397_VDRM_CON4 0x0380
969 +#define MT6397_VDRM_CON5 0x0382
970 +#define MT6397_VDRM_CON6 0x0384
971 +#define MT6397_VDRM_CON7 0x0386
972 +#define MT6397_VDRM_CON8 0x0388
973 +#define MT6397_VDRM_CON9 0x038A
974 +#define MT6397_VDRM_CON10 0x038C
975 +#define MT6397_VDRM_CON11 0x038E
976 +#define MT6397_VDRM_CON12 0x0390
977 +#define MT6397_VDRM_CON13 0x0392
978 +#define MT6397_VDRM_CON14 0x0394
979 +#define MT6397_VDRM_CON15 0x0396
980 +#define MT6397_VDRM_CON16 0x0398
981 +#define MT6397_VDRM_CON17 0x039A
982 +#define MT6397_VDRM_CON18 0x039C
983 +#define MT6397_BUCK_K_CON0 0x039E
984 +#define MT6397_BUCK_K_CON1 0x03A0
985 +#define MT6397_ANALDO_CON0 0x0400
986 +#define MT6397_ANALDO_CON1 0x0402
987 +#define MT6397_ANALDO_CON2 0x0404
988 +#define MT6397_ANALDO_CON3 0x0406
989 +#define MT6397_ANALDO_CON4 0x0408
990 +#define MT6397_ANALDO_CON5 0x040A
991 +#define MT6397_ANALDO_CON6 0x040C
992 +#define MT6397_ANALDO_CON7 0x040E
993 +#define MT6397_DIGLDO_CON0 0x0410
994 +#define MT6397_DIGLDO_CON1 0x0412
995 +#define MT6397_DIGLDO_CON2 0x0414
996 +#define MT6397_DIGLDO_CON3 0x0416
997 +#define MT6397_DIGLDO_CON4 0x0418
998 +#define MT6397_DIGLDO_CON5 0x041A
999 +#define MT6397_DIGLDO_CON6 0x041C
1000 +#define MT6397_DIGLDO_CON7 0x041E
1001 +#define MT6397_DIGLDO_CON8 0x0420
1002 +#define MT6397_DIGLDO_CON9 0x0422
1003 +#define MT6397_DIGLDO_CON10 0x0424
1004 +#define MT6397_DIGLDO_CON11 0x0426
1005 +#define MT6397_DIGLDO_CON12 0x0428
1006 +#define MT6397_DIGLDO_CON13 0x042A
1007 +#define MT6397_DIGLDO_CON14 0x042C
1008 +#define MT6397_DIGLDO_CON15 0x042E
1009 +#define MT6397_DIGLDO_CON16 0x0430
1010 +#define MT6397_DIGLDO_CON17 0x0432
1011 +#define MT6397_DIGLDO_CON18 0x0434
1012 +#define MT6397_DIGLDO_CON19 0x0436
1013 +#define MT6397_DIGLDO_CON20 0x0438
1014 +#define MT6397_DIGLDO_CON21 0x043A
1015 +#define MT6397_DIGLDO_CON22 0x043C
1016 +#define MT6397_DIGLDO_CON23 0x043E
1017 +#define MT6397_DIGLDO_CON24 0x0440
1018 +#define MT6397_DIGLDO_CON25 0x0442
1019 +#define MT6397_DIGLDO_CON26 0x0444
1020 +#define MT6397_DIGLDO_CON27 0x0446
1021 +#define MT6397_DIGLDO_CON28 0x0448
1022 +#define MT6397_DIGLDO_CON29 0x044A
1023 +#define MT6397_DIGLDO_CON30 0x044C
1024 +#define MT6397_DIGLDO_CON31 0x044E
1025 +#define MT6397_DIGLDO_CON32 0x0450
1026 +#define MT6397_DIGLDO_CON33 0x045A
1027 +#define MT6397_SPK_CON0 0x0600
1028 +#define MT6397_SPK_CON1 0x0602
1029 +#define MT6397_SPK_CON2 0x0604
1030 +#define MT6397_SPK_CON3 0x0606
1031 +#define MT6397_SPK_CON4 0x0608
1032 +#define MT6397_SPK_CON5 0x060A
1033 +#define MT6397_SPK_CON6 0x060C
1034 +#define MT6397_SPK_CON7 0x060E
1035 +#define MT6397_SPK_CON8 0x0610
1036 +#define MT6397_SPK_CON9 0x0612
1037 +#define MT6397_SPK_CON10 0x0614
1038 +#define MT6397_SPK_CON11 0x0616
1039 +#define MT6397_AUDDAC_CON0 0x0700
1040 +#define MT6397_AUDBUF_CFG0 0x0702
1041 +#define MT6397_AUDBUF_CFG1 0x0704
1042 +#define MT6397_AUDBUF_CFG2 0x0706
1043 +#define MT6397_AUDBUF_CFG3 0x0708
1044 +#define MT6397_AUDBUF_CFG4 0x070A
1045 +#define MT6397_IBIASDIST_CFG0 0x070C
1046 +#define MT6397_AUDACCDEPOP_CFG0 0x070E
1047 +#define MT6397_AUD_IV_CFG0 0x0710
1048 +#define MT6397_AUDCLKGEN_CFG0 0x0712
1049 +#define MT6397_AUDLDO_CFG0 0x0714
1050 +#define MT6397_AUDLDO_CFG1 0x0716
1051 +#define MT6397_AUDNVREGGLB_CFG0 0x0718
1052 +#define MT6397_AUD_NCP0 0x071A
1053 +#define MT6397_AUDPREAMP_CON0 0x071C
1054 +#define MT6397_AUDADC_CON0 0x071E
1055 +#define MT6397_AUDADC_CON1 0x0720
1056 +#define MT6397_AUDADC_CON2 0x0722
1057 +#define MT6397_AUDADC_CON3 0x0724
1058 +#define MT6397_AUDADC_CON4 0x0726
1059 +#define MT6397_AUDADC_CON5 0x0728
1060 +#define MT6397_AUDADC_CON6 0x072A
1061 +#define MT6397_AUDDIGMI_CON0 0x072C
1062 +#define MT6397_AUDLSBUF_CON0 0x072E
1063 +#define MT6397_AUDLSBUF_CON1 0x0730
1064 +#define MT6397_AUDENCSPARE_CON0 0x0732
1065 +#define MT6397_AUDENCCLKSQ_CON0 0x0734
1066 +#define MT6397_AUDPREAMPGAIN_CON0 0x0736
1067 +#define MT6397_ZCD_CON0 0x0738
1068 +#define MT6397_ZCD_CON1 0x073A
1069 +#define MT6397_ZCD_CON2 0x073C
1070 +#define MT6397_ZCD_CON3 0x073E
1071 +#define MT6397_ZCD_CON4 0x0740
1072 +#define MT6397_ZCD_CON5 0x0742
1073 +#define MT6397_NCP_CLKDIV_CON0 0x0744
1074 +#define MT6397_NCP_CLKDIV_CON1 0x0746
1075 +
1076 +#endif /* __MFD_MT6397_REGISTERS_H__ */
Staging tree of Mathias Kresin