target/linux/mediatek/patches/0064-arm-mediatek-add-mt7623-pcie-support.patch

   1 From 29ceb2449cb3622ccfba9eb1c77bf2ac4162464b Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 27 Jun 2015 13:15:29 +0200
   4 Subject: [PATCH 64/76] arm: mediatek: add mt7623 pcie support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/arm/mach-mediatek/Makefile |    2 +-
   9  arch/arm/mach-mediatek/pcie.c   |  383 +++++++++++++++++++++++++++++++++++++++
  10  arch/arm/mach-mediatek/pcie.h   |   14 ++
  11  3 files changed, 398 insertions(+), 1 deletion(-)
  12  create mode 100644 arch/arm/mach-mediatek/pcie.c
  13  create mode 100644 arch/arm/mach-mediatek/pcie.h
  14
  15 diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
  16 index 2116460..aca28a2 100644
  17 --- a/arch/arm/mach-mediatek/Makefile
  18 +++ b/arch/arm/mach-mediatek/Makefile
  19 @@ -1,4 +1,4 @@
  20  ifeq ($(CONFIG_SMP),y)
  21  obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o
  22  endif
  23 -obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o
  24 +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o pcie.o
  25 diff --git a/arch/arm/mach-mediatek/pcie.c b/arch/arm/mach-mediatek/pcie.c
  26 new file mode 100644
  27 index 0000000..8394712
  28 --- /dev/null
  29 +++ b/arch/arm/mach-mediatek/pcie.c
  30 @@ -0,0 +1,383 @@
  31 +/*
  32 + *  Mediatek MT7623 SoC PCIE support
  33 + *
  34 + *  Copyright (C) 2015 Mediatek
  35 + *  Copyright (C) 2015 John Crispin <blogic@openwrt.org>
  36 + *
  37 + *  This program is free software; you can redistribute it and/or modify it
  38 + *  under the terms of the GNU General Public License version 2 as published
  39 + *  by the Free Software Foundation.
  40 + */
  41 +
  42 +#include <linux/kernel.h>
  43 +#include <linux/pci.h>
  44 +#include <linux/ioport.h>
  45 +#include <linux/interrupt.h>
  46 +#include <linux/spinlock.h>
  47 +#include <linux/init.h>
  48 +#include <linux/io.h>
  49 +#include <linux/delay.h>
  50 +#include <asm/irq.h>
  51 +#include <asm/mach/pci.h>
  52 +#include <linux/module.h>
  53 +#include <linux/of.h>
  54 +#include <linux/of_irq.h>
  55 +#include <linux/of_pci.h>
  56 +#include <linux/reset.h>
  57 +#include <linux/platform_device.h>
  58 +
  59 +#include "pcie.h"
  60 +
  61 +#define PCICFG                 0x00
  62 +#define PCIINT                 0x08
  63 +#define PCIENA                 0x0C
  64 +#define CFGADDR                        0x20
  65 +#define CFGDATA                        0x24
  66 +#define MEMBASE                        0x28
  67 +#define IOBASE                 0x2C
  68 +
  69 +#define BAR0SETUP              0x10
  70 +#define IMBASEBAR0             0x18
  71 +#define PCIE_CLASS             0x34
  72 +#define PCIE_SISTAT            0x50
  73 +
  74 +#define MTK_PCIE_HIGH_PERF     BIT(14)
  75 +#define PCIEP0_BASE            0x2000
  76 +#define PCIEP1_BASE            0x3000
  77 +#define PCIEP2_BASE            0x4000
  78 +
  79 +#define PHY_P0_CTL             0x9000
  80 +#define PHY_P1_CTL             0xA000
  81 +#define PHY_P2_CTL             0x4000
  82 +
  83 +#define RSTCTL_PCIE0_RST       BIT(24)
  84 +#define RSTCTL_PCIE1_RST       BIT(25)
  85 +#define RSTCTL_PCIE2_RST       BIT(26)
  86 +
  87 +static void __iomem *pcie_base;
  88 +static int pcie_card_link;
  89 +
  90 +static struct mtk_pcie_port {
  91 +       int id;
  92 +       int enable;
  93 +       u32 base;
  94 +       u32 phy_base;
  95 +       u32 perst_n;
  96 +       u32 reset;
  97 +       u32 interrupt;
  98 +       u32 link;
  99 +} mtk_pcie_port[] = {
 100 +       { 0, 1, PCIEP0_BASE, PHY_P0_CTL, BIT(1), RSTCTL_PCIE0_RST, BIT(20) },
 101 +       { 1, 1, PCIEP1_BASE, PHY_P1_CTL, BIT(2), RSTCTL_PCIE1_RST, BIT(21) },
 102 +       { 2, 0, PCIEP2_BASE, PHY_P2_CTL, BIT(3), RSTCTL_PCIE2_RST, BIT(22) },
 103 +};
 104 +
 105 +#define mtk_foreach_port(p)            \
 106 +       for (p = mtk_pcie_port; p != &mtk_pcie_port[ARRAY_SIZE(mtk_pcie_port)]; p++)
 107 +
 108 +#define mtk_foreach_port_enabled(p)    \
 109 +       mtk_foreach_port(p)             \
 110 +               if (p->enable)
 111 +
 112 +#define mtk_foreach_port_link(p)       \
 113 +       mtk_foreach_port(p)             \
 114 +               if (p->link)
 115 +
 116 +static struct mtk_phy_init {
 117 +       uint32_t reg;
 118 +       uint32_t mask;
 119 +       uint32_t val;
 120 +} mtk_phy_init[] = {
 121 +       { 0xC00, 0x33000, 0x22000 },
 122 +       { 0xB04, 0xe0000000, 0x40000000 },
 123 +       { 0xB00, 0xe, 0x4 },
 124 +       { 0xC3C, 0xffff0000, 0x3c0000 },
 125 +       { 0xC48, 0xffff, 0x36 },
 126 +       { 0xC0C, 0x30000000, 0x10000000 },
 127 +       { 0xC08, 0x3800c0, 0xc0 },
 128 +       { 0xC10, 0xf0000, 0x20000 },
 129 +       { 0xC0C, 0xf000, 0x1000 },
 130 +       { 0xC14, 0xf0000, 0xa0000 },
 131 +};
 132 +
 133 +static inline void pcie_w32(u32 val, unsigned reg)
 134 +{
 135 +       iowrite32(val, pcie_base + reg);
 136 +}
 137 +
 138 +static inline u32 pcie_r32(unsigned reg)
 139 +{
 140 +       return ioread32(pcie_base + reg);
 141 +}
 142 +
 143 +static inline void pcie_m32(u32 mask, u32 val, unsigned reg)
 144 +{
 145 +       u32 v = pcie_r32(reg);
 146 +
 147 +       v &= mask;
 148 +       v |= val;
 149 +       pcie_w32(v, reg);
 150 +}
 151 +
 152 +static int pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 153 +{
 154 +       unsigned int slot = PCI_SLOT(devfn);
 155 +       u8 func = PCI_FUNC(devfn);
 156 +       u32 address;
 157 +       u32 data;
 158 +       u32 num = 0;
 159 +
 160 +       if (bus)
 161 +               num = bus->number;
 162 +
 163 +       address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc);
 164 +       pcie_m32(0xf0000000, address, CFGADDR);
 165 +       data = pcie_r32(CFGDATA);
 166 +
 167 +       switch (size) {
 168 +       case 1:
 169 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 170 +               break;
 171 +       case 2:
 172 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 173 +               break;
 174 +       case 4:
 175 +               *val = data;
 176 +               break;
 177 +       }
 178 +
 179 +       return PCIBIOS_SUCCESSFUL;
 180 +}
 181 +
 182 +static int pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 183 +{
 184 +       unsigned int slot = PCI_SLOT(devfn);
 185 +       u8 func = PCI_FUNC(devfn);
 186 +       u32 address;
 187 +       u32 data;
 188 +       u32 num = 0;
 189 +
 190 +       if (bus)
 191 +               num = bus->number;
 192 +
 193 +       address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc);
 194 +       pcie_m32(0xf0000000, address, CFGADDR);
 195 +       data = pcie_r32(CFGDATA);
 196 +
 197 +       switch (size) {
 198 +       case 1:
 199 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 200 +               (val << ((where & 3) << 3));
 201 +               break;
 202 +       case 2:
 203 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 204 +               (val << ((where & 3) << 3));
 205 +               break;
 206 +       case 4:
 207 +               data = val;
 208 +               break;
 209 +       }
 210 +
 211 +       pcie_w32(data, CFGDATA);
 212 +
 213 +       return PCIBIOS_SUCCESSFUL;
 214 +}
 215 +
 216 +static struct pci_ops mtk_pcie_ops = {
 217 +       .read   = pcie_config_read,
 218 +       .write  = pcie_config_write,
 219 +};
 220 +
 221 +static struct resource pci_mem = {
 222 +       .name   = "PCIe Memory space",
 223 +       .start  = MEM_DIRECT1,
 224 +       .end    = (u32) (MEM_DIRECT1 + (unsigned char *) 0x0fffffff),
 225 +       .flags  = IORESOURCE_MEM,
 226 +};
 227 +
 228 +static struct resource pci_io = {
 229 +       .name   = "PCIe IO space",
 230 +       .start  = IO_WIN,
 231 +       .end    = (u32) (IO_WIN + (unsigned char *) 0x0ffff),
 232 +       .flags  = IORESOURCE_IO,
 233 +};
 234 +
 235 +static int __init mtk_pcie_setup(int nr, struct pci_sys_data *sys)
 236 +{
 237 +       sys->mem_offset = 0;
 238 +       sys->io_offset = 0;
 239 +
 240 +       request_resource(&ioport_resource, &pci_io);
 241 +       request_resource(&iomem_resource, &pci_mem);
 242 +
 243 +       pci_add_resource_offset(&sys->resources, &pci_io, sys->io_offset);
 244 +       pci_add_resource_offset(&sys->resources, &pci_mem, sys->mem_offset);
 245 +
 246 +       return 1;
 247 +}
 248 +
 249 +static struct pci_bus * __init mtk_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 250 +{
 251 +       return pci_scan_root_bus(NULL, sys->busnr, &mtk_pcie_ops, sys,
 252 +                                &sys->resources);
 253 +}
 254 +
 255 +static int __init mtk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 256 +{
 257 +       u16 cmd;
 258 +       u32 val;
 259 +
 260 +       if (dev->bus->number == 0) {
 261 +               pcie_config_write(NULL, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 262 +               pcie_config_read(NULL, slot, 0, PCI_BASE_ADDRESS_0, &val);
 263 +               printk("BAR0 at bus %d, slot %d\n", dev->bus->number, slot);
 264 +       }
 265 +
 266 +       printk("bus=0x%x, slot = 0x%x, pin=0x%x, irq=0x%x\n", dev->bus->number, slot, pin, dev->irq);
 267 +
 268 +       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
 269 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);
 270 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 271 +       cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 272 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 273 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 274 +
 275 +       return dev->irq;
 276 +}
 277 +
 278 +static void __init mtk_pcie_preinit(void)
 279 +{
 280 +       struct mtk_pcie_port *port;
 281 +       u32 val = 0;
 282 +       int i;
 283 +
 284 +       pcibios_min_io = 0;
 285 +       pcibios_min_mem = 0;
 286 +
 287 +#if defined (CONFIG_PCIE_PORT2)
 288 +       printk("%s: PCIe/USB3 combo PHY mode (%x) =%x\n", __func__, SYSCFG1, REGDATA(SYSCFG1));
 289 +       REGDATA(SYSCFG1) &= ~(0x300000);
 290 +       printk("%s: PCIe/USB3 combo PHY mode (%x) =%x\n", __func__, SYSCFG1, REGDATA(SYSCFG1));
 291 +#endif
 292 +
 293 +       /* PCIe RC Reset */
 294 +       val = 0;
 295 +       mtk_foreach_port_enabled(port)
 296 +               val |= port->reset;
 297 +       REGDATA(RSTCTL) |= val;
 298 +       mdelay(10);
 299 +       REGDATA(RSTCTL) &= ~val;
 300 +       mdelay(10);
 301 +
 302 +       /* Configure PCIe PHY */
 303 +       mtk_foreach_port_enabled(port) {
 304 +               for (i = 0; i < ARRAY_SIZE(mtk_phy_init); i++) {
 305 +                       u32 val = pcie_r32(port->phy_base + mtk_phy_init[i].reg);
 306 +                       val &= ~mtk_phy_init[i].mask;
 307 +                       val |= mtk_phy_init[i].val;
 308 +                       pcie_w32(val, port->phy_base + mtk_phy_init[i].reg);
 309 +               }
 310 +               mdelay(10);
 311 +       }
 312 +
 313 +       /* Enable RC */
 314 +       mtk_foreach_port_enabled(port) {
 315 +               val = 0;
 316 +               pcie_config_read(NULL, port->id, 0, 0x73c, &val);
 317 +               val &= ~(0x9fff)<<16;
 318 +               val |= 0x806c<<16;
 319 +               pcie_config_write(NULL, port->id, 0, 0x73c, val);
 320 +       }
 321 +
 322 +       /* PCIe EP reset */
 323 +       val = 0;
 324 +       mtk_foreach_port_enabled(port)
 325 +               val |= port->perst_n;
 326 +       val |= MTK_PCIE_HIGH_PERF;
 327 +       pcie_w32(pcie_r32(PCICFG) | val, PCICFG);
 328 +       mdelay(10);
 329 +       pcie_w32(pcie_r32(PCICFG) & ~val, PCICFG);
 330 +       mdelay(10);
 331 +
 332 +       /* check the link status */
 333 +       val = 0;
 334 +       mtk_foreach_port_enabled(port) {
 335 +               if ((pcie_r32(port->base + PCIE_SISTAT) & 0x1))
 336 +                       port->link = 1;
 337 +               else
 338 +                       val |= port->reset;
 339 +       }
 340 +       REGDATA(RSTCTL) |= val;
 341 +
 342 +       mtk_foreach_port_link(port)
 343 +               pcie_card_link++;
 344 +
 345 +       printk("PCIe Link count = %d\n", pcie_card_link);
 346 +       if (!pcie_card_link)
 347 +               return;
 348 +
 349 +       pcie_w32(MEM_WIN, MEMBASE);
 350 +       pcie_w32(IO_WIN, IOBASE);
 351 +
 352 +       mtk_foreach_port_link(port) {
 353 +               pcie_m32(0, port->interrupt, PCIENA);
 354 +               pcie_w32(0x7FFF0001, port->base + BAR0SETUP);
 355 +               pcie_w32(MEMORY_BASE, port->base + IMBASEBAR0);
 356 +               pcie_w32(0x06040001, port->base + PCIE_CLASS);
 357 +               printk("PCIE%d Setup OK\n", port->id);
 358 +       }
 359 +       val = 0;
 360 +
 361 +       pcie_config_read(NULL, pcie_card_link - 1, 0, 0x4, &val);
 362 +       pcie_config_write(NULL, pcie_card_link - 1, 0, 0x4, val|0x4);
 363 +       pcie_config_read(NULL, pcie_card_link - 1, 0, 0x70c, &val);
 364 +       val &= ~(0xff3) << 8;
 365 +       val |= 0x50 << 8;
 366 +       pcie_config_write(NULL, pcie_card_link - 1, 0, 0x70c, val);
 367 +       pcie_config_read(NULL, pcie_card_link - 1, 0, 0x70c, &val);
 368 +}
 369 +
 370 +static struct hw_pci mtk_pci __initdata = {
 371 +       .nr_controllers         = 1,
 372 +       .map_irq                = mtk_pcie_map_irq,
 373 +       .setup                  = mtk_pcie_setup,
 374 +       .scan                   = mtk_pcie_scan_bus,
 375 +       .preinit                = mtk_pcie_preinit,
 376 +};
 377 +
 378 +extern void mt7623_ethifsys_init(void);
 379 +static int mtk_pcie_probe(struct platform_device *pdev)
 380 +{
 381 +       struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 382 +
 383 +       pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
 384 +        if (!pcie_base)
 385 +               return -ENOMEM;
 386 +
 387 +       mt7623_ethifsys_init();
 388 +       pci_common_init_dev(&pdev->dev, &mtk_pci);
 389 +
 390 +       return 0;
 391 +}
 392 +
 393 +static const struct of_device_id mtk_pcie_ids[] = {
 394 +       { .compatible = "mediatek,mt7623-pcie" },
 395 +       {},
 396 +};
 397 +MODULE_DEVICE_TABLE(of, mtk_pcie_ids);
 398 +
 399 +static struct platform_driver mtk_pcie_driver = {
 400 +       .probe = mtk_pcie_probe,
 401 +       .driver = {
 402 +               .name = "mt7623-pcie",
 403 +               .owner = THIS_MODULE,
 404 +               .of_match_table = of_match_ptr(mtk_pcie_ids),
 405 +       },
 406 +};
 407 +
 408 +static int __init mtk_pcie_init(void)
 409 +{
 410 +       return platform_driver_register(&mtk_pcie_driver);
 411 +}
 412 +
 413 +late_initcall(mtk_pcie_init);
 414 diff --git a/arch/arm/mach-mediatek/pcie.h b/arch/arm/mach-mediatek/pcie.h
 415 new file mode 100644
 416 index 0000000..400a760e
 417 --- /dev/null
 418 +++ b/arch/arm/mach-mediatek/pcie.h
 419 @@ -0,0 +1,14 @@
 420 +#define SYSCTL_BASE    0xFA000000
 421 +#define MEM_WIN                0x1A150000
 422 +#define IO_WIN         0x1A160000
 423 +#define MEM_DIRECT1    0x60000000
 424 +#define MEMORY_BASE    0x80000000
 425 +
 426 +#define REGADDR(x, y)  (x##_BASE + y)
 427 +#define REGDATA(x)                     *((volatile unsigned int *)(x))
 428 +
 429 +#define SYSCFG1                REGADDR(SYSCTL, 0x14)
 430 +#define RSTCTL         REGADDR(SYSCTL, 0x34)
 431 +
 432 +
 433 +
 434 --
 435 1.7.10.4
 436