1 From a6bf117b5fe3acd76bbc45cc87fd80f589136e59 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 27 Jun 2015 13:14:42 +0200
4 Subject: [PATCH 66/76] arm: mediatek: add m7623 devicetree
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/arm/boot/dts/Makefile | 1 +
9 arch/arm/boot/dts/mt7623-evb.dts | 162 ++++++++++++++++++
10 arch/arm/boot/dts/mt7623.dtsi | 348 ++++++++++++++++++++++++++++++++++++++
11 3 files changed, 511 insertions(+)
12 create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
13 create mode 100644 arch/arm/boot/dts/mt7623.dtsi
15 --- a/arch/arm/boot/dts/Makefile
16 +++ b/arch/arm/boot/dts/Makefile
17 @@ -658,6 +658,7 @@ dtb-$(CONFIG_MACH_DOVE) += \
18 dtb-$(CONFIG_ARCH_MEDIATEK) += \
26 +++ b/arch/arm/boot/dts/mt7623-evb.dts
29 + * Copyright (c) 2014 MediaTek Inc.
30 + * Author: Joe.C <yingjoe.chen@mediatek.com>
32 + * This program is free software; you can redistribute it and/or modify
33 + * it under the terms of the GNU General Public License version 2 as
34 + * published by the Free Software Foundation.
36 + * This program is distributed in the hope that it will be useful,
37 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
38 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
39 + * GNU General Public License for more details.
43 +#include <dt-bindings/gpio/gpio.h>
44 +#include "mt7623.dtsi"
47 + model = "MediaTek MT7623 Evaluation Board";
48 + compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
51 + stdout-path = &uart2;
55 + reg = <0 0x80000000 0 0x10000000>;
58 + usb_p1_vbus: fixedregulator@0 {
59 + compatible = "regulator-fixed";
60 + regulator-name = "usb_vbus";
61 + regulator-min-microvolt = <5000000>;
62 + regulator-max-microvolt = <5000000>;
63 + gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
70 + pinctrl_uart2_default: uart2@0 {
72 + pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
73 + <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
77 + pinctrl_i2c0_default: i2c@0 {
79 + pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
80 + <MT7623_PIN_76_SCL0_FUNC_SCL0>;
84 + pinctrl_pcie_default: pcie@0 {
86 + pinmux = <MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N>,
87 + <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
88 + <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>,
89 + <MT7623_PIN_250_GPIO250_FUNC_PCIE0_CLKREQ_N>,
90 + <MT7623_PIN_251_GPIO251_FUNC_PCIE0_WAKE_N>,
91 + <MT7623_PIN_252_GPIO252_FUNC_PCIE1_CLKREQ_N>,
92 + <MT7623_PIN_253_GPIO253_FUNC_PCIE1_WAKE_N>,
93 + <MT7623_PIN_254_GPIO254_FUNC_PCIE2_CLKREQ_N>,
94 + <MT7623_PIN_255_GPIO255_FUNC_PCIE2_WAKE_N>;
98 + pinctrl_spi_default: spi@0 {
100 + pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
101 + <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
102 + <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>,
103 + <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>;
116 + pinctrl-names = "default";
117 + pinctrl-0 = <&pinctrl_uart2_default>;
123 + pinctrl-names = "default";
124 + pinctrl-0 = <&pinctrl_i2c0_default>;
130 + pinctrl-names = "default";
131 + pinctrl-0 = <&pinctrl_spi_default>;
134 + #address-cells = <1>;
136 + compatible = "mx25l12805d";
138 + linux,modalias = "m25p80", "w25q128";
139 + spi-max-frequency = <10000000>;
143 + reg = <0x0 0x30000>;
148 + label = "u-boot-env";
149 + reg = <0x30000 0x10000>;
153 + factory: partition@40000 {
155 + reg = <0x40000 0x10000>;
160 + label = "firmware";
161 + reg = <0x50000 0xfb0000>;
169 +// pinctrl-names = "default", "state_uhs";
170 +// pinctrl-0 = <&mmc0_pins_default>;
171 +// pinctrl-1 = <&mmc0_pins_uhs>;
173 + max-frequency = <50000000>;
175 +// vmmc-supply = <&mt6397_vemc_3v3_reg>;
176 +// vqmmc-supply = <&mt6397_vio18_reg>;
181 + reg-p1-vbus-supply = <&usb_p1_vbus>;
187 + pinctrl-names = "default";
188 + pinctrl-0 = <&pinctrl_pcie_default>;
191 +++ b/arch/arm/boot/dts/mt7623.dtsi
194 + * Copyright (c) 2014 MediaTek Inc.
195 + * Author: Joe.C <yingjoe.chen@mediatek.com>
197 + * This program is free software; you can redistribute it and/or modify
198 + * it under the terms of the GNU General Public License version 2 as
199 + * published by the Free Software Foundation.
201 + * This program is distributed in the hope that it will be useful,
202 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
203 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
204 + * GNU General Public License for more details.
207 +#include <dt-bindings/clock/mt7623-clk.h>
208 +#include <dt-bindings/interrupt-controller/irq.h>
209 +#include <dt-bindings/interrupt-controller/arm-gic.h>
210 +#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
211 +#include <dt-bindings/reset-controller/mt7623-resets.h>
212 +#include "skeleton64.dtsi"
215 + compatible = "mediatek,mt7623";
216 + interrupt-parent = <&sysirq>;
219 + #address-cells = <1>;
221 + enable-method = "mediatek,mt65xx-smp";
223 + device_type = "cpu";
224 + compatible = "arm,cortex-a7";
228 + device_type = "cpu";
229 + compatible = "arm,cortex-a7";
233 + device_type = "cpu";
234 + compatible = "arm,cortex-a7";
238 + device_type = "cpu";
239 + compatible = "arm,cortex-a7";
245 + clk26m: oscillator@0 {
246 + compatible = "fixed-clock";
247 + #clock-cells = <0>;
248 + clock-frequency = <26000000>;
249 + clock-output-names = "clk26m";
252 + clk32k: oscillator@1 {
253 + compatible = "fixed-clock";
254 + #clock-cells = <0>;
255 + clock-frequency = <32000>;
256 + clock-output-names = "clk32k";
260 + compatible = "arm,armv7-timer";
261 + interrupt-parent = <&gic>;
262 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
263 + IRQ_TYPE_LEVEL_LOW)>,
264 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
265 + IRQ_TYPE_LEVEL_LOW)>,
266 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
267 + IRQ_TYPE_LEVEL_LOW)>,
268 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
269 + IRQ_TYPE_LEVEL_LOW)>;
270 + clock-frequency = <13000000>;
271 + arm,cpu-registers-not-fw-configured;
275 + cpu_thermal: cpu_thermal {
276 + polling-delay-passive = <1000>;
277 + polling-delay = <5000>;
279 + thermal-sensors = <&thermal 1>;
284 + #address-cells = <2>;
286 + compatible = "simple-bus";
289 + topckgen: topckgen@10000000 {
290 + compatible = "mediatek,mt7623-topckgen";
291 + reg = <0 0x10000000 0 0x1000>;
292 + #clock-cells = <1>;
295 + infracfg: infracfg@10001000 {
296 + compatible = "mediatek,mt7623-infracfg", "syscon";
297 + reg = <0 0x10001000 0 0x1000>;
298 + #clock-cells = <1>;
299 + #reset-cells = <1>;
302 + pericfg: pericfg@10003000 {
303 + compatible = "mediatek,mt7623-pericfg", "syscon";
304 + reg = <0 0x10003000 0 0x1000>;
305 + #clock-cells = <1>;
306 + #reset-cells = <1>;
310 + * Pinctrl access register at 0x10005000 through regmap.
311 + * Register 0x1000b000 is used by EINT.
313 + pio: pinctrl@10005000 {
314 + compatible = "mediatek,mt7623-pinctrl";
315 + reg = <0 0x1000b000 0 0x1000>;
316 + mediatek,pctl-regmap = <&syscfg_pctl_a>;
320 + interrupt-controller;
321 + #interrupt-cells = <2>;
322 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
325 + syscfg_pctl_a: syscfg_pctl_a@10005000 {
326 + compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
327 + reg = <0 0x10005000 0 0x1000>;
330 + wdt: watchdog@10007000 {
331 + compatible = "mediatek,mt7623-wdt", "mediatek,mt6589-wdt";
332 + reg = <0 0x10007000 0 0x18>;
335 + timer: timer@10008000 {
336 + compatible = "mediatek,mt7623-timer",
337 + "mediatek,mt6577-timer";
338 + reg = <0 0x10008000 0 0x80>;
339 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
340 + clocks = <&topckgen CLK_TOP_AXI_SEL>,
341 + <&topckgen CLK_TOP_RTC_SEL>;
342 + clock-names = "system-clk", "rtc-clk";
345 + sysirq: interrupt-controller@10200100 {
346 + compatible = "mediatek,mt7623-sysirq",
347 + "mediatek,mt6577-sysirq";
348 + interrupt-controller;
349 + #interrupt-cells = <3>;
350 + interrupt-parent = <&gic>;
351 + reg = <0 0x10200100 0 0x1c>;
354 + apmixedsys: apmixedsys@10209000 {
355 + compatible = "mediatek,mt7623-apmixedsys";
356 + reg = <0 0x10209000 0 0x1000>;
357 + #clock-cells = <1>;
360 + gic: interrupt-controller@10211000 {
361 + compatible = "arm,cortex-a7-gic";
362 + interrupt-controller;
363 + #interrupt-cells = <3>;
364 + interrupt-parent = <&gic>;
365 + reg = <0 0x10211000 0 0x1000>,
366 + <0 0x10212000 0 0x1000>,
367 + <0 0x10214000 0 0x2000>,
368 + <0 0x10216000 0 0x2000>;
371 + auxadc: auxadc@11001000 {
372 + compatible = "mediatek,mt7623-auxadc", "mediatek,mt8173-auxadc";
373 + reg = <0 0x11001000 0 0x1000>;
376 + uart0: serial@11006000 {
377 + compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart";
378 + reg = <0 0x11002000 0 0x400>;
379 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
380 + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
381 + clock-names = "baud", "bus";
383 + status = "disabled";
386 + uart1: serial@11007000 {
387 + compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart";
388 + reg = <0 0x11003000 0 0x400>;
389 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
390 + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
391 + clock-names = "baud", "bus";
393 + status = "disabled";
396 + uart2: serial@11008000 {
397 + compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart";
398 + reg = <0 0x11004000 0 0x400>;
399 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
400 + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
401 + clock-names = "baud", "bus";
403 + status = "disabled";
406 + uart3: serial@11009000 {
407 + compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart";
408 + reg = <0 0x11005000 0 0x400>;
409 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
410 + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
411 + clock-names = "baud", "bus";
413 + status = "disabled";
416 + spi: spi@1100a000 {
417 + compatible = "medi/THEatek,mt7623-spi", "mediatek,mt6589-spi";
418 + reg = <0 0x1100a000 0 0x1000>;
419 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
420 + clocks = <&pericfg CLK_PERI_SPI0>;
421 + clock-names = "main";
423 + status = "disabled";
426 + thermal: thermal@1100b000 {
427 + #thermal-sensor-cells = <1>;
428 + compatible = "mediatek,mt7623-thermal", "mediatek,mt8173-thermal";
429 + reg = <0 0x1100b000 0 0x1000>;
430 + interrupts = <0 38 IRQ_TYPE_LEVEL_LOW>;
431 + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
432 + clock-names = "therm", "auxadc";
433 + resets = <&pericfg MT7623_PERI_THERM_SW_RST>;
434 + reset-names = "therm";
435 + auxadc = <&auxadc>;
436 + apmixedsys = <&apmixedsys>;
438 + status = "disabled";
441 + i2c0: i2c@11007000 {
442 + compatible = "mediatek,mt7623-i2c", "mediatek,mt6577-i2c";
443 + reg = <0 0x11007000 0 0x70>,
444 + <0 0x11000300 0 0x80>;
445 + interrupts = <0 44 IRQ_TYPE_LEVEL_LOW>;
446 + clock-frequency = <400000>;
448 + clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
449 + clock-names = "main", "dma";
451 + status = "disabled";
454 + mmc0: mmc@11230000 {
455 + compatible = "mediatek,mt7623-mmc",
456 + "mediatek,mt8135-mmc";
457 + reg = <0 0x11230000 0 0x1000>;
458 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
459 + clocks = <&pericfg CLK_PERI_MSDC20_1>,
460 + <&topckgen CLK_TOP_MSDC30_0_SEL>;
461 + clock-names = "source", "hclk";
462 + status = "disabled";
465 + usb: usb30@11270000 {
466 + compatible = "mediatek,mt7623-xhci", "mediatek,mt8173-xhci", "generic-xhci";
467 + reg = <0 0x11270000 0 0x1000>;
468 + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
469 + usb-phy = <&u3phy>;
473 + u3phy: usb-phy@11271000 {
474 + compatible = "mediatek,mt7623-u3phy", "mediatek,mt8173-u3phy";
475 + reg = <0 0x11271000 0 0x3000>,
476 + <0 0x11280000 0 0x20000>;
477 +// power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
478 +// reg-vusb33-supply = <&mt6397_vusb_reg>;
479 + clocks = <&pericfg CLK_PERI_USB0>,
480 + <&pericfg CLK_PERI_USB1>,
481 + <&topckgen CLK_TOP_USB20_SEL>;
482 +// <&apmixedsys CLK_APMIXED_REF2USB_TX>;
483 + clock-names = "wakeup_deb_p0",
491 + ethernet@1B100000 {
492 + compatible = "mediatek,mt7623-net";
493 + interrupts = <0 200 IRQ_TYPE_LEVEL_LOW>;
496 + pcie: pcie@1a140000 {
497 + compatible = "mediatek,mt7623-pcie";
498 + reg = <0 0x1a140000 0 0x10000>;
500 + #address-cells = <3>;
503 + device_type = "pci";
505 + bus-range = <0 255>;
507 + 0x02000000 0 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
508 + 0x01000000 0 0 0x00000000 0x1A160000 0 0x00010000 /* io space */
512 + reg = <0x0000 0 0 0 0>;
514 + #address-cells = <3>;
517 + device_type = "pci";
521 + reg = <0x0800 0 0 0 0>;
523 + #address-cells = <3>;
526 + device_type = "pci";
530 + reg = <0x1000 0 0 0 0>;
532 + #address-cells = <3>;
535 + device_type = "pci";
538 + status = "disabled";