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kernel: update 4.1 to 4.1.13
[openwrt/staging/mkresin.git] / target / linux / mediatek / patches / 0072-mfd.patch
1 From 1a4dcc30578512d687528adcf963203faee50d83 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 3 Jul 2015 05:45:17 +0200
4 Subject: [PATCH 72/76] mfd
5
6 ---
7 drivers/mfd/mt6323-core.c | 168 +++----
8 drivers/regulator/mt6323-regulator.c | 218 ++++----
9 include/linux/mfd/mt6323/core.h | 76 +--
10 include/linux/mfd/mt6323/registers.h | 745 +++++++++++++++-------------
11 include/linux/regulator/mt6323-regulator.h | 37 ++
12 5 files changed, 636 insertions(+), 608 deletions(-)
13 create mode 100644 include/linux/regulator/mt6323-regulator.h
14
15 --- a/drivers/mfd/mt6323-core.c
16 +++ b/drivers/mfd/mt6323-core.c
17 @@ -18,111 +18,99 @@
18 #include <linux/of_irq.h>
19 #include <linux/regmap.h>
20 #include <linux/mfd/core.h>
21 -#include <linux/mfd/mt6397/core.h>
22 -#include <linux/mfd/mt6397/registers.h>
23 +#include <linux/mfd/mt6323/core.h>
24 +#include <linux/mfd/mt6323/registers.h>
25
26 -static const struct mfd_cell mt6397_devs[] = {
27 +static const struct mfd_cell mt6323_devs[] = {
28 {
29 - .name = "mt6397-rtc",
30 - .of_compatible = "mediatek,mt6397-rtc",
31 - }, {
32 - .name = "mt6397-regulator",
33 - .of_compatible = "mediatek,mt6397-regulator",
34 - }, {
35 - .name = "mt6397-codec",
36 - .of_compatible = "mediatek,mt6397-codec",
37 - }, {
38 - .name = "mt6397-clk",
39 - .of_compatible = "mediatek,mt6397-clk",
40 - }, {
41 - .name = "mediatek-mt6397-pinctrl",
42 - .of_compatible = "mediatek,mt6397-pinctrl",
43 + .name = "mt6323-regulator",
44 + .of_compatible = "mediatek,mt6323-regulator",
45 },
46 };
47
48 -static void mt6397_irq_lock(struct irq_data *data)
49 +static void mt6323_irq_lock(struct irq_data *data)
50 {
51 - struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
52 + struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq);
53
54 - mutex_lock(&mt6397->irqlock);
55 + mutex_lock(&mt6323->irqlock);
56 }
57
58 -static void mt6397_irq_sync_unlock(struct irq_data *data)
59 +static void mt6323_irq_sync_unlock(struct irq_data *data)
60 {
61 - struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
62 + struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq);
63
64 - regmap_write(mt6397->regmap, MT6397_INT_CON0, mt6397->irq_masks_cur[0]);
65 - regmap_write(mt6397->regmap, MT6397_INT_CON1, mt6397->irq_masks_cur[1]);
66 + regmap_write(mt6323->regmap, MT6323_INT_CON0, mt6323->irq_masks_cur[0]);
67 + regmap_write(mt6323->regmap, MT6323_INT_CON1, mt6323->irq_masks_cur[1]);
68
69 - mutex_unlock(&mt6397->irqlock);
70 + mutex_unlock(&mt6323->irqlock);
71 }
72
73 -static void mt6397_irq_disable(struct irq_data *data)
74 +static void mt6323_irq_disable(struct irq_data *data)
75 {
76 - struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
77 + struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq);
78 int shift = data->hwirq & 0xf;
79 int reg = data->hwirq >> 4;
80
81 - mt6397->irq_masks_cur[reg] &= ~BIT(shift);
82 + mt6323->irq_masks_cur[reg] &= ~BIT(shift);
83 }
84
85 -static void mt6397_irq_enable(struct irq_data *data)
86 +static void mt6323_irq_enable(struct irq_data *data)
87 {
88 - struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
89 + struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq);
90 int shift = data->hwirq & 0xf;
91 int reg = data->hwirq >> 4;
92
93 - mt6397->irq_masks_cur[reg] |= BIT(shift);
94 + mt6323->irq_masks_cur[reg] |= BIT(shift);
95 }
96
97 -static struct irq_chip mt6397_irq_chip = {
98 - .name = "mt6397-irq",
99 - .irq_bus_lock = mt6397_irq_lock,
100 - .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
101 - .irq_enable = mt6397_irq_enable,
102 - .irq_disable = mt6397_irq_disable,
103 +static struct irq_chip mt6323_irq_chip = {
104 + .name = "mt6323-irq",
105 + .irq_bus_lock = mt6323_irq_lock,
106 + .irq_bus_sync_unlock = mt6323_irq_sync_unlock,
107 + .irq_enable = mt6323_irq_enable,
108 + .irq_disable = mt6323_irq_disable,
109 };
110
111 -static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
112 +static void mt6323_irq_handle_reg(struct mt6323_chip *mt6323, int reg,
113 int irqbase)
114 {
115 unsigned int status;
116 int i, irq, ret;
117
118 - ret = regmap_read(mt6397->regmap, reg, &status);
119 + ret = regmap_read(mt6323->regmap, reg, &status);
120 if (ret) {
121 - dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
122 + dev_err(mt6323->dev, "Failed to read irq status: %d\n", ret);
123 return;
124 }
125
126 for (i = 0; i < 16; i++) {
127 if (status & BIT(i)) {
128 - irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
129 + irq = irq_find_mapping(mt6323->irq_domain, irqbase + i);
130 if (irq)
131 handle_nested_irq(irq);
132 }
133 }
134
135 - regmap_write(mt6397->regmap, reg, status);
136 + regmap_write(mt6323->regmap, reg, status);
137 }
138
139 -static irqreturn_t mt6397_irq_thread(int irq, void *data)
140 +static irqreturn_t mt6323_irq_thread(int irq, void *data)
141 {
142 - struct mt6397_chip *mt6397 = data;
143 + struct mt6323_chip *mt6323 = data;
144
145 - mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS0, 0);
146 - mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS1, 16);
147 + mt6323_irq_handle_reg(mt6323, MT6323_INT_STATUS0, 0);
148 + mt6323_irq_handle_reg(mt6323, MT6323_INT_STATUS1, 16);
149
150 return IRQ_HANDLED;
151 }
152
153 -static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
154 +static int mt6323_irq_domain_map(struct irq_domain *d, unsigned int irq,
155 irq_hw_number_t hw)
156 {
157 - struct mt6397_chip *mt6397 = d->host_data;
158 + struct mt6323_chip *mt6323 = d->host_data;
159
160 - irq_set_chip_data(irq, mt6397);
161 - irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
162 + irq_set_chip_data(irq, mt6323);
163 + irq_set_chip_and_handler(irq, &mt6323_irq_chip, handle_level_irq);
164 irq_set_nested_thread(irq, 1);
165 #ifdef CONFIG_ARM
166 set_irq_flags(irq, IRQF_VALID);
167 @@ -133,98 +121,98 @@ static int mt6397_irq_domain_map(struct
168 return 0;
169 }
170
171 -static struct irq_domain_ops mt6397_irq_domain_ops = {
172 - .map = mt6397_irq_domain_map,
173 +static struct irq_domain_ops mt6323_irq_domain_ops = {
174 + .map = mt6323_irq_domain_map,
175 };
176
177 -static int mt6397_irq_init(struct mt6397_chip *mt6397)
178 +static int mt6323_irq_init(struct mt6323_chip *mt6323)
179 {
180 int ret;
181
182 - mutex_init(&mt6397->irqlock);
183 + mutex_init(&mt6323->irqlock);
184
185 /* Mask all interrupt sources */
186 - regmap_write(mt6397->regmap, MT6397_INT_CON0, 0x0);
187 - regmap_write(mt6397->regmap, MT6397_INT_CON1, 0x0);
188 + regmap_write(mt6323->regmap, MT6323_INT_CON0, 0x0);
189 + regmap_write(mt6323->regmap, MT6323_INT_CON1, 0x0);
190
191 - mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
192 - MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
193 - if (!mt6397->irq_domain) {
194 - dev_err(mt6397->dev, "could not create irq domain\n");
195 + mt6323->irq_domain = irq_domain_add_linear(mt6323->dev->of_node,
196 + MT6323_IRQ_NR, &mt6323_irq_domain_ops, mt6323);
197 + if (!mt6323->irq_domain) {
198 + dev_err(mt6323->dev, "could not create irq domain\n");
199 return -ENOMEM;
200 }
201
202 - ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
203 - mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
204 + ret = devm_request_threaded_irq(mt6323->dev, mt6323->irq, NULL,
205 + mt6323_irq_thread, IRQF_ONESHOT, "mt6323-pmic", mt6323);
206 if (ret) {
207 - dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
208 - mt6397->irq, ret);
209 + dev_err(mt6323->dev, "failed to register irq=%d; err: %d\n",
210 + mt6323->irq, ret);
211 return ret;
212 }
213
214 return 0;
215 }
216
217 -static int mt6397_probe(struct platform_device *pdev)
218 +static int mt6323_probe(struct platform_device *pdev)
219 {
220 int ret;
221 - struct mt6397_chip *mt6397;
222 + struct mt6323_chip *mt6323;
223
224 - mt6397 = devm_kzalloc(&pdev->dev, sizeof(*mt6397), GFP_KERNEL);
225 - if (!mt6397)
226 + mt6323 = devm_kzalloc(&pdev->dev, sizeof(*mt6323), GFP_KERNEL);
227 + if (!mt6323)
228 return -ENOMEM;
229
230 - mt6397->dev = &pdev->dev;
231 + mt6323->dev = &pdev->dev;
232 /*
233 - * mt6397 MFD is child device of soc pmic wrapper.
234 + * mt6323 MFD is child device of soc pmic wrapper.
235 * Regmap is set from its parent.
236 */
237 - mt6397->regmap = dev_get_regmap(pdev->dev.parent, NULL);
238 - if (!mt6397->regmap)
239 + mt6323->regmap = dev_get_regmap(pdev->dev.parent, NULL);
240 + if (!mt6323->regmap)
241 return -ENODEV;
242
243 - platform_set_drvdata(pdev, mt6397);
244 + platform_set_drvdata(pdev, mt6323);
245
246 - mt6397->irq = platform_get_irq(pdev, 0);
247 - if (mt6397->irq > 0) {
248 - ret = mt6397_irq_init(mt6397);
249 + mt6323->irq = platform_get_irq(pdev, 0);
250 + if (mt6323->irq > 0) {
251 + ret = mt6323_irq_init(mt6323);
252 if (ret)
253 return ret;
254 }
255
256 - ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
257 - ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
258 + ret = mfd_add_devices(&pdev->dev, -1, mt6323_devs,
259 + ARRAY_SIZE(mt6323_devs), NULL, 0, NULL);
260 if (ret)
261 dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
262
263 return ret;
264 }
265
266 -static int mt6397_remove(struct platform_device *pdev)
267 +static int mt6323_remove(struct platform_device *pdev)
268 {
269 mfd_remove_devices(&pdev->dev);
270
271 return 0;
272 }
273
274 -static const struct of_device_id mt6397_of_match[] = {
275 - { .compatible = "mediatek,mt6397" },
276 +static const struct of_device_id mt6323_of_match[] = {
277 + { .compatible = "mediatek,mt6323" },
278 { }
279 };
280 -MODULE_DEVICE_TABLE(of, mt6397_of_match);
281 +MODULE_DEVICE_TABLE(of, mt6323_of_match);
282
283 -static struct platform_driver mt6397_driver = {
284 - .probe = mt6397_probe,
285 - .remove = mt6397_remove,
286 +static struct platform_driver mt6323_driver = {
287 + .probe = mt6323_probe,
288 + .remove = mt6323_remove,
289 .driver = {
290 - .name = "mt6397",
291 - .of_match_table = of_match_ptr(mt6397_of_match),
292 + .name = "mt6323",
293 + .of_match_table = of_match_ptr(mt6323_of_match),
294 },
295 };
296
297 -module_platform_driver(mt6397_driver);
298 +module_platform_driver(mt6323_driver);
299
300 MODULE_AUTHOR("Flora Fu, MediaTek");
301 -MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
302 +MODULE_DESCRIPTION("Driver for MediaTek MT6323 PMIC");
303 MODULE_LICENSE("GPL");
304 -MODULE_ALIAS("platform:mt6397");
305 +MODULE_ALIAS("platform:mt6323");
306 --- a/drivers/regulator/mt6323-regulator.c
307 +++ b/drivers/regulator/mt6323-regulator.c
308 @@ -16,15 +16,15 @@
309 #include <linux/of.h>
310 #include <linux/platform_device.h>
311 #include <linux/regmap.h>
312 -#include <linux/mfd/mt6397/core.h>
313 -#include <linux/mfd/mt6397/registers.h>
314 +#include <linux/mfd/mt6323/core.h>
315 +#include <linux/mfd/mt6323/registers.h>
316 #include <linux/regulator/driver.h>
317 #include <linux/regulator/machine.h>
318 -#include <linux/regulator/mt6397-regulator.h>
319 +#include <linux/regulator/mt6323-regulator.h>
320 #include <linux/regulator/of_regulator.h>
321
322 /*
323 - * MT6397 regulators' information
324 + * MT6323 regulators' information
325 *
326 * @desc: standard fields of regulator description.
327 * @qi: Mask for query enable signal status of regulators
328 @@ -32,7 +32,7 @@
329 * @vselctrl_reg: Register for controlling the buck control mode.
330 * @vselctrl_mask: Mask for query buck's voltage control mode.
331 */
332 -struct mt6397_regulator_info {
333 +struct mt6323_regulator_info {
334 struct regulator_desc desc;
335 u32 qi;
336 u32 vselon_reg;
337 @@ -40,15 +40,15 @@ struct mt6397_regulator_info {
338 u32 vselctrl_mask;
339 };
340
341 -#define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
342 +#define MT6323_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
343 vosel, vosel_mask, voselon, vosel_ctrl) \
344 -[MT6397_ID_##vreg] = { \
345 +[MT6323_ID_##vreg] = { \
346 .desc = { \
347 .name = #vreg, \
348 .of_match = of_match_ptr(match), \
349 - .ops = &mt6397_volt_range_ops, \
350 + .ops = &mt6323_volt_range_ops, \
351 .type = REGULATOR_VOLTAGE, \
352 - .id = MT6397_ID_##vreg, \
353 + .id = MT6323_ID_##vreg, \
354 .owner = THIS_MODULE, \
355 .n_voltages = (max - min)/step + 1, \
356 .linear_ranges = volt_ranges, \
357 @@ -64,15 +64,15 @@ struct mt6397_regulator_info {
358 .vselctrl_mask = BIT(1), \
359 }
360
361 -#define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \
362 +#define MT6323_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \
363 vosel_mask) \
364 -[MT6397_ID_##vreg] = { \
365 +[MT6323_ID_##vreg] = { \
366 .desc = { \
367 .name = #vreg, \
368 .of_match = of_match_ptr(match), \
369 - .ops = &mt6397_volt_table_ops, \
370 + .ops = &mt6323_volt_table_ops, \
371 .type = REGULATOR_VOLTAGE, \
372 - .id = MT6397_ID_##vreg, \
373 + .id = MT6323_ID_##vreg, \
374 .owner = THIS_MODULE, \
375 .n_voltages = ARRAY_SIZE(ldo_volt_table), \
376 .volt_table = ldo_volt_table, \
377 @@ -84,14 +84,14 @@ struct mt6397_regulator_info {
378 .qi = BIT(15), \
379 }
380
381 -#define MT6397_REG_FIXED(match, vreg, enreg, enbit, volt) \
382 -[MT6397_ID_##vreg] = { \
383 +#define MT6323_REG_FIXED(match, vreg, enreg, enbit, volt) \
384 +[MT6323_ID_##vreg] = { \
385 .desc = { \
386 .name = #vreg, \
387 .of_match = of_match_ptr(match), \
388 - .ops = &mt6397_volt_fixed_ops, \
389 + .ops = &mt6323_volt_fixed_ops, \
390 .type = REGULATOR_VOLTAGE, \
391 - .id = MT6397_ID_##vreg, \
392 + .id = MT6323_ID_##vreg, \
393 .owner = THIS_MODULE, \
394 .n_voltages = 1, \
395 .enable_reg = enreg, \
396 @@ -106,50 +106,34 @@ static const struct regulator_linear_ran
397 };
398
399 static const struct regulator_linear_range buck_volt_range2[] = {
400 - REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250),
401 + REGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500),
402 };
403
404 static const struct regulator_linear_range buck_volt_range3[] = {
405 - REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000),
406 + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
407 };
408
409 static const u32 ldo_volt_table1[] = {
410 - 1500000, 1800000, 2500000, 2800000,
411 + 1800000, 3300000,
412 };
413
414 static const u32 ldo_volt_table2[] = {
415 - 1800000, 3300000,
416 + 3000000, 3300000,
417 };
418
419 static const u32 ldo_volt_table3[] = {
420 - 3000000, 3300000,
421 + 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000,
422 };
423
424 static const u32 ldo_volt_table4[] = {
425 - 1220000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
426 -};
427 -
428 -static const u32 ldo_volt_table5[] = {
429 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
430 };
431
432 -static const u32 ldo_volt_table5_v2[] = {
433 - 1200000, 1000000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
434 -};
435 -
436 -static const u32 ldo_volt_table6[] = {
437 - 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000,
438 -};
439 -
440 -static const u32 ldo_volt_table7[] = {
441 - 1300000, 1500000, 1800000, 2000000, 2500000, 2800000, 3000000, 3300000,
442 -};
443 -
444 -static int mt6397_get_status(struct regulator_dev *rdev)
445 +static int mt6323_get_status(struct regulator_dev *rdev)
446 {
447 int ret;
448 u32 regval;
449 - struct mt6397_regulator_info *info = rdev_get_drvdata(rdev);
450 + struct mt6323_regulator_info *info = rdev_get_drvdata(rdev);
451
452 ret = regmap_read(rdev->regmap, info->desc.enable_reg, &regval);
453 if (ret != 0) {
454 @@ -160,7 +144,7 @@ static int mt6397_get_status(struct regu
455 return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
456 }
457
458 -static struct regulator_ops mt6397_volt_range_ops = {
459 +static struct regulator_ops mt6323_volt_range_ops = {
460 .list_voltage = regulator_list_voltage_linear_range,
461 .map_voltage = regulator_map_voltage_linear_range,
462 .set_voltage_sel = regulator_set_voltage_sel_regmap,
463 @@ -169,10 +153,10 @@ static struct regulator_ops mt6397_volt_
464 .enable = regulator_enable_regmap,
465 .disable = regulator_disable_regmap,
466 .is_enabled = regulator_is_enabled_regmap,
467 - .get_status = mt6397_get_status,
468 + .get_status = mt6323_get_status,
469 };
470
471 -static struct regulator_ops mt6397_volt_table_ops = {
472 +static struct regulator_ops mt6323_volt_table_ops = {
473 .list_voltage = regulator_list_voltage_table,
474 .map_voltage = regulator_map_voltage_iterate,
475 .set_voltage_sel = regulator_set_voltage_sel_regmap,
476 @@ -181,90 +165,68 @@ static struct regulator_ops mt6397_volt_
477 .enable = regulator_enable_regmap,
478 .disable = regulator_disable_regmap,
479 .is_enabled = regulator_is_enabled_regmap,
480 - .get_status = mt6397_get_status,
481 + .get_status = mt6323_get_status,
482 };
483
484 -static struct regulator_ops mt6397_volt_fixed_ops = {
485 +static struct regulator_ops mt6323_volt_fixed_ops = {
486 .list_voltage = regulator_list_voltage_linear,
487 .enable = regulator_enable_regmap,
488 .disable = regulator_disable_regmap,
489 .is_enabled = regulator_is_enabled_regmap,
490 - .get_status = mt6397_get_status,
491 + .get_status = mt6323_get_status,
492 };
493
494 -/* The array is indexed by id(MT6397_ID_XXX) */
495 -static struct mt6397_regulator_info mt6397_regulators[] = {
496 - MT6397_BUCK("buck_vpca15", VPCA15, 700000, 1493750, 6250,
497 - buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f,
498 - MT6397_VCA15_CON10, MT6397_VCA15_CON5),
499 - MT6397_BUCK("buck_vpca7", VPCA7, 700000, 1493750, 6250,
500 - buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f,
501 - MT6397_VPCA7_CON10, MT6397_VPCA7_CON5),
502 - MT6397_BUCK("buck_vsramca15", VSRAMCA15, 700000, 1493750, 6250,
503 - buck_volt_range1, MT6397_VSRMCA15_CON7, MT6397_VSRMCA15_CON9,
504 - 0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5),
505 - MT6397_BUCK("buck_vsramca7", VSRAMCA7, 700000, 1493750, 6250,
506 - buck_volt_range1, MT6397_VSRMCA7_CON7, MT6397_VSRMCA7_CON9,
507 - 0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5),
508 - MT6397_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250,
509 - buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f,
510 - MT6397_VCORE_CON10, MT6397_VCORE_CON5),
511 - MT6397_BUCK("buck_vgpu", VGPU, 700000, 1493750, 6250, buck_volt_range1,
512 - MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f,
513 - MT6397_VGPU_CON10, MT6397_VGPU_CON5),
514 - MT6397_BUCK("buck_vdrm", VDRM, 800000, 1593750, 6250, buck_volt_range2,
515 - MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f,
516 - MT6397_VDRM_CON10, MT6397_VDRM_CON5),
517 - MT6397_BUCK("buck_vio18", VIO18, 1500000, 2120000, 20000,
518 - buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f,
519 - MT6397_VIO18_CON10, MT6397_VIO18_CON5),
520 - MT6397_REG_FIXED("ldo_vtcxo", VTCXO, MT6397_ANALDO_CON0, 10, 2800000),
521 - MT6397_REG_FIXED("ldo_va28", VA28, MT6397_ANALDO_CON1, 14, 2800000),
522 - MT6397_LDO("ldo_vcama", VCAMA, ldo_volt_table1,
523 - MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0),
524 - MT6397_REG_FIXED("ldo_vio28", VIO28, MT6397_DIGLDO_CON0, 14, 2800000),
525 - MT6397_REG_FIXED("ldo_vusb", VUSB, MT6397_DIGLDO_CON1, 14, 3300000),
526 - MT6397_LDO("ldo_vmc", VMC, ldo_volt_table2,
527 - MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10),
528 - MT6397_LDO("ldo_vmch", VMCH, ldo_volt_table3,
529 - MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80),
530 - MT6397_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table3,
531 - MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10),
532 - MT6397_LDO("ldo_vgp1", VGP1, ldo_volt_table4,
533 - MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0),
534 - MT6397_LDO("ldo_vgp2", VGP2, ldo_volt_table5,
535 - MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0),
536 - MT6397_LDO("ldo_vgp3", VGP3, ldo_volt_table5,
537 - MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0),
538 - MT6397_LDO("ldo_vgp4", VGP4, ldo_volt_table5,
539 - MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0),
540 - MT6397_LDO("ldo_vgp5", VGP5, ldo_volt_table6,
541 - MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0),
542 - MT6397_LDO("ldo_vgp6", VGP6, ldo_volt_table5,
543 - MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0),
544 - MT6397_LDO("ldo_vibr", VIBR, ldo_volt_table7,
545 - MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00),
546 +/* The array is indexed by id(MT6323_ID_XXX) */
547 +static struct mt6323_regulator_info mt6323_regulators[] = {
548 + /* buck */
549 + MT6323_BUCK("buck_vproc", VPROC, 700000, 1493750, 6250,
550 + buck_volt_range1, MT6323_VPROC_CON7, MT6323_VPROC_CON9, 0x7f,
551 + MT6323_VPROC_CON10, MT6323_VPROC_CON5),
552 + MT6323_BUCK("buck_vsys", VSYS, 1400000, 3000000, 12500,
553 + buck_volt_range2, MT6323_VSYS_CON7, MT6323_VSYS_CON9,
554 + 0x7f, MT6323_VSYS_CON10, MT6323_VSYS_CON5),
555 + MT6323_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
556 + buck_volt_range3, MT6323_VPA_CON7, MT6323_VPA_CON9, 0x7f,
557 + MT6323_VPA_CON10, MT6323_VPA_CON5),
558 +
559 + /* analog */
560 + MT6323_REG_FIXED("ldo_vtcxo", VTCXO, MT6323_ANALDO_CON1, 10, 2800000),
561 + MT6323_REG_FIXED("ldo_va", VA, MT6323_ANALDO_CON2, 14, 2800000),
562 + MT6323_REG_FIXED("ldo_vcn28", VCN28, MT6323_ANALDO_CON19, 12, 2800000),
563 + MT6323_REG_FIXED("ldo_vcn33", VCN33, MT6323_ANALDO_CON21, 12, 3300000),
564 +
565 + /* digital */
566 + MT6323_REG_FIXED("ldo_vio28", VIO28, MT6323_DIGLDO_CON0, 15, 2800000),
567 + MT6323_REG_FIXED("ldo_vusb", VUSB, MT6323_DIGLDO_CON2, 15, 3300000),
568 + MT6323_LDO("ldo_vmc", VMC, ldo_volt_table1,
569 + MT6323_DIGLDO_CON3, 12, MT6323_DIGLDO_CON24, 0x10),
570 + MT6323_LDO("ldo_vmch", VMCH, ldo_volt_table2,
571 + MT6323_DIGLDO_CON5, 14, MT6323_DIGLDO_CON26, 0x80),
572 + MT6323_LDO("ldo_vgp1", VGP1, ldo_volt_table3,
573 + MT6323_DIGLDO_CON7, 15, MT6323_DIGLDO_CON28, 0xE0),
574 + MT6323_LDO("ldo_vgp2", VGP2, ldo_volt_table4,
575 + MT6323_DIGLDO_CON8, 15, MT6323_DIGLDO_CON29, 0xE0),
576 };
577
578 -static int mt6397_set_buck_vosel_reg(struct platform_device *pdev)
579 +static int mt6323_set_buck_vosel_reg(struct platform_device *pdev)
580 {
581 - struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
582 + struct mt6323_chip *mt6323 = dev_get_drvdata(pdev->dev.parent);
583 int i;
584 u32 regval;
585
586 - for (i = 0; i < MT6397_MAX_REGULATOR; i++) {
587 - if (mt6397_regulators[i].vselctrl_reg) {
588 - if (regmap_read(mt6397->regmap,
589 - mt6397_regulators[i].vselctrl_reg,
590 + for (i = 0; i < MT6323_MAX_REGULATOR; i++) {
591 + if (mt6323_regulators[i].vselctrl_reg) {
592 + if (regmap_read(mt6323->regmap,
593 + mt6323_regulators[i].vselctrl_reg,
594 &regval) < 0) {
595 dev_err(&pdev->dev,
596 "Failed to read buck ctrl\n");
597 return -EIO;
598 }
599
600 - if (regval & mt6397_regulators[i].vselctrl_mask) {
601 - mt6397_regulators[i].desc.vsel_reg =
602 - mt6397_regulators[i].vselon_reg;
603 + if (regval & mt6323_regulators[i].vselctrl_mask) {
604 + mt6323_regulators[i].desc.vsel_reg =
605 + mt6323_regulators[i].vselon_reg;
606 }
607 }
608 }
609 @@ -272,44 +234,34 @@ static int mt6397_set_buck_vosel_reg(str
610 return 0;
611 }
612
613 -static int mt6397_regulator_probe(struct platform_device *pdev)
614 +static int mt6323_regulator_probe(struct platform_device *pdev)
615 {
616 - struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
617 + struct mt6323_chip *mt6323 = dev_get_drvdata(pdev->dev.parent);
618 struct regulator_config config = {};
619 struct regulator_dev *rdev;
620 int i;
621 - u32 reg_value, version;
622 + u32 reg_value;
623
624 /* Query buck controller to select activated voltage register part */
625 - if (mt6397_set_buck_vosel_reg(pdev))
626 + if (mt6323_set_buck_vosel_reg(pdev))
627 return -EIO;
628
629 /* Read PMIC chip revision to update constraints and voltage table */
630 - if (regmap_read(mt6397->regmap, MT6397_CID, &reg_value) < 0) {
631 + if (regmap_read(mt6323->regmap, MT6323_CID, &reg_value) < 0) {
632 dev_err(&pdev->dev, "Failed to read Chip ID\n");
633 return -EIO;
634 }
635 dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);
636
637 - version = (reg_value & 0xFF);
638 - switch (version) {
639 - case MT6397_REGULATOR_ID91:
640 - mt6397_regulators[MT6397_ID_VGP2].desc.volt_table =
641 - ldo_volt_table5_v2;
642 - break;
643 - default:
644 - break;
645 - }
646 -
647 - for (i = 0; i < MT6397_MAX_REGULATOR; i++) {
648 + for (i = 0; i < MT6323_MAX_REGULATOR; i++) {
649 config.dev = &pdev->dev;
650 - config.driver_data = &mt6397_regulators[i];
651 - config.regmap = mt6397->regmap;
652 + config.driver_data = &mt6323_regulators[i];
653 + config.regmap = mt6323->regmap;
654 rdev = devm_regulator_register(&pdev->dev,
655 - &mt6397_regulators[i].desc, &config);
656 + &mt6323_regulators[i].desc, &config);
657 if (IS_ERR(rdev)) {
658 dev_err(&pdev->dev, "failed to register %s\n",
659 - mt6397_regulators[i].desc.name);
660 + mt6323_regulators[i].desc.name);
661 return PTR_ERR(rdev);
662 }
663 }
664 @@ -317,16 +269,16 @@ static int mt6397_regulator_probe(struct
665 return 0;
666 }
667
668 -static struct platform_driver mt6397_regulator_driver = {
669 +static struct platform_driver mt6323_regulator_driver = {
670 .driver = {
671 - .name = "mt6397-regulator",
672 + .name = "mt6323-regulator",
673 },
674 - .probe = mt6397_regulator_probe,
675 + .probe = mt6323_regulator_probe,
676 };
677
678 -module_platform_driver(mt6397_regulator_driver);
679 +module_platform_driver(mt6323_regulator_driver);
680
681 MODULE_AUTHOR("Flora Fu <flora.fu@mediatek.com>");
682 -MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC");
683 +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6323 PMIC");
684 MODULE_LICENSE("GPL");
685 -MODULE_ALIAS("platform:mt6397-regulator");
686 +MODULE_ALIAS("platform:mt6323-regulator");
687 --- a/include/linux/mfd/mt6323/core.h
688 +++ b/include/linux/mfd/mt6323/core.h
689 @@ -12,46 +12,46 @@
690 * GNU General Public License for more details.
691 */
692
693 -#ifndef __MFD_MT6397_CORE_H__
694 -#define __MFD_MT6397_CORE_H__
695 +#ifndef __MFD_MT6323_CORE_H__
696 +#define __MFD_MT6323_CORE_H__
697
698 -enum mt6397_irq_numbers {
699 - MT6397_IRQ_SPKL_AB = 0,
700 - MT6397_IRQ_SPKR_AB,
701 - MT6397_IRQ_SPKL,
702 - MT6397_IRQ_SPKR,
703 - MT6397_IRQ_BAT_L,
704 - MT6397_IRQ_BAT_H,
705 - MT6397_IRQ_FG_BAT_L,
706 - MT6397_IRQ_FG_BAT_H,
707 - MT6397_IRQ_WATCHDOG,
708 - MT6397_IRQ_PWRKEY,
709 - MT6397_IRQ_THR_L,
710 - MT6397_IRQ_THR_H,
711 - MT6397_IRQ_VBATON_UNDET,
712 - MT6397_IRQ_BVALID_DET,
713 - MT6397_IRQ_CHRDET,
714 - MT6397_IRQ_OV,
715 - MT6397_IRQ_LDO,
716 - MT6397_IRQ_HOMEKEY,
717 - MT6397_IRQ_ACCDET,
718 - MT6397_IRQ_AUDIO,
719 - MT6397_IRQ_RTC,
720 - MT6397_IRQ_PWRKEY_RSTB,
721 - MT6397_IRQ_HDMI_SIFM,
722 - MT6397_IRQ_HDMI_CEC,
723 - MT6397_IRQ_VCA15,
724 - MT6397_IRQ_VSRMCA15,
725 - MT6397_IRQ_VCORE,
726 - MT6397_IRQ_VGPU,
727 - MT6397_IRQ_VIO18,
728 - MT6397_IRQ_VPCA7,
729 - MT6397_IRQ_VSRMCA7,
730 - MT6397_IRQ_VDRM,
731 - MT6397_IRQ_NR,
732 +enum mt6323_irq_numbers {
733 + MT6323_IRQ_SPKL_AB = 0,
734 + MT6323_IRQ_SPKR_AB,
735 + MT6323_IRQ_SPKL,
736 + MT6323_IRQ_SPKR,
737 + MT6323_IRQ_BAT_L,
738 + MT6323_IRQ_BAT_H,
739 + MT6323_IRQ_FG_BAT_L,
740 + MT6323_IRQ_FG_BAT_H,
741 + MT6323_IRQ_WATCHDOG,
742 + MT6323_IRQ_PWRKEY,
743 + MT6323_IRQ_THR_L,
744 + MT6323_IRQ_THR_H,
745 + MT6323_IRQ_VBATON_UNDET,
746 + MT6323_IRQ_BVALID_DET,
747 + MT6323_IRQ_CHRDET,
748 + MT6323_IRQ_OV,
749 + MT6323_IRQ_LDO,
750 + MT6323_IRQ_HOMEKEY,
751 + MT6323_IRQ_ACCDET,
752 + MT6323_IRQ_AUDIO,
753 + MT6323_IRQ_RTC,
754 + MT6323_IRQ_PWRKEY_RSTB,
755 + MT6323_IRQ_HDMI_SIFM,
756 + MT6323_IRQ_HDMI_CEC,
757 + MT6323_IRQ_VCA15,
758 + MT6323_IRQ_VSRMCA15,
759 + MT6323_IRQ_VCORE,
760 + MT6323_IRQ_VGPU,
761 + MT6323_IRQ_VIO18,
762 + MT6323_IRQ_VPCA7,
763 + MT6323_IRQ_VSRMCA7,
764 + MT6323_IRQ_VDRM,
765 + MT6323_IRQ_NR,
766 };
767
768 -struct mt6397_chip {
769 +struct mt6323_chip {
770 struct device *dev;
771 struct regmap *regmap;
772 int irq;
773 @@ -61,4 +61,4 @@ struct mt6397_chip {
774 u16 irq_masks_cache[2];
775 };
776
777 -#endif /* __MFD_MT6397_CORE_H__ */
778 +#endif /* __MFD_MT6323_CORE_H__ */
779 --- a/include/linux/mfd/mt6323/registers.h
780 +++ b/include/linux/mfd/mt6323/registers.h
781 @@ -1,6 +1,5 @@
782 /*
783 - * Copyright (c) 2014 MediaTek Inc.
784 - * Author: Flora Fu, MediaTek
785 + * Copyright (c) 2015 - John Crispin <blogic@openwrt.org>
786 *
787 * This program is free software; you can redistribute it and/or modify
788 * it under the terms of the GNU General Public License version 2 as
789 @@ -12,351 +11,403 @@
790 * GNU General Public License for more details.
791 */
792
793 -#ifndef __MFD_MT6397_REGISTERS_H__
794 -#define __MFD_MT6397_REGISTERS_H__
795 +#ifndef __MFD_MT6323_REGISTERS_H__
796 +#define __MFD_MT6323_REGISTERS_H__
797
798 /* PMIC Registers */
799 -#define MT6397_CID 0x0100
800 -#define MT6397_TOP_CKPDN 0x0102
801 -#define MT6397_TOP_CKPDN_SET 0x0104
802 -#define MT6397_TOP_CKPDN_CLR 0x0106
803 -#define MT6397_TOP_CKPDN2 0x0108
804 -#define MT6397_TOP_CKPDN2_SET 0x010A
805 -#define MT6397_TOP_CKPDN2_CLR 0x010C
806 -#define MT6397_TOP_GPIO_CKPDN 0x010E
807 -#define MT6397_TOP_RST_CON 0x0114
808 -#define MT6397_WRP_CKPDN 0x011A
809 -#define MT6397_WRP_RST_CON 0x0120
810 -#define MT6397_TOP_RST_MISC 0x0126
811 -#define MT6397_TOP_CKCON1 0x0128
812 -#define MT6397_TOP_CKCON2 0x012A
813 -#define MT6397_TOP_CKTST1 0x012C
814 -#define MT6397_TOP_CKTST2 0x012E
815 -#define MT6397_OC_DEG_EN 0x0130
816 -#define MT6397_OC_CTL0 0x0132
817 -#define MT6397_OC_CTL1 0x0134
818 -#define MT6397_OC_CTL2 0x0136
819 -#define MT6397_INT_RSV 0x0138
820 -#define MT6397_TEST_CON0 0x013A
821 -#define MT6397_TEST_CON1 0x013C
822 -#define MT6397_STATUS0 0x013E
823 -#define MT6397_STATUS1 0x0140
824 -#define MT6397_PGSTATUS 0x0142
825 -#define MT6397_CHRSTATUS 0x0144
826 -#define MT6397_OCSTATUS0 0x0146
827 -#define MT6397_OCSTATUS1 0x0148
828 -#define MT6397_OCSTATUS2 0x014A
829 -#define MT6397_HDMI_PAD_IE 0x014C
830 -#define MT6397_TEST_OUT_L 0x014E
831 -#define MT6397_TEST_OUT_H 0x0150
832 -#define MT6397_TDSEL_CON 0x0152
833 -#define MT6397_RDSEL_CON 0x0154
834 -#define MT6397_GPIO_SMT_CON0 0x0156
835 -#define MT6397_GPIO_SMT_CON1 0x0158
836 -#define MT6397_GPIO_SMT_CON2 0x015A
837 -#define MT6397_GPIO_SMT_CON3 0x015C
838 -#define MT6397_DRV_CON0 0x015E
839 -#define MT6397_DRV_CON1 0x0160
840 -#define MT6397_DRV_CON2 0x0162
841 -#define MT6397_DRV_CON3 0x0164
842 -#define MT6397_DRV_CON4 0x0166
843 -#define MT6397_DRV_CON5 0x0168
844 -#define MT6397_DRV_CON6 0x016A
845 -#define MT6397_DRV_CON7 0x016C
846 -#define MT6397_DRV_CON8 0x016E
847 -#define MT6397_DRV_CON9 0x0170
848 -#define MT6397_DRV_CON10 0x0172
849 -#define MT6397_DRV_CON11 0x0174
850 -#define MT6397_DRV_CON12 0x0176
851 -#define MT6397_INT_CON0 0x0178
852 -#define MT6397_INT_CON1 0x017E
853 -#define MT6397_INT_STATUS0 0x0184
854 -#define MT6397_INT_STATUS1 0x0186
855 -#define MT6397_FQMTR_CON0 0x0188
856 -#define MT6397_FQMTR_CON1 0x018A
857 -#define MT6397_FQMTR_CON2 0x018C
858 -#define MT6397_EFUSE_DOUT_0_15 0x01C4
859 -#define MT6397_EFUSE_DOUT_16_31 0x01C6
860 -#define MT6397_EFUSE_DOUT_32_47 0x01C8
861 -#define MT6397_EFUSE_DOUT_48_63 0x01CA
862 -#define MT6397_SPI_CON 0x01CC
863 -#define MT6397_TOP_CKPDN3 0x01CE
864 -#define MT6397_TOP_CKCON3 0x01D4
865 -#define MT6397_EFUSE_DOUT_64_79 0x01D6
866 -#define MT6397_EFUSE_DOUT_80_95 0x01D8
867 -#define MT6397_EFUSE_DOUT_96_111 0x01DA
868 -#define MT6397_EFUSE_DOUT_112_127 0x01DC
869 -#define MT6397_EFUSE_DOUT_128_143 0x01DE
870 -#define MT6397_EFUSE_DOUT_144_159 0x01E0
871 -#define MT6397_EFUSE_DOUT_160_175 0x01E2
872 -#define MT6397_EFUSE_DOUT_176_191 0x01E4
873 -#define MT6397_EFUSE_DOUT_192_207 0x01E6
874 -#define MT6397_EFUSE_DOUT_208_223 0x01E8
875 -#define MT6397_EFUSE_DOUT_224_239 0x01EA
876 -#define MT6397_EFUSE_DOUT_240_255 0x01EC
877 -#define MT6397_EFUSE_DOUT_256_271 0x01EE
878 -#define MT6397_EFUSE_DOUT_272_287 0x01F0
879 -#define MT6397_EFUSE_DOUT_288_300 0x01F2
880 -#define MT6397_EFUSE_DOUT_304_319 0x01F4
881 -#define MT6397_BUCK_CON0 0x0200
882 -#define MT6397_BUCK_CON1 0x0202
883 -#define MT6397_BUCK_CON2 0x0204
884 -#define MT6397_BUCK_CON3 0x0206
885 -#define MT6397_BUCK_CON4 0x0208
886 -#define MT6397_BUCK_CON5 0x020A
887 -#define MT6397_BUCK_CON6 0x020C
888 -#define MT6397_BUCK_CON7 0x020E
889 -#define MT6397_BUCK_CON8 0x0210
890 -#define MT6397_BUCK_CON9 0x0212
891 -#define MT6397_VCA15_CON0 0x0214
892 -#define MT6397_VCA15_CON1 0x0216
893 -#define MT6397_VCA15_CON2 0x0218
894 -#define MT6397_VCA15_CON3 0x021A
895 -#define MT6397_VCA15_CON4 0x021C
896 -#define MT6397_VCA15_CON5 0x021E
897 -#define MT6397_VCA15_CON6 0x0220
898 -#define MT6397_VCA15_CON7 0x0222
899 -#define MT6397_VCA15_CON8 0x0224
900 -#define MT6397_VCA15_CON9 0x0226
901 -#define MT6397_VCA15_CON10 0x0228
902 -#define MT6397_VCA15_CON11 0x022A
903 -#define MT6397_VCA15_CON12 0x022C
904 -#define MT6397_VCA15_CON13 0x022E
905 -#define MT6397_VCA15_CON14 0x0230
906 -#define MT6397_VCA15_CON15 0x0232
907 -#define MT6397_VCA15_CON16 0x0234
908 -#define MT6397_VCA15_CON17 0x0236
909 -#define MT6397_VCA15_CON18 0x0238
910 -#define MT6397_VSRMCA15_CON0 0x023A
911 -#define MT6397_VSRMCA15_CON1 0x023C
912 -#define MT6397_VSRMCA15_CON2 0x023E
913 -#define MT6397_VSRMCA15_CON3 0x0240
914 -#define MT6397_VSRMCA15_CON4 0x0242
915 -#define MT6397_VSRMCA15_CON5 0x0244
916 -#define MT6397_VSRMCA15_CON6 0x0246
917 -#define MT6397_VSRMCA15_CON7 0x0248
918 -#define MT6397_VSRMCA15_CON8 0x024A
919 -#define MT6397_VSRMCA15_CON9 0x024C
920 -#define MT6397_VSRMCA15_CON10 0x024E
921 -#define MT6397_VSRMCA15_CON11 0x0250
922 -#define MT6397_VSRMCA15_CON12 0x0252
923 -#define MT6397_VSRMCA15_CON13 0x0254
924 -#define MT6397_VSRMCA15_CON14 0x0256
925 -#define MT6397_VSRMCA15_CON15 0x0258
926 -#define MT6397_VSRMCA15_CON16 0x025A
927 -#define MT6397_VSRMCA15_CON17 0x025C
928 -#define MT6397_VSRMCA15_CON18 0x025E
929 -#define MT6397_VSRMCA15_CON19 0x0260
930 -#define MT6397_VSRMCA15_CON20 0x0262
931 -#define MT6397_VSRMCA15_CON21 0x0264
932 -#define MT6397_VCORE_CON0 0x0266
933 -#define MT6397_VCORE_CON1 0x0268
934 -#define MT6397_VCORE_CON2 0x026A
935 -#define MT6397_VCORE_CON3 0x026C
936 -#define MT6397_VCORE_CON4 0x026E
937 -#define MT6397_VCORE_CON5 0x0270
938 -#define MT6397_VCORE_CON6 0x0272
939 -#define MT6397_VCORE_CON7 0x0274
940 -#define MT6397_VCORE_CON8 0x0276
941 -#define MT6397_VCORE_CON9 0x0278
942 -#define MT6397_VCORE_CON10 0x027A
943 -#define MT6397_VCORE_CON11 0x027C
944 -#define MT6397_VCORE_CON12 0x027E
945 -#define MT6397_VCORE_CON13 0x0280
946 -#define MT6397_VCORE_CON14 0x0282
947 -#define MT6397_VCORE_CON15 0x0284
948 -#define MT6397_VCORE_CON16 0x0286
949 -#define MT6397_VCORE_CON17 0x0288
950 -#define MT6397_VCORE_CON18 0x028A
951 -#define MT6397_VGPU_CON0 0x028C
952 -#define MT6397_VGPU_CON1 0x028E
953 -#define MT6397_VGPU_CON2 0x0290
954 -#define MT6397_VGPU_CON3 0x0292
955 -#define MT6397_VGPU_CON4 0x0294
956 -#define MT6397_VGPU_CON5 0x0296
957 -#define MT6397_VGPU_CON6 0x0298
958 -#define MT6397_VGPU_CON7 0x029A
959 -#define MT6397_VGPU_CON8 0x029C
960 -#define MT6397_VGPU_CON9 0x029E
961 -#define MT6397_VGPU_CON10 0x02A0
962 -#define MT6397_VGPU_CON11 0x02A2
963 -#define MT6397_VGPU_CON12 0x02A4
964 -#define MT6397_VGPU_CON13 0x02A6
965 -#define MT6397_VGPU_CON14 0x02A8
966 -#define MT6397_VGPU_CON15 0x02AA
967 -#define MT6397_VGPU_CON16 0x02AC
968 -#define MT6397_VGPU_CON17 0x02AE
969 -#define MT6397_VGPU_CON18 0x02B0
970 -#define MT6397_VIO18_CON0 0x0300
971 -#define MT6397_VIO18_CON1 0x0302
972 -#define MT6397_VIO18_CON2 0x0304
973 -#define MT6397_VIO18_CON3 0x0306
974 -#define MT6397_VIO18_CON4 0x0308
975 -#define MT6397_VIO18_CON5 0x030A
976 -#define MT6397_VIO18_CON6 0x030C
977 -#define MT6397_VIO18_CON7 0x030E
978 -#define MT6397_VIO18_CON8 0x0310
979 -#define MT6397_VIO18_CON9 0x0312
980 -#define MT6397_VIO18_CON10 0x0314
981 -#define MT6397_VIO18_CON11 0x0316
982 -#define MT6397_VIO18_CON12 0x0318
983 -#define MT6397_VIO18_CON13 0x031A
984 -#define MT6397_VIO18_CON14 0x031C
985 -#define MT6397_VIO18_CON15 0x031E
986 -#define MT6397_VIO18_CON16 0x0320
987 -#define MT6397_VIO18_CON17 0x0322
988 -#define MT6397_VIO18_CON18 0x0324
989 -#define MT6397_VPCA7_CON0 0x0326
990 -#define MT6397_VPCA7_CON1 0x0328
991 -#define MT6397_VPCA7_CON2 0x032A
992 -#define MT6397_VPCA7_CON3 0x032C
993 -#define MT6397_VPCA7_CON4 0x032E
994 -#define MT6397_VPCA7_CON5 0x0330
995 -#define MT6397_VPCA7_CON6 0x0332
996 -#define MT6397_VPCA7_CON7 0x0334
997 -#define MT6397_VPCA7_CON8 0x0336
998 -#define MT6397_VPCA7_CON9 0x0338
999 -#define MT6397_VPCA7_CON10 0x033A
1000 -#define MT6397_VPCA7_CON11 0x033C
1001 -#define MT6397_VPCA7_CON12 0x033E
1002 -#define MT6397_VPCA7_CON13 0x0340
1003 -#define MT6397_VPCA7_CON14 0x0342
1004 -#define MT6397_VPCA7_CON15 0x0344
1005 -#define MT6397_VPCA7_CON16 0x0346
1006 -#define MT6397_VPCA7_CON17 0x0348
1007 -#define MT6397_VPCA7_CON18 0x034A
1008 -#define MT6397_VSRMCA7_CON0 0x034C
1009 -#define MT6397_VSRMCA7_CON1 0x034E
1010 -#define MT6397_VSRMCA7_CON2 0x0350
1011 -#define MT6397_VSRMCA7_CON3 0x0352
1012 -#define MT6397_VSRMCA7_CON4 0x0354
1013 -#define MT6397_VSRMCA7_CON5 0x0356
1014 -#define MT6397_VSRMCA7_CON6 0x0358
1015 -#define MT6397_VSRMCA7_CON7 0x035A
1016 -#define MT6397_VSRMCA7_CON8 0x035C
1017 -#define MT6397_VSRMCA7_CON9 0x035E
1018 -#define MT6397_VSRMCA7_CON10 0x0360
1019 -#define MT6397_VSRMCA7_CON11 0x0362
1020 -#define MT6397_VSRMCA7_CON12 0x0364
1021 -#define MT6397_VSRMCA7_CON13 0x0366
1022 -#define MT6397_VSRMCA7_CON14 0x0368
1023 -#define MT6397_VSRMCA7_CON15 0x036A
1024 -#define MT6397_VSRMCA7_CON16 0x036C
1025 -#define MT6397_VSRMCA7_CON17 0x036E
1026 -#define MT6397_VSRMCA7_CON18 0x0370
1027 -#define MT6397_VSRMCA7_CON19 0x0372
1028 -#define MT6397_VSRMCA7_CON20 0x0374
1029 -#define MT6397_VSRMCA7_CON21 0x0376
1030 -#define MT6397_VDRM_CON0 0x0378
1031 -#define MT6397_VDRM_CON1 0x037A
1032 -#define MT6397_VDRM_CON2 0x037C
1033 -#define MT6397_VDRM_CON3 0x037E
1034 -#define MT6397_VDRM_CON4 0x0380
1035 -#define MT6397_VDRM_CON5 0x0382
1036 -#define MT6397_VDRM_CON6 0x0384
1037 -#define MT6397_VDRM_CON7 0x0386
1038 -#define MT6397_VDRM_CON8 0x0388
1039 -#define MT6397_VDRM_CON9 0x038A
1040 -#define MT6397_VDRM_CON10 0x038C
1041 -#define MT6397_VDRM_CON11 0x038E
1042 -#define MT6397_VDRM_CON12 0x0390
1043 -#define MT6397_VDRM_CON13 0x0392
1044 -#define MT6397_VDRM_CON14 0x0394
1045 -#define MT6397_VDRM_CON15 0x0396
1046 -#define MT6397_VDRM_CON16 0x0398
1047 -#define MT6397_VDRM_CON17 0x039A
1048 -#define MT6397_VDRM_CON18 0x039C
1049 -#define MT6397_BUCK_K_CON0 0x039E
1050 -#define MT6397_BUCK_K_CON1 0x03A0
1051 -#define MT6397_ANALDO_CON0 0x0400
1052 -#define MT6397_ANALDO_CON1 0x0402
1053 -#define MT6397_ANALDO_CON2 0x0404
1054 -#define MT6397_ANALDO_CON3 0x0406
1055 -#define MT6397_ANALDO_CON4 0x0408
1056 -#define MT6397_ANALDO_CON5 0x040A
1057 -#define MT6397_ANALDO_CON6 0x040C
1058 -#define MT6397_ANALDO_CON7 0x040E
1059 -#define MT6397_DIGLDO_CON0 0x0410
1060 -#define MT6397_DIGLDO_CON1 0x0412
1061 -#define MT6397_DIGLDO_CON2 0x0414
1062 -#define MT6397_DIGLDO_CON3 0x0416
1063 -#define MT6397_DIGLDO_CON4 0x0418
1064 -#define MT6397_DIGLDO_CON5 0x041A
1065 -#define MT6397_DIGLDO_CON6 0x041C
1066 -#define MT6397_DIGLDO_CON7 0x041E
1067 -#define MT6397_DIGLDO_CON8 0x0420
1068 -#define MT6397_DIGLDO_CON9 0x0422
1069 -#define MT6397_DIGLDO_CON10 0x0424
1070 -#define MT6397_DIGLDO_CON11 0x0426
1071 -#define MT6397_DIGLDO_CON12 0x0428
1072 -#define MT6397_DIGLDO_CON13 0x042A
1073 -#define MT6397_DIGLDO_CON14 0x042C
1074 -#define MT6397_DIGLDO_CON15 0x042E
1075 -#define MT6397_DIGLDO_CON16 0x0430
1076 -#define MT6397_DIGLDO_CON17 0x0432
1077 -#define MT6397_DIGLDO_CON18 0x0434
1078 -#define MT6397_DIGLDO_CON19 0x0436
1079 -#define MT6397_DIGLDO_CON20 0x0438
1080 -#define MT6397_DIGLDO_CON21 0x043A
1081 -#define MT6397_DIGLDO_CON22 0x043C
1082 -#define MT6397_DIGLDO_CON23 0x043E
1083 -#define MT6397_DIGLDO_CON24 0x0440
1084 -#define MT6397_DIGLDO_CON25 0x0442
1085 -#define MT6397_DIGLDO_CON26 0x0444
1086 -#define MT6397_DIGLDO_CON27 0x0446
1087 -#define MT6397_DIGLDO_CON28 0x0448
1088 -#define MT6397_DIGLDO_CON29 0x044A
1089 -#define MT6397_DIGLDO_CON30 0x044C
1090 -#define MT6397_DIGLDO_CON31 0x044E
1091 -#define MT6397_DIGLDO_CON32 0x0450
1092 -#define MT6397_DIGLDO_CON33 0x045A
1093 -#define MT6397_SPK_CON0 0x0600
1094 -#define MT6397_SPK_CON1 0x0602
1095 -#define MT6397_SPK_CON2 0x0604
1096 -#define MT6397_SPK_CON3 0x0606
1097 -#define MT6397_SPK_CON4 0x0608
1098 -#define MT6397_SPK_CON5 0x060A
1099 -#define MT6397_SPK_CON6 0x060C
1100 -#define MT6397_SPK_CON7 0x060E
1101 -#define MT6397_SPK_CON8 0x0610
1102 -#define MT6397_SPK_CON9 0x0612
1103 -#define MT6397_SPK_CON10 0x0614
1104 -#define MT6397_SPK_CON11 0x0616
1105 -#define MT6397_AUDDAC_CON0 0x0700
1106 -#define MT6397_AUDBUF_CFG0 0x0702
1107 -#define MT6397_AUDBUF_CFG1 0x0704
1108 -#define MT6397_AUDBUF_CFG2 0x0706
1109 -#define MT6397_AUDBUF_CFG3 0x0708
1110 -#define MT6397_AUDBUF_CFG4 0x070A
1111 -#define MT6397_IBIASDIST_CFG0 0x070C
1112 -#define MT6397_AUDACCDEPOP_CFG0 0x070E
1113 -#define MT6397_AUD_IV_CFG0 0x0710
1114 -#define MT6397_AUDCLKGEN_CFG0 0x0712
1115 -#define MT6397_AUDLDO_CFG0 0x0714
1116 -#define MT6397_AUDLDO_CFG1 0x0716
1117 -#define MT6397_AUDNVREGGLB_CFG0 0x0718
1118 -#define MT6397_AUD_NCP0 0x071A
1119 -#define MT6397_AUDPREAMP_CON0 0x071C
1120 -#define MT6397_AUDADC_CON0 0x071E
1121 -#define MT6397_AUDADC_CON1 0x0720
1122 -#define MT6397_AUDADC_CON2 0x0722
1123 -#define MT6397_AUDADC_CON3 0x0724
1124 -#define MT6397_AUDADC_CON4 0x0726
1125 -#define MT6397_AUDADC_CON5 0x0728
1126 -#define MT6397_AUDADC_CON6 0x072A
1127 -#define MT6397_AUDDIGMI_CON0 0x072C
1128 -#define MT6397_AUDLSBUF_CON0 0x072E
1129 -#define MT6397_AUDLSBUF_CON1 0x0730
1130 -#define MT6397_AUDENCSPARE_CON0 0x0732
1131 -#define MT6397_AUDENCCLKSQ_CON0 0x0734
1132 -#define MT6397_AUDPREAMPGAIN_CON0 0x0736
1133 -#define MT6397_ZCD_CON0 0x0738
1134 -#define MT6397_ZCD_CON1 0x073A
1135 -#define MT6397_ZCD_CON2 0x073C
1136 -#define MT6397_ZCD_CON3 0x073E
1137 -#define MT6397_ZCD_CON4 0x0740
1138 -#define MT6397_ZCD_CON5 0x0742
1139 -#define MT6397_NCP_CLKDIV_CON0 0x0744
1140 -#define MT6397_NCP_CLKDIV_CON1 0x0746
1141 +#define MT6323_CHR_CON0 0x0000
1142 +#define MT6323_CHR_CON1 0x0002
1143 +#define MT6323_CHR_CON2 0x0004
1144 +#define MT6323_CHR_CON3 0x0006
1145 +#define MT6323_CHR_CON4 0x0008
1146 +#define MT6323_CHR_CON5 0x000A
1147 +#define MT6323_CHR_CON6 0x000C
1148 +#define MT6323_CHR_CON7 0x000E
1149 +#define MT6323_CHR_CON8 0x0010
1150 +#define MT6323_CHR_CON9 0x0012
1151 +#define MT6323_CHR_CON10 0x0014
1152 +#define MT6323_CHR_CON11 0x0016
1153 +#define MT6323_CHR_CON12 0x0018
1154 +#define MT6323_CHR_CON13 0x001A
1155 +#define MT6323_CHR_CON14 0x001C
1156 +#define MT6323_CHR_CON15 0x001E
1157 +#define MT6323_CHR_CON16 0x0020
1158 +#define MT6323_CHR_CON17 0x0022
1159 +#define MT6323_CHR_CON18 0x0024
1160 +#define MT6323_CHR_CON19 0x0026
1161 +#define MT6323_CHR_CON20 0x0028
1162 +#define MT6323_CHR_CON21 0x002A
1163 +#define MT6323_CHR_CON22 0x002C
1164 +#define MT6323_CHR_CON23 0x002E
1165 +#define MT6323_CHR_CON24 0x0030
1166 +#define MT6323_CHR_CON25 0x0032
1167 +#define MT6323_CHR_CON26 0x0034
1168 +#define MT6323_CHR_CON27 0x0036
1169 +#define MT6323_CHR_CON28 0x0038
1170 +#define MT6323_CHR_CON29 0x003A
1171 +#define MT6323_STRUP_CON0 0x003C
1172 +#define MT6323_STRUP_CON2 0x003E
1173 +#define MT6323_STRUP_CON3 0x0040
1174 +#define MT6323_STRUP_CON4 0x0042
1175 +#define MT6323_STRUP_CON5 0x0044
1176 +#define MT6323_STRUP_CON6 0x0046
1177 +#define MT6323_STRUP_CON7 0x0048
1178 +#define MT6323_STRUP_CON8 0x004A
1179 +#define MT6323_STRUP_CON9 0x004C
1180 +#define MT6323_STRUP_CON10 0x004E
1181 +#define MT6323_STRUP_CON11 0x0050
1182 +#define MT6323_SPK_CON0 0x0052
1183 +#define MT6323_SPK_CON1 0x0054
1184 +#define MT6323_SPK_CON2 0x0056
1185 +#define MT6323_SPK_CON6 0x005E
1186 +#define MT6323_SPK_CON7 0x0060
1187 +#define MT6323_SPK_CON8 0x0062
1188 +#define MT6323_SPK_CON9 0x0064
1189 +#define MT6323_SPK_CON10 0x0066
1190 +#define MT6323_SPK_CON11 0x0068
1191 +#define MT6323_SPK_CON12 0x006A
1192 +#define MT6323_CID 0x0100
1193 +#define MT6323_TOP_CKPDN0 0x0102
1194 +#define MT6323_TOP_CKPDN0_SET 0x0104
1195 +#define MT6323_TOP_CKPDN0_CLR 0x0106
1196 +#define MT6323_TOP_CKPDN1 0x0108
1197 +#define MT6323_TOP_CKPDN1_SET 0x010A
1198 +#define MT6323_TOP_CKPDN1_CLR 0x010C
1199 +#define MT6323_TOP_CKPDN2 0x010E
1200 +#define MT6323_TOP_CKPDN2_SET 0x0110
1201 +#define MT6323_TOP_CKPDN2_CLR 0x0112
1202 +#define MT6323_TOP_RST_CON 0x0114
1203 +#define MT6323_TOP_RST_CON_SET 0x0116
1204 +#define MT6323_TOP_RST_CON_CLR 0x0118
1205 +#define MT6323_TOP_RST_MISC 0x011A
1206 +#define MT6323_TOP_RST_MISC_SET 0x011C
1207 +#define MT6323_TOP_RST_MISC_CLR 0x011E
1208 +#define MT6323_TOP_CKCON0 0x0120
1209 +#define MT6323_TOP_CKCON0_SET 0x0122
1210 +#define MT6323_TOP_CKCON0_CLR 0x0124
1211 +#define MT6323_TOP_CKCON1 0x0126
1212 +#define MT6323_TOP_CKCON1_SET 0x0128
1213 +#define MT6323_TOP_CKCON1_CLR 0x012A
1214 +#define MT6323_TOP_CKTST0 0x012C
1215 +#define MT6323_TOP_CKTST1 0x012E
1216 +#define MT6323_TOP_CKTST2 0x0130
1217 +#define MT6323_TEST_OUT 0x0132
1218 +#define MT6323_TEST_CON0 0x0134
1219 +#define MT6323_TEST_CON1 0x0136
1220 +#define MT6323_EN_STATUS0 0x0138
1221 +#define MT6323_EN_STATUS1 0x013A
1222 +#define MT6323_OCSTATUS0 0x013C
1223 +#define MT6323_OCSTATUS1 0x013E
1224 +#define MT6323_PGSTATUS 0x0140
1225 +#define MT6323_CHRSTATUS 0x0142
1226 +#define MT6323_TDSEL_CON 0x0144
1227 +#define MT6323_RDSEL_CON 0x0146
1228 +#define MT6323_SMT_CON0 0x0148
1229 +#define MT6323_SMT_CON1 0x014A
1230 +#define MT6323_SMT_CON2 0x014C
1231 +#define MT6323_SMT_CON3 0x014E
1232 +#define MT6323_SMT_CON4 0x0150
1233 +#define MT6323_DRV_CON0 0x0152
1234 +#define MT6323_DRV_CON1 0x0154
1235 +#define MT6323_DRV_CON2 0x0156
1236 +#define MT6323_DRV_CON3 0x0158
1237 +#define MT6323_DRV_CON4 0x015A
1238 +#define MT6323_SIMLS1_CON 0x015C
1239 +#define MT6323_SIMLS2_CON 0x015E
1240 +#define MT6323_INT_CON0 0x0160
1241 +#define MT6323_INT_CON0_SET 0x0162
1242 +#define MT6323_INT_CON0_CLR 0x0164
1243 +#define MT6323_INT_CON1 0x0166
1244 +#define MT6323_INT_CON1_SET 0x0168
1245 +#define MT6323_INT_CON1_CLR 0x016A
1246 +#define MT6323_INT_MISC_CON 0x016C
1247 +#define MT6323_INT_MISC_CON_SET 0x016E
1248 +#define MT6323_INT_MISC_CON_CLR 0x0170
1249 +#define MT6323_INT_STATUS0 0x0172
1250 +#define MT6323_INT_STATUS1 0x0174
1251 +#define MT6323_OC_GEAR_0 0x0176
1252 +#define MT6323_OC_GEAR_1 0x0178
1253 +#define MT6323_OC_GEAR_2 0x017A
1254 +#define MT6323_OC_CTL_VPROC 0x017C
1255 +#define MT6323_OC_CTL_VSYS 0x017E
1256 +#define MT6323_OC_CTL_VPA 0x0180
1257 +#define MT6323_FQMTR_CON0 0x0182
1258 +#define MT6323_FQMTR_CON1 0x0184
1259 +#define MT6323_FQMTR_CON2 0x0186
1260 +#define MT6323_RG_SPI_CON 0x0188
1261 +#define MT6323_DEW_DIO_EN 0x018A
1262 +#define MT6323_DEW_READ_TEST 0x018C
1263 +#define MT6323_DEW_WRITE_TEST 0x018E
1264 +#define MT6323_DEW_CRC_SWRST 0x0190
1265 +#define MT6323_DEW_CRC_EN 0x0192
1266 +#define MT6323_DEW_CRC_VAL 0x0194
1267 +#define MT6323_DEW_DBG_MON_SEL 0x0196
1268 +#define MT6323_DEW_CIPHER_KEY_SEL 0x0198
1269 +#define MT6323_DEW_CIPHER_IV_SEL 0x019A
1270 +#define MT6323_DEW_CIPHER_EN 0x019C
1271 +#define MT6323_DEW_CIPHER_RDY 0x019E
1272 +#define MT6323_DEW_CIPHER_MODE 0x01A0
1273 +#define MT6323_DEW_CIPHER_SWRST 0x01A2
1274 +#define MT6323_DEW_RDDMY_NO 0x01A4
1275 +#define MT6323_DEW_RDATA_DLY_SEL 0x01A6
1276 +#define MT6323_BUCK_CON0 0x0200
1277 +#define MT6323_BUCK_CON1 0x0202
1278 +#define MT6323_BUCK_CON2 0x0204
1279 +#define MT6323_BUCK_CON3 0x0206
1280 +#define MT6323_BUCK_CON4 0x0208
1281 +#define MT6323_BUCK_CON5 0x020A
1282 +#define MT6323_VPROC_CON0 0x020C
1283 +#define MT6323_VPROC_CON1 0x020E
1284 +#define MT6323_VPROC_CON2 0x0210
1285 +#define MT6323_VPROC_CON3 0x0212
1286 +#define MT6323_VPROC_CON4 0x0214
1287 +#define MT6323_VPROC_CON5 0x0216
1288 +#define MT6323_VPROC_CON7 0x021A
1289 +#define MT6323_VPROC_CON8 0x021C
1290 +#define MT6323_VPROC_CON9 0x021E
1291 +#define MT6323_VPROC_CON10 0x0220
1292 +#define MT6323_VPROC_CON11 0x0222
1293 +#define MT6323_VPROC_CON12 0x0224
1294 +#define MT6323_VPROC_CON13 0x0226
1295 +#define MT6323_VPROC_CON14 0x0228
1296 +#define MT6323_VPROC_CON15 0x022A
1297 +#define MT6323_VPROC_CON18 0x0230
1298 +#define MT6323_VSYS_CON0 0x0232
1299 +#define MT6323_VSYS_CON1 0x0234
1300 +#define MT6323_VSYS_CON2 0x0236
1301 +#define MT6323_VSYS_CON3 0x0238
1302 +#define MT6323_VSYS_CON4 0x023A
1303 +#define MT6323_VSYS_CON5 0x023C
1304 +#define MT6323_VSYS_CON7 0x0240
1305 +#define MT6323_VSYS_CON8 0x0242
1306 +#define MT6323_VSYS_CON9 0x0244
1307 +#define MT6323_VSYS_CON10 0x0246
1308 +#define MT6323_VSYS_CON11 0x0248
1309 +#define MT6323_VSYS_CON12 0x024A
1310 +#define MT6323_VSYS_CON13 0x024C
1311 +#define MT6323_VSYS_CON14 0x024E
1312 +#define MT6323_VSYS_CON15 0x0250
1313 +#define MT6323_VSYS_CON18 0x0256
1314 +#define MT6323_VPA_CON0 0x0300
1315 +#define MT6323_VPA_CON1 0x0302
1316 +#define MT6323_VPA_CON2 0x0304
1317 +#define MT6323_VPA_CON3 0x0306
1318 +#define MT6323_VPA_CON4 0x0308
1319 +#define MT6323_VPA_CON5 0x030A
1320 +#define MT6323_VPA_CON7 0x030E
1321 +#define MT6323_VPA_CON8 0x0310
1322 +#define MT6323_VPA_CON9 0x0312
1323 +#define MT6323_VPA_CON10 0x0314
1324 +#define MT6323_VPA_CON11 0x0316
1325 +#define MT6323_VPA_CON12 0x0318
1326 +#define MT6323_VPA_CON14 0x031C
1327 +#define MT6323_VPA_CON16 0x0320
1328 +#define MT6323_VPA_CON17 0x0322
1329 +#define MT6323_VPA_CON18 0x0324
1330 +#define MT6323_VPA_CON19 0x0326
1331 +#define MT6323_VPA_CON20 0x0328
1332 +#define MT6323_BUCK_K_CON0 0x032A
1333 +#define MT6323_BUCK_K_CON1 0x032C
1334 +#define MT6323_BUCK_K_CON2 0x032E
1335 +#define MT6323_ISINK0_CON0 0x0330
1336 +#define MT6323_ISINK0_CON1 0x0332
1337 +#define MT6323_ISINK0_CON2 0x0334
1338 +#define MT6323_ISINK0_CON3 0x0336
1339 +#define MT6323_ISINK1_CON0 0x0338
1340 +#define MT6323_ISINK1_CON1 0x033A
1341 +#define MT6323_ISINK1_CON2 0x033C
1342 +#define MT6323_ISINK1_CON3 0x033E
1343 +#define MT6323_ISINK2_CON0 0x0340
1344 +#define MT6323_ISINK2_CON1 0x0342
1345 +#define MT6323_ISINK2_CON2 0x0344
1346 +#define MT6323_ISINK2_CON3 0x0346
1347 +#define MT6323_ISINK3_CON0 0x0348
1348 +#define MT6323_ISINK3_CON1 0x034A
1349 +#define MT6323_ISINK3_CON2 0x034C
1350 +#define MT6323_ISINK3_CON3 0x034E
1351 +#define MT6323_ISINK_ANA0 0x0350
1352 +#define MT6323_ISINK_ANA1 0x0352
1353 +#define MT6323_ISINK_PHASE_DLY 0x0354
1354 +#define MT6323_ISINK_EN_CTRL 0x0356
1355 +#define MT6323_ANALDO_CON0 0x0400
1356 +#define MT6323_ANALDO_CON1 0x0402
1357 +#define MT6323_ANALDO_CON2 0x0404
1358 +#define MT6323_ANALDO_CON3 0x0406
1359 +#define MT6323_ANALDO_CON4 0x0408
1360 +#define MT6323_ANALDO_CON5 0x040A
1361 +#define MT6323_ANALDO_CON6 0x040C
1362 +#define MT6323_ANALDO_CON7 0x040E
1363 +#define MT6323_ANALDO_CON8 0x0410
1364 +#define MT6323_ANALDO_CON10 0x0412
1365 +#define MT6323_ANALDO_CON15 0x0414
1366 +#define MT6323_ANALDO_CON16 0x0416
1367 +#define MT6323_ANALDO_CON17 0x0418
1368 +#define MT6323_ANALDO_CON18 0x041A
1369 +#define MT6323_ANALDO_CON19 0x041C
1370 +#define MT6323_ANALDO_CON20 0x041E
1371 +#define MT6323_ANALDO_CON21 0x0420
1372 +#define MT6323_DIGLDO_CON0 0x0500
1373 +#define MT6323_DIGLDO_CON2 0x0502
1374 +#define MT6323_DIGLDO_CON3 0x0504
1375 +#define MT6323_DIGLDO_CON5 0x0506
1376 +#define MT6323_DIGLDO_CON6 0x0508
1377 +#define MT6323_DIGLDO_CON7 0x050A
1378 +#define MT6323_DIGLDO_CON8 0x050C
1379 +#define MT6323_DIGLDO_CON9 0x050E
1380 +#define MT6323_DIGLDO_CON10 0x0510
1381 +#define MT6323_DIGLDO_CON11 0x0512
1382 +#define MT6323_DIGLDO_CON12 0x0514
1383 +#define MT6323_DIGLDO_CON13 0x0516
1384 +#define MT6323_DIGLDO_CON14 0x0518
1385 +#define MT6323_DIGLDO_CON15 0x051A
1386 +#define MT6323_DIGLDO_CON16 0x051C
1387 +#define MT6323_DIGLDO_CON17 0x051E
1388 +#define MT6323_DIGLDO_CON18 0x0520
1389 +#define MT6323_DIGLDO_CON19 0x0522
1390 +#define MT6323_DIGLDO_CON20 0x0524
1391 +#define MT6323_DIGLDO_CON21 0x0526
1392 +#define MT6323_DIGLDO_CON23 0x0528
1393 +#define MT6323_DIGLDO_CON24 0x052A
1394 +#define MT6323_DIGLDO_CON26 0x052C
1395 +#define MT6323_DIGLDO_CON27 0x052E
1396 +#define MT6323_DIGLDO_CON28 0x0530
1397 +#define MT6323_DIGLDO_CON29 0x0532
1398 +#define MT6323_DIGLDO_CON30 0x0534
1399 +#define MT6323_DIGLDO_CON31 0x0536
1400 +#define MT6323_DIGLDO_CON32 0x0538
1401 +#define MT6323_DIGLDO_CON33 0x053A
1402 +#define MT6323_DIGLDO_CON34 0x053C
1403 +#define MT6323_DIGLDO_CON35 0x053E
1404 +#define MT6323_DIGLDO_CON36 0x0540
1405 +#define MT6323_DIGLDO_CON39 0x0542
1406 +#define MT6323_DIGLDO_CON40 0x0544
1407 +#define MT6323_DIGLDO_CON41 0x0546
1408 +#define MT6323_DIGLDO_CON42 0x0548
1409 +#define MT6323_DIGLDO_CON43 0x054A
1410 +#define MT6323_DIGLDO_CON44 0x054C
1411 +#define MT6323_DIGLDO_CON45 0x054E
1412 +#define MT6323_DIGLDO_CON46 0x0550
1413 +#define MT6323_DIGLDO_CON47 0x0552
1414 +#define MT6323_DIGLDO_CON48 0x0554
1415 +#define MT6323_DIGLDO_CON49 0x0556
1416 +#define MT6323_DIGLDO_CON50 0x0558
1417 +#define MT6323_DIGLDO_CON51 0x055A
1418 +#define MT6323_DIGLDO_CON52 0x055C
1419 +#define MT6323_DIGLDO_CON53 0x055E
1420 +#define MT6323_DIGLDO_CON54 0x0560
1421 +#define MT6323_EFUSE_CON0 0x0600
1422 +#define MT6323_EFUSE_CON1 0x0602
1423 +#define MT6323_EFUSE_CON2 0x0604
1424 +#define MT6323_EFUSE_CON3 0x0606
1425 +#define MT6323_EFUSE_CON4 0x0608
1426 +#define MT6323_EFUSE_CON5 0x060A
1427 +#define MT6323_EFUSE_CON6 0x060C
1428 +#define MT6323_EFUSE_VAL_0_15 0x060E
1429 +#define MT6323_EFUSE_VAL_16_31 0x0610
1430 +#define MT6323_EFUSE_VAL_32_47 0x0612
1431 +#define MT6323_EFUSE_VAL_48_63 0x0614
1432 +#define MT6323_EFUSE_VAL_64_79 0x0616
1433 +#define MT6323_EFUSE_VAL_80_95 0x0618
1434 +#define MT6323_EFUSE_VAL_96_111 0x061A
1435 +#define MT6323_EFUSE_VAL_112_127 0x061C
1436 +#define MT6323_EFUSE_VAL_128_143 0x061E
1437 +#define MT6323_EFUSE_VAL_144_159 0x0620
1438 +#define MT6323_EFUSE_VAL_160_175 0x0622
1439 +#define MT6323_EFUSE_VAL_176_191 0x0624
1440 +#define MT6323_EFUSE_DOUT_0_15 0x0626
1441 +#define MT6323_EFUSE_DOUT_16_31 0x0628
1442 +#define MT6323_EFUSE_DOUT_32_47 0x062A
1443 +#define MT6323_EFUSE_DOUT_48_63 0x062C
1444 +#define MT6323_EFUSE_DOUT_64_79 0x062E
1445 +#define MT6323_EFUSE_DOUT_80_95 0x0630
1446 +#define MT6323_EFUSE_DOUT_96_111 0x0632
1447 +#define MT6323_EFUSE_DOUT_112_127 0x0634
1448 +#define MT6323_EFUSE_DOUT_128_143 0x0636
1449 +#define MT6323_EFUSE_DOUT_144_159 0x0638
1450 +#define MT6323_EFUSE_DOUT_160_175 0x063A
1451 +#define MT6323_EFUSE_DOUT_176_191 0x063C
1452 +#define MT6323_EFUSE_CON7 0x063E
1453 +#define MT6323_EFUSE_CON8 0x0640
1454 +#define MT6323_EFUSE_CON9 0x0642
1455 +#define MT6323_RTC_MIX_CON0 0x0644
1456 +#define MT6323_RTC_MIX_CON1 0x0646
1457 +#define MT6323_AUDTOP_CON0 0x0700
1458 +#define MT6323_AUDTOP_CON1 0x0702
1459 +#define MT6323_AUDTOP_CON2 0x0704
1460 +#define MT6323_AUDTOP_CON3 0x0706
1461 +#define MT6323_AUDTOP_CON4 0x0708
1462 +#define MT6323_AUDTOP_CON5 0x070A
1463 +#define MT6323_AUDTOP_CON6 0x070C
1464 +#define MT6323_AUDTOP_CON7 0x070E
1465 +#define MT6323_AUDTOP_CON8 0x0710
1466 +#define MT6323_AUDTOP_CON9 0x0712
1467 +#define MT6323_AUXADC_ADC0 0x0714
1468 +#define MT6323_AUXADC_ADC1 0x0716
1469 +#define MT6323_AUXADC_ADC2 0x0718
1470 +#define MT6323_AUXADC_ADC3 0x071A
1471 +#define MT6323_AUXADC_ADC4 0x071C
1472 +#define MT6323_AUXADC_ADC5 0x071E
1473 +#define MT6323_AUXADC_ADC6 0x0720
1474 +#define MT6323_AUXADC_ADC7 0x0722
1475 +#define MT6323_AUXADC_ADC8 0x0724
1476 +#define MT6323_AUXADC_ADC9 0x0726
1477 +#define MT6323_AUXADC_ADC10 0x0728
1478 +#define MT6323_AUXADC_ADC11 0x072A
1479 +#define MT6323_AUXADC_ADC12 0x072C
1480 +#define MT6323_AUXADC_ADC13 0x072E
1481 +#define MT6323_AUXADC_ADC14 0x0730
1482 +#define MT6323_AUXADC_ADC15 0x0732
1483 +#define MT6323_AUXADC_ADC16 0x0734
1484 +#define MT6323_AUXADC_ADC17 0x0736
1485 +#define MT6323_AUXADC_ADC18 0x0738
1486 +#define MT6323_AUXADC_ADC19 0x073A
1487 +#define MT6323_AUXADC_ADC20 0x073C
1488 +#define MT6323_AUXADC_RSV1 0x073E
1489 +#define MT6323_AUXADC_RSV2 0x0740
1490 +#define MT6323_AUXADC_CON0 0x0742
1491 +#define MT6323_AUXADC_CON1 0x0744
1492 +#define MT6323_AUXADC_CON2 0x0746
1493 +#define MT6323_AUXADC_CON3 0x0748
1494 +#define MT6323_AUXADC_CON4 0x074A
1495 +#define MT6323_AUXADC_CON5 0x074C
1496 +#define MT6323_AUXADC_CON6 0x074E
1497 +#define MT6323_AUXADC_CON7 0x0750
1498 +#define MT6323_AUXADC_CON8 0x0752
1499 +#define MT6323_AUXADC_CON9 0x0754
1500 +#define MT6323_AUXADC_CON10 0x0756
1501 +#define MT6323_AUXADC_CON11 0x0758
1502 +#define MT6323_AUXADC_CON12 0x075A
1503 +#define MT6323_AUXADC_CON13 0x075C
1504 +#define MT6323_AUXADC_CON14 0x075E
1505 +#define MT6323_AUXADC_CON15 0x0760
1506 +#define MT6323_AUXADC_CON16 0x0762
1507 +#define MT6323_AUXADC_CON17 0x0764
1508 +#define MT6323_AUXADC_CON18 0x0766
1509 +#define MT6323_AUXADC_CON19 0x0768
1510 +#define MT6323_AUXADC_CON20 0x076A
1511 +#define MT6323_AUXADC_CON21 0x076C
1512 +#define MT6323_AUXADC_CON22 0x076E
1513 +#define MT6323_AUXADC_CON23 0x0770
1514 +#define MT6323_AUXADC_CON24 0x0772
1515 +#define MT6323_AUXADC_CON25 0x0774
1516 +#define MT6323_AUXADC_CON26 0x0776
1517 +#define MT6323_AUXADC_CON27 0x0778
1518 +#define MT6323_ACCDET_CON0 0x077A
1519 +#define MT6323_ACCDET_CON1 0x077C
1520 +#define MT6323_ACCDET_CON2 0x077E
1521 +#define MT6323_ACCDET_CON3 0x0780
1522 +#define MT6323_ACCDET_CON4 0x0782
1523 +#define MT6323_ACCDET_CON5 0x0784
1524 +#define MT6323_ACCDET_CON6 0x0786
1525 +#define MT6323_ACCDET_CON7 0x0788
1526 +#define MT6323_ACCDET_CON8 0x078A
1527 +#define MT6323_ACCDET_CON9 0x078C
1528 +#define MT6323_ACCDET_CON10 0x078E
1529 +#define MT6323_ACCDET_CON11 0x0790
1530 +#define MT6323_ACCDET_CON12 0x0792
1531 +#define MT6323_ACCDET_CON13 0x0794
1532 +#define MT6323_ACCDET_CON14 0x0796
1533 +#define MT6323_ACCDET_CON15 0x0798
1534 +#define MT6323_ACCDET_CON16 0x079A
1535
1536 -#endif /* __MFD_MT6397_REGISTERS_H__ */
1537 +#endif
1538 --- /dev/null
1539 +++ b/include/linux/regulator/mt6323-regulator.h
1540 @@ -0,0 +1,37 @@
1541 +/*
1542 + * Copyright (c) 2015 MediaTek Inc.
1543 + * Author: John Crispin <blogic@openwrt.org>
1544 + *
1545 + * This program is free software; you can redistribute it and/or modify
1546 + * it under the terms of the GNU General Public License version 2 as
1547 + * published by the Free Software Foundation.
1548 + *
1549 + * This program is distributed in the hope that it will be useful,
1550 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1551 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1552 + * GNU General Public License for more details.
1553 + */
1554 +
1555 +#ifndef __LINUX_REGULATOR_MT6323_H
1556 +#define __LINUX_REGULATOR_MT6323_H
1557 +
1558 +enum {
1559 + MT6323_ID_VPROC = 0,
1560 + MT6323_ID_VSYS,
1561 + MT6323_ID_VPA,
1562 + MT6323_ID_VTCXO,
1563 + MT6323_ID_VA,
1564 + MT6323_ID_VCN28,
1565 + MT6323_ID_VCN33,
1566 + MT6323_ID_VIO28,
1567 + MT6323_ID_VUSB,
1568 + MT6323_ID_VMC,
1569 + MT6323_ID_VMCH,
1570 + MT6323_ID_VGP1,
1571 + MT6323_ID_VGP2,
1572 + MT6323_ID_RG_MAX,
1573 +};
1574 +
1575 +#define MT6323_MAX_REGULATOR MT6323_ID_RG_MAX
1576 +
1577 +#endif /* __LINUX_REGULATOR_MT6323_H */
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