1 diff -urN a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c
2 --- a/drivers/clk/clk-devres.c 2019-08-29 16:59:26.540010395 +0800
3 +++ b/drivers/clk/clk-devres.c 2019-08-29 17:02:09.215924786 +0800
6 EXPORT_SYMBOL(devm_clk_get);
8 +struct clk *devm_clk_get_optional(struct device *dev, const char *id)
10 + struct clk *clk = devm_clk_get(dev, id);
12 + if (clk == ERR_PTR(-ENOENT))
17 +EXPORT_SYMBOL(devm_clk_get_optional);
19 struct clk_bulk_devres {
20 struct clk_bulk_data *clks;
22 diff -urN a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
23 --- a/drivers/pci/controller/pcie-mediatek.c 2019-08-29 16:59:10.520410188 +0800
24 +++ b/drivers/pci/controller/pcie-mediatek.c 2019-08-29 17:01:58.340199243 +0800
26 #include <linux/irqdomain.h>
27 #include <linux/kernel.h>
28 #include <linux/msi.h>
29 +#include <linux/module.h>
30 #include <linux/of_address.h>
31 #include <linux/of_pci.h>
32 #include <linux/of_platform.h>
34 * @phy: pointer to PHY control block
38 * @irq_domain: legacy INTx IRQ domain
39 * @inner_domain: inner IRQ domain
40 * @msi_domain: MSI IRQ domain
46 struct irq_domain *irq_domain;
47 struct irq_domain *inner_domain;
48 struct irq_domain *msi_domain;
51 clk_disable_unprepare(pcie->free_ck);
53 - if (dev->pm_domain) {
54 - pm_runtime_put_sync(dev);
55 - pm_runtime_disable(dev);
57 + pm_runtime_put_sync(dev);
58 + pm_runtime_disable(dev);
61 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
63 .write = mtk_pcie_config_write,
66 -static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
68 - struct mtk_pcie *pcie = port->pcie;
69 - struct resource *mem = &pcie->mem;
70 - const struct mtk_pcie_soc *soc = port->pcie->soc;
75 - /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
77 - val = readl(pcie->base + PCIE_SYS_CFG_V2);
78 - val |= PCIE_CSR_LTSSM_EN(port->slot) |
79 - PCIE_CSR_ASPM_L1_EN(port->slot);
80 - writel(val, pcie->base + PCIE_SYS_CFG_V2);
83 - /* Assert all reset signals */
84 - writel(0, port->base + PCIE_RST_CTRL);
87 - * Enable PCIe link down reset, if link status changed from link up to
88 - * link down, this will reset MAC control registers and configuration
91 - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
93 - /* De-assert PHY, PE, PIPE, MAC and configuration reset */
94 - val = readl(port->base + PCIE_RST_CTRL);
95 - val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
96 - PCIE_MAC_SRSTB | PCIE_CRSTB;
97 - writel(val, port->base + PCIE_RST_CTRL);
99 - /* Set up vendor ID and class code */
100 - if (soc->need_fix_class_id) {
101 - val = PCI_VENDOR_ID_MEDIATEK;
102 - writew(val, port->base + PCIE_CONF_VEND_ID);
104 - val = PCI_CLASS_BRIDGE_HOST;
105 - writew(val, port->base + PCIE_CONF_CLASS_ID);
108 - /* 100ms timeout value should be enough for Gen1/2 training */
109 - err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
110 - !!(val & PCIE_PORT_LINKUP_V2), 20,
111 - 100 * USEC_PER_MSEC);
115 - /* Set INTx mask */
116 - val = readl(port->base + PCIE_INT_MASK);
118 - writel(val, port->base + PCIE_INT_MASK);
120 - /* Set AHB to PCIe translation windows */
121 - size = mem->end - mem->start;
122 - val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
123 - writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
125 - val = upper_32_bits(mem->start);
126 - writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
128 - /* Set PCIe to AXI translation memory space.*/
129 - val = fls(0xffffffff) | WIN_ENABLE;
130 - writel(val, port->base + PCIE_AXI_WINDOW0);
135 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
137 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
139 writel(val, port->base + PCIE_INT_MASK);
142 +static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
144 + struct mtk_pcie_port *port, *tmp;
146 + list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
147 + irq_set_chained_handler_and_data(port->irq, NULL, NULL);
149 + if (port->irq_domain)
150 + irq_domain_remove(port->irq_domain);
152 + if (IS_ENABLED(CONFIG_PCI_MSI)) {
153 + if (port->msi_domain)
154 + irq_domain_remove(port->msi_domain);
155 + if (port->inner_domain)
156 + irq_domain_remove(port->inner_domain);
159 + irq_dispose_mapping(port->irq);
163 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
164 irq_hw_number_t hwirq)
168 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
169 &intx_domain_ops, port);
170 + of_node_put(pcie_intc_node);
171 if (!port->irq_domain) {
172 dev_err(dev, "failed to get INTx IRQ domain\n");
175 ret = mtk_pcie_allocate_msi_domains(port);
179 - mtk_pcie_enable_msi(port);
184 struct mtk_pcie *pcie = port->pcie;
185 struct device *dev = pcie->dev;
186 struct platform_device *pdev = to_platform_device(dev);
190 err = mtk_pcie_init_irq_domain(port, node);
196 - irq = platform_get_irq(pdev, port->slot);
197 - irq_set_chained_handler_and_data(irq, mtk_pcie_intr_handler, port);
198 + port->irq = platform_get_irq(pdev, port->slot);
199 + irq_set_chained_handler_and_data(port->irq,
200 + mtk_pcie_intr_handler, port);
205 +static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
207 + struct mtk_pcie *pcie = port->pcie;
208 + struct resource *mem = &pcie->mem;
209 + const struct mtk_pcie_soc *soc = port->pcie->soc;
214 + /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
216 + val = readl(pcie->base + PCIE_SYS_CFG_V2);
217 + val |= PCIE_CSR_LTSSM_EN(port->slot) |
218 + PCIE_CSR_ASPM_L1_EN(port->slot);
219 + writel(val, pcie->base + PCIE_SYS_CFG_V2);
222 + /* Assert all reset signals */
223 + writel(0, port->base + PCIE_RST_CTRL);
226 + * Enable PCIe link down reset, if link status changed from link up to
227 + * link down, this will reset MAC control registers and configuration
230 + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
232 + /* De-assert PHY, PE, PIPE, MAC and configuration reset */
233 + val = readl(port->base + PCIE_RST_CTRL);
234 + val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
235 + PCIE_MAC_SRSTB | PCIE_CRSTB;
236 + writel(val, port->base + PCIE_RST_CTRL);
238 + /* Set up vendor ID and class code */
239 + if (soc->need_fix_class_id) {
240 + val = PCI_VENDOR_ID_MEDIATEK;
241 + writew(val, port->base + PCIE_CONF_VEND_ID);
243 + val = PCI_CLASS_BRIDGE_PCI;
244 + writew(val, port->base + PCIE_CONF_CLASS_ID);
247 + /* 100ms timeout value should be enough for Gen1/2 training */
248 + err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
249 + !!(val & PCIE_PORT_LINKUP_V2), 20,
250 + 100 * USEC_PER_MSEC);
254 + /* Set INTx mask */
255 + val = readl(port->base + PCIE_INT_MASK);
257 + writel(val, port->base + PCIE_INT_MASK);
259 + if (IS_ENABLED(CONFIG_PCI_MSI))
260 + mtk_pcie_enable_msi(port);
262 + /* Set AHB to PCIe translation windows */
263 + size = mem->end - mem->start;
264 + val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
265 + writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
267 + val = upper_32_bits(mem->start);
268 + writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
270 + /* Set PCIe to AXI translation memory space.*/
271 + val = fls(0xffffffff) | WIN_ENABLE;
272 + writel(val, port->base + PCIE_AXI_WINDOW0);
276 @@ -903,49 +928,29 @@
278 /* sys_ck might be divided into the following parts in some chips */
279 snprintf(name, sizeof(name), "ahb_ck%d", slot);
280 - port->ahb_ck = devm_clk_get(dev, name);
281 - if (IS_ERR(port->ahb_ck)) {
282 - if (PTR_ERR(port->ahb_ck) == -EPROBE_DEFER)
283 - return -EPROBE_DEFER;
285 - port->ahb_ck = NULL;
287 + port->ahb_ck = devm_clk_get_optional(dev, name);
288 + if (IS_ERR(port->ahb_ck))
289 + return PTR_ERR(port->ahb_ck);
291 snprintf(name, sizeof(name), "axi_ck%d", slot);
292 - port->axi_ck = devm_clk_get(dev, name);
293 - if (IS_ERR(port->axi_ck)) {
294 - if (PTR_ERR(port->axi_ck) == -EPROBE_DEFER)
295 - return -EPROBE_DEFER;
297 - port->axi_ck = NULL;
299 + port->axi_ck = devm_clk_get_optional(dev, name);
300 + if (IS_ERR(port->axi_ck))
301 + return PTR_ERR(port->axi_ck);
303 snprintf(name, sizeof(name), "aux_ck%d", slot);
304 - port->aux_ck = devm_clk_get(dev, name);
305 - if (IS_ERR(port->aux_ck)) {
306 - if (PTR_ERR(port->aux_ck) == -EPROBE_DEFER)
307 - return -EPROBE_DEFER;
309 - port->aux_ck = NULL;
311 + port->aux_ck = devm_clk_get_optional(dev, name);
312 + if (IS_ERR(port->aux_ck))
313 + return PTR_ERR(port->aux_ck);
315 snprintf(name, sizeof(name), "obff_ck%d", slot);
316 - port->obff_ck = devm_clk_get(dev, name);
317 - if (IS_ERR(port->obff_ck)) {
318 - if (PTR_ERR(port->obff_ck) == -EPROBE_DEFER)
319 - return -EPROBE_DEFER;
321 - port->obff_ck = NULL;
323 + port->obff_ck = devm_clk_get_optional(dev, name);
324 + if (IS_ERR(port->obff_ck))
325 + return PTR_ERR(port->obff_ck);
327 snprintf(name, sizeof(name), "pipe_ck%d", slot);
328 - port->pipe_ck = devm_clk_get(dev, name);
329 - if (IS_ERR(port->pipe_ck)) {
330 - if (PTR_ERR(port->pipe_ck) == -EPROBE_DEFER)
331 - return -EPROBE_DEFER;
333 - port->pipe_ck = NULL;
335 + port->pipe_ck = devm_clk_get_optional(dev, name);
336 + if (IS_ERR(port->pipe_ck))
337 + return PTR_ERR(port->pipe_ck);
339 snprintf(name, sizeof(name), "pcie-rst%d", slot);
340 port->reset = devm_reset_control_get_optional_exclusive(dev, name);
341 @@ -998,10 +1003,8 @@
342 pcie->free_ck = NULL;
345 - if (dev->pm_domain) {
346 - pm_runtime_enable(dev);
347 - pm_runtime_get_sync(dev);
349 + pm_runtime_enable(dev);
350 + pm_runtime_get_sync(dev);
352 /* enable top level clock */
353 err = clk_prepare_enable(pcie->free_ck);
354 @@ -1013,10 +1016,8 @@
358 - if (dev->pm_domain) {
359 - pm_runtime_put_sync(dev);
360 - pm_runtime_disable(dev);
362 + pm_runtime_put_sync(dev);
363 + pm_runtime_disable(dev);
367 @@ -1125,34 +1126,6 @@
371 -static int mtk_pcie_register_host(struct pci_host_bridge *host)
373 - struct mtk_pcie *pcie = pci_host_bridge_priv(host);
374 - struct pci_bus *child;
377 - host->busnr = pcie->busn.start;
378 - host->dev.parent = pcie->dev;
379 - host->ops = pcie->soc->ops;
380 - host->map_irq = of_irq_parse_and_map_pci;
381 - host->swizzle_irq = pci_common_swizzle;
382 - host->sysdata = pcie;
384 - err = pci_scan_root_bus_bridge(host);
388 - pci_bus_size_bridges(host->bus);
389 - pci_bus_assign_resources(host->bus);
391 - list_for_each_entry(child, &host->bus->children, node)
392 - pcie_bus_configure_settings(child);
394 - pci_bus_add_devices(host->bus);
399 static int mtk_pcie_probe(struct platform_device *pdev)
401 struct device *dev = &pdev->dev;
402 @@ -1179,7 +1152,14 @@
406 - err = mtk_pcie_register_host(host);
407 + host->busnr = pcie->busn.start;
408 + host->dev.parent = pcie->dev;
409 + host->ops = pcie->soc->ops;
410 + host->map_irq = of_irq_parse_and_map_pci;
411 + host->swizzle_irq = pci_common_swizzle;
412 + host->sysdata = pcie;
414 + err = pci_host_probe(host);
418 @@ -1192,6 +1172,80 @@
423 +static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
425 + struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
426 + struct list_head *windows = &host->windows;
428 + pci_free_resource_list(windows);
431 +static int mtk_pcie_remove(struct platform_device *pdev)
433 + struct mtk_pcie *pcie = platform_get_drvdata(pdev);
434 + struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
436 + pci_stop_root_bus(host->bus);
437 + pci_remove_root_bus(host->bus);
438 + mtk_pcie_free_resources(pcie);
440 + mtk_pcie_irq_teardown(pcie);
442 + mtk_pcie_put_resources(pcie);
447 +static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
449 + struct mtk_pcie *pcie = dev_get_drvdata(dev);
450 + struct mtk_pcie_port *port;
452 + if (list_empty(&pcie->ports))
455 + list_for_each_entry(port, &pcie->ports, list) {
456 + clk_disable_unprepare(port->pipe_ck);
457 + clk_disable_unprepare(port->obff_ck);
458 + clk_disable_unprepare(port->axi_ck);
459 + clk_disable_unprepare(port->aux_ck);
460 + clk_disable_unprepare(port->ahb_ck);
461 + clk_disable_unprepare(port->sys_ck);
462 + phy_power_off(port->phy);
463 + phy_exit(port->phy);
466 + clk_disable_unprepare(pcie->free_ck);
471 +static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
473 + struct mtk_pcie *pcie = dev_get_drvdata(dev);
474 + struct mtk_pcie_port *port, *tmp;
476 + if (list_empty(&pcie->ports))
479 + clk_prepare_enable(pcie->free_ck);
481 + list_for_each_entry_safe(port, tmp, &pcie->ports, list)
482 + mtk_pcie_enable_port(port);
484 + /* In case of EP was removed while system suspend. */
485 + if (list_empty(&pcie->ports))
486 + clk_disable_unprepare(pcie->free_ck);
491 +static const struct dev_pm_ops mtk_pcie_pm_ops = {
492 + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
493 + mtk_pcie_resume_noirq)
496 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
497 .ops = &mtk_pcie_ops,
498 .startup = mtk_pcie_startup_port,
499 @@ -1220,10 +1274,13 @@
501 static struct platform_driver mtk_pcie_driver = {
502 .probe = mtk_pcie_probe,
503 + .remove = mtk_pcie_remove,
506 .of_match_table = mtk_pcie_ids,
507 .suppress_bind_attrs = true,
508 + .pm = &mtk_pcie_pm_ops,
511 -builtin_platform_driver(mtk_pcie_driver);
512 +module_platform_driver(mtk_pcie_driver);
513 +MODULE_LICENSE("GPL v2");
514 diff -urN a/include/linux/clk.h b/include/linux/clk.h
515 --- a/include/linux/clk.h 2019-08-29 16:59:52.335365591 +0800
516 +++ b/include/linux/clk.h 2019-08-29 17:02:17.107725525 +0800
518 struct clk *devm_clk_get(struct device *dev, const char *id);
521 + * devm_clk_get_optional - lookup and obtain a managed reference to an optional
523 + * @dev: device for clock "consumer"
524 + * @id: clock consumer ID
526 + * Behaves the same as devm_clk_get() except where there is no clock producer.
527 + * In this case, instead of returning -ENOENT, the function returns NULL.
529 +struct clk *devm_clk_get_optional(struct device *dev, const char *id);
532 * devm_get_clk_from_child - lookup and obtain a managed reference to a
533 * clock producer from child node.
534 * @dev: device for clock "consumer"