1 Index: linux-4.14.18/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
2 ===================================================================
3 --- linux-4.14.18.orig/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
4 +++ linux-4.14.18/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
6 stdout-path = "serial2:115200n8";
10 + reg = <0 0x80000000 0 0x20000000>;
15 proc-supply = <&mt6323_vproc_reg>;
18 reg = <0 0x80000000 0 0x40000000>;
22 + compatible = "mediatek,mt7530";
32 + compatible = "mediatek,eth-mac";
51 compatible = "mediatek,mt7530";
55 core-supply = <&mt6323_vpa_reg>;
56 io-supply = <&mt6323_vemc3v3_reg>;
58 + dsa,mii-bus = <&mdio>;
98 + ethernet = <&gmac1>;
107 + cpu_port0: port@6 {
119 pinctrl-names = "default";
120 Index: linux-4.14.18/arch/arm/boot/dts/Makefile
121 ===================================================================
122 --- linux-4.14.18.orig/arch/arm/boot/dts/Makefile
123 +++ linux-4.14.18/arch/arm/boot/dts/Makefile
124 @@ -1061,6 +1061,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
126 mt6589-aquaris5.dtb \
128 + mt7623a-rfb-emmc.dtb \
129 mt7623n-rfb-nand.dtb \
130 mt7623n-bananapi-bpi-r2.dtb \
132 Index: linux-4.14.18/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
133 ===================================================================
135 +++ linux-4.14.18/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
138 + * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
140 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
144 +#include <dt-bindings/input/input.h>
145 +#include "mt7623.dtsi"
146 +#include "mt6323.dtsi"
149 + model = "MediaTek MT7623N NAND reference board";
150 + compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
157 + bootargs = "earlyprintk block2mtd.block2mtd=/dev/mmcblk0,65536,eMMC,5 mtdparts=eMMC:256k(mbr)ro,512k(uboot)ro,256k(config)ro,256k(factory)ro,32M(kernel),32M(recovery),1024M(rootfs),2048M(usrdata),-(bmtpool) rootfstype=squashfs,jffs2";
159 + stdout-path = "serial2:115200n8";
163 + reg = <0 0x80000000 0 0x20000000>;
168 + proc-supply = <&mt6323_vproc_reg>;
172 + proc-supply = <&mt6323_vproc_reg>;
176 + proc-supply = <&mt6323_vproc_reg>;
180 + proc-supply = <&mt6323_vproc_reg>;
185 + reg = <0 0x80000000 0 0x40000000>;
189 + compatible = "mediatek,mt7530";
190 + #address-cells = <1>;
203 + compatible = "mediatek,eth-mac";
205 + phy-mode = "trgmii";
215 + compatible = "mediatek,eth-mac";
217 + phy-mode = "rgmiii-rxid";
218 + phy-handle = <&phy5>;
222 + #address-cells = <1>;
224 + phy5: ethernet-phy@5 {
226 + phy-mode = "rgmii-rxid";
232 + compatible = "mediatek,mt7530";
233 + #address-cells = <1>;
236 + pinctrl-names = "default";
238 + resets = <ðsys 2>;
239 + reset-names = "mcm";
240 + core-supply = <&mt6323_vpa_reg>;
241 + io-supply = <&mt6323_vemc3v3_reg>;
243 + dsa,mii-bus = <&mdio>;
246 + #address-cells = <1>;
253 + cpu = <&cpu_port0>;
259 + cpu = <&cpu_port0>;
265 + cpu = <&cpu_port0>;
271 + cpu = <&cpu_port0>;
274 + cpu_port0: port@6 {
277 + ethernet = <&gmac0>;
278 + phy-mode = "trgmii";
289 + pinctrl-names = "default";
290 + pinctrl-0 = <&i2c0_pins_a>;
295 + pinctrl-names = "default";
296 + pinctrl-0 = <&i2c1_pins_a>;
301 + pinctrl-names = "default", "state_uhs";
302 + pinctrl-0 = <&mmc0_pins_default>;
303 + pinctrl-1 = <&mmc0_pins_uhs>;
306 + max-frequency = <50000000>;
308 + vmmc-supply = <&mt6323_vemc3v3_reg>;
309 + vqmmc-supply = <&mt6323_vio18_reg>;
314 + pinctrl-names = "default", "state_uhs";
315 + pinctrl-0 = <&mmc1_pins_default>;
316 + pinctrl-1 = <&mmc1_pins_uhs>;
319 + max-frequency = <50000000>;
321 + cd-gpios = <&pio 261 0>;
322 + vmmc-supply = <&mt6323_vmch_reg>;
323 + vqmmc-supply = <&mt6323_vio18_reg>;
329 + pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
334 + i2c0_pins_a: i2c@0 {
336 + pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
337 + <MT7623_PIN_76_SCL0_FUNC_SCL0>;
342 + i2c1_pins_a: i2c@1 {
344 + pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
345 + <MT7623_PIN_58_SCL1_FUNC_SCL1>;
350 + i2s0_pins_a: i2s@0 {
352 + pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
353 + <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
354 + <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
355 + <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
356 + <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
357 + drive-strength = <MTK_DRIVE_12mA>;
362 + i2s1_pins_a: i2s@1 {
364 + pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
365 + <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
366 + <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
367 + <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
368 + <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
369 + drive-strength = <MTK_DRIVE_12mA>;
374 + mmc0_pins_default: mmc0default {
376 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
377 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
378 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
379 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
380 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
381 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
382 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
383 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
384 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
390 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
395 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
400 + mmc0_pins_uhs: mmc0 {
402 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
403 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
404 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
405 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
406 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
407 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
408 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
409 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
410 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
412 + drive-strength = <MTK_DRIVE_2mA>;
413 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
417 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
418 + drive-strength = <MTK_DRIVE_2mA>;
419 + bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
423 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
428 + mmc1_pins_default: mmc1default {
430 + pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
431 + <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
432 + <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
433 + <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
434 + <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
436 + drive-strength = <MTK_DRIVE_4mA>;
437 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
441 + pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
443 + drive-strength = <MTK_DRIVE_4mA>;
447 + pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
453 + pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
458 + mmc1_pins_uhs: mmc1 {
460 + pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
461 + <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
462 + <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
463 + <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
464 + <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
466 + drive-strength = <MTK_DRIVE_4mA>;
467 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
471 + pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
472 + drive-strength = <MTK_DRIVE_4mA>;
473 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
477 + pwm_pins_a: pwm@0 {
479 + pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
480 + <MT7623_PIN_204_PWM1_FUNC_PWM1>,
481 + <MT7623_PIN_205_PWM2_FUNC_PWM2>,
482 + <MT7623_PIN_206_PWM3_FUNC_PWM3>,
483 + <MT7623_PIN_207_PWM4_FUNC_PWM4>;
487 + spi0_pins_a: spi@0 {
489 + pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
490 + <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
491 + <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
492 + <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
497 + uart0_pins_a: uart@0 {
499 + pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
500 + <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
504 + uart1_pins_a: uart@1 {
506 + pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
507 + <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
513 + pinctrl-names = "default";
514 + pinctrl-0 = <&pwm_pins_a>;
521 + compatible = "mediatek,mt6323-led";
522 + #address-cells = <1>;
527 + label = "bpi-r2:isink:green";
528 + default-state = "off";
533 + label = "bpi-r2:isink:red";
534 + default-state = "off";
539 + label = "bpi-r2:isink:blue";
540 + default-state = "off";
547 + pinctrl-names = "default";
548 + pinctrl-0 = <&spi0_pins_a>;
553 + pinctrl-names = "default";
554 + pinctrl-0 = <&uart0_pins_a>;
555 + status = "disabled";
559 + pinctrl-names = "default";
560 + pinctrl-0 = <&uart1_pins_a>;
561 + status = "disabled";
569 + vusb33-supply = <&mt6323_vusb_reg>;
574 + vusb33-supply = <&mt6323_vusb_reg>;
586 Index: linux-4.14.18/arch/arm/boot/dts/mt7623.dtsi
587 ===================================================================
588 --- linux-4.14.18.orig/arch/arm/boot/dts/mt7623.dtsi
589 +++ linux-4.14.18/arch/arm/boot/dts/mt7623.dtsi
592 reg = <0 0x1b000000 0 0x1000>;
594 + #reset-cells = <1>;
597 eth: ethernet@1b100000 {