1 From 71198859668501ef57450be07da77e9544f59f1e Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Sat, 13 May 2017 15:16:58 +0800
4 Subject: [PATCH 204/224] dt-bindings: dmaengine: Add MediaTek High-Speed DMA
7 Document the devicetree bindings for MediaTek High-Speed DMA controller
8 which could be found on MT7623 SoC or other similar Mediatek SoCs.
10 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
12 .../devicetree/bindings/dma/mtk-hsdma.txt | 33 ++++++++++++++++++++++
13 1 file changed, 33 insertions(+)
14 create mode 100644 Documentation/devicetree/bindings/dma/mtk-hsdma.txt
16 diff --git a/Documentation/devicetree/bindings/dma/mtk-hsdma.txt b/Documentation/devicetree/bindings/dma/mtk-hsdma.txt
18 index 000000000000..4bb317359dc6
20 +++ b/Documentation/devicetree/bindings/dma/mtk-hsdma.txt
22 +MediaTek High-Speed DMA Controller
23 +==================================
25 +This device follows the generic DMA bindings defined in dma/dma.txt.
29 +- compatible: Must be one of
30 + "mediatek,mt7622-hsdma": for MT7622 SoC
31 + "mediatek,mt7623-hsdma": for MT7623 SoC
32 +- reg: Should contain the register's base address and length.
33 +- interrupts: Should contain a reference to the interrupt used by this
35 +- clocks: Should be the clock specifiers corresponding to the entry in
36 + clock-names property.
37 +- clock-names: Should contain "hsdma" entries.
38 +- power-domains: Phandle to the power domain that the device is part of
39 +- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
40 + in dmas property of a client device represents the channel
44 + hsdma: dma-controller@1b007000 {
45 + compatible = "mediatek,mt7623-hsdma";
46 + reg = <0 0x1b007000 0 0x1000>;
47 + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
48 + clocks = <ðsys CLK_ETHSYS_HSDMA>;
49 + clock-names = "hsdma";
50 + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
54 +DMA clients must use the format described in dma/dma.txt file.