1 From 13872b8abfadfe70598c065c19d1db759477c4e6 Mon Sep 17 00:00:00 2001
2 From: Kristian Evensen <kristian.evensen@gmail.com>
3 Date: Sun, 17 Jun 2018 14:41:47 +0200
4 Subject: [PATCH] arm: dts: Add Unielec U7623 DTS
7 arch/arm/boot/dts/Makefile | 1 +
8 .../dts/mt7623a-unielec-u7623-02-emmc-512M.dts | 17 +
9 .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi | 375 +++++++++++++++++++++
10 3 files changed, 393 insertions(+)
11 create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
12 create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
14 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
15 index 3fec84fa0..e685ce9a4 100644
16 --- a/arch/arm/boot/dts/Makefile
17 +++ b/arch/arm/boot/dts/Makefile
18 @@ -1062,6 +1062,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
21 mt7623a-rfb-emmc.dtb \
22 + mt7623a-unielec-u7623-02-emmc-512M.dtb \
23 mt7623n-rfb-nand.dtb \
24 mt7623n-bananapi-bpi-r2.dtb \
26 diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
28 index 000000000..3b14eccd3
30 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
33 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
35 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
39 +#include "mt7623a-unielec-u7623-02-emmc.dtsi"
42 + model = "UniElec U7623-02 eMMC (512M RAM)";
43 + compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623";
46 + reg = <0 0x80000000 0 0x20000000>;
49 diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
51 index 000000000..436b02f2d
53 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
56 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
58 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
61 +#include <dt-bindings/input/input.h>
62 +#include "mt7623.dtsi"
63 +#include "mt6323.dtsi"
66 + compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
73 + bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs";
74 + stdout-path = "serial2:115200n8";
78 + reg = <0 0x80000000 0 0x20000000>;
83 + proc-supply = <&mt6323_vproc_reg>;
87 + proc-supply = <&mt6323_vproc_reg>;
91 + proc-supply = <&mt6323_vproc_reg>;
95 + proc-supply = <&mt6323_vproc_reg>;
99 + reg_1p8v: regulator-1p8v {
100 + compatible = "regulator-fixed";
101 + regulator-name = "fixed-1.8V";
102 + regulator-min-microvolt = <1800000>;
103 + regulator-max-microvolt = <1800000>;
105 + regulator-always-on;
108 + reg_3p3v: regulator-3p3v {
109 + compatible = "regulator-fixed";
110 + regulator-name = "fixed-3.3V";
111 + regulator-min-microvolt = <3300000>;
112 + regulator-max-microvolt = <3300000>;
114 + regulator-always-on;
117 + reg_5v: regulator-5v {
118 + compatible = "regulator-fixed";
119 + regulator-name = "fixed-5V";
120 + regulator-min-microvolt = <5000000>;
121 + regulator-max-microvolt = <5000000>;
123 + regulator-always-on;
127 + compatible = "gpio-keys";
128 + pinctrl-names = "default";
129 + pinctrl-0 = <&key_pins_a>;
133 + linux,code = <KEY_RESTART>;
134 + gpios = <&pio 256 GPIO_ACTIVE_LOW>;
139 + compatible = "gpio-leds";
140 + pinctrl-names = "default";
141 + pinctrl-0 = <&led_pins_unielec>;
144 + label = "u7623-01:green:led3";
145 + gpios = <&pio 14 GPIO_ACTIVE_LOW>;
146 + default-state = "off";
150 + label = "u7623-01:green:led4";
151 + gpios = <&pio 15 GPIO_ACTIVE_LOW>;
152 + default-state = "off";
157 + device_type = "memory";
158 + reg = <0 0x80000000 0 0x40000000>;
162 + compatible = "mediatek,mt7530";
163 + #address-cells = <1>;
176 + compatible = "mediatek,eth-mac";
178 + phy-mode = "trgmii";
188 + #address-cells = <1>;
190 + phy5: ethernet-phy@5 {
192 + phy-mode = "rgmii-rxid";
198 + compatible = "mediatek,mt7530";
199 + #address-cells = <1>;
202 + pinctrl-names = "default";
204 + resets = <ðsys 2>;
205 + reset-names = "mcm";
206 + core-supply = <&mt6323_vpa_reg>;
207 + io-supply = <&mt6323_vemc3v3_reg>;
209 + dsa,mii-bus = <&mdio>;
212 + #address-cells = <1>;
219 + cpu = <&cpu_port0>;
225 + cpu = <&cpu_port0>;
231 + cpu = <&cpu_port0>;
237 + cpu = <&cpu_port0>;
243 + cpu = <&cpu_port0>;
246 + cpu_port0: port@6 {
249 + ethernet = <&gmac0>;
250 + phy-mode = "trgmii";
261 + pinctrl-names = "default", "state_uhs";
262 + pinctrl-0 = <&mmc0_pins_default>;
263 + pinctrl-1 = <&mmc0_pins_uhs>;
266 + max-frequency = <50000000>;
268 + vmmc-supply = <®_3p3v>;
269 + vqmmc-supply = <®_1p8v>;
274 + key_pins_a: keys-alt {
276 + pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
277 + <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
282 + led_pins_unielec: leds-unielec {
284 + pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
285 + <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
289 + mmc0_pins_default: mmc0default {
291 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
292 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
293 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
294 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
295 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
296 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
297 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
298 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
299 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
305 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
310 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
315 + mmc0_pins_uhs: mmc0 {
317 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
318 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
319 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
320 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
321 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
322 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
323 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
324 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
325 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
327 + drive-strength = <MTK_DRIVE_2mA>;
328 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
332 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
333 + drive-strength = <MTK_DRIVE_2mA>;
334 + bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
338 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
343 + pwm_pins_a: pwm@0 {
345 + pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
346 + <MT7623_PIN_204_PWM1_FUNC_PWM1>,
347 + <MT7623_PIN_205_PWM2_FUNC_PWM2>,
348 + <MT7623_PIN_206_PWM3_FUNC_PWM3>,
349 + <MT7623_PIN_207_PWM4_FUNC_PWM4>;
353 + uart2_pins_b: uart@2 {
355 + pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
356 + <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
360 + pcie_default: pcie_pin_default {
362 + pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
363 + <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
370 + pinctrl-names = "default";
371 + pinctrl-0 = <&pwm_pins_a>;
378 + compatible = "mediatek,mt6323-led";
379 + #address-cells = <1>;
385 + default-state = "off";
392 + pinctrl-names = "default";
393 + pinctrl-0 = <&uart2_pins_b>;
398 + vusb33-supply = <®_3p3v>;
399 + vbus-supply = <®_3p3v>;
409 + mediatek,phy-switch = <&hifsys>;
413 + pinctrl-names = "default";
414 + pinctrl-0 = <&pcie_default>;