1 From 51d5ca9e151eb323bd965e72ad1e1dc93fcf7b13 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 5 Jan 2016 12:16:17 +0100
4 Subject: [PATCH 023/102] ARM: dts: mediatek: add MT7623 basic support
6 This adds basic chip support for Mediatek MT7623.
8 Signed-off-by: John Crispin <blogic@openwrt.org>
10 arch/arm/boot/dts/Makefile | 1 +
11 arch/arm/boot/dts/mt7623-evb.dts | 421 ++++++++++++++++++++++++++
12 arch/arm/boot/dts/mt7623.dtsi | 601 +++++++++++++++++++++++++++++++++++++
13 arch/arm/mach-mediatek/Kconfig | 4 +
14 arch/arm/mach-mediatek/mediatek.c | 1 +
15 5 files changed, 1028 insertions(+)
16 create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
17 create mode 100644 arch/arm/boot/dts/mt7623.dtsi
19 --- a/arch/arm/boot/dts/Makefile
20 +++ b/arch/arm/boot/dts/Makefile
21 @@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
28 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
30 +++ b/arch/arm/boot/dts/mt7623-evb.dts
33 + * Copyright (c) 2016 MediaTek Inc.
34 + * Author: John Crispin <blogic@openwrt.org>
36 + * This program is free software; you can redistribute it and/or modify
37 + * it under the terms of the GNU General Public License version 2 as
38 + * published by the Free Software Foundation.
40 + * This program is distributed in the hope that it will be useful,
41 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
42 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43 + * GNU General Public License for more details.
48 +#include "mt7623.dtsi"
49 +#include <dt-bindings/gpio/gpio.h>
52 + model = "MediaTek MT7623 evaluation board";
53 + compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
56 + stdout-path = &uart2;
60 + reg = <0 0x80000000 0 0x20000000>;
63 + usb_p1_vbus: regulator@0 {
64 + compatible = "regulator-fixed";
65 + regulator-name = "usb_vbus";
66 + regulator-min-microvolt = <5000000>;
67 + regulator-max-microvolt = <5000000>;
68 + gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
74 + proc-supply = <&mt6323_vproc_reg>;
78 + proc-supply = <&mt6323_vproc_reg>;
82 + proc-supply = <&mt6323_vproc_reg>;
86 + proc-supply = <&mt6323_vproc_reg>;
91 + compatible = "mediatek,mt6323";
92 + interrupt-parent = <&pio>;
93 + interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
94 + interrupt-controller;
95 + #interrupt-cells = <2>;
97 + mt6323regulator: mt6323regulator{
98 + compatible = "mediatek,mt6323-regulator";
100 + mt6323_vproc_reg: buck_vproc{
101 + regulator-name = "vproc";
102 + regulator-min-microvolt = < 700000>;
103 + regulator-max-microvolt = <1350000>;
104 + regulator-ramp-delay = <12500>;
105 + regulator-always-on;
109 + mt6323_vsys_reg: buck_vsys{
110 + regulator-name = "vsys";
111 + regulator-min-microvolt = <1400000>;
112 + regulator-max-microvolt = <2987500>;
113 + regulator-ramp-delay = <25000>;
114 + regulator-always-on;
118 + mt6323_vpa_reg: buck_vpa{
119 + regulator-name = "vpa";
120 + regulator-min-microvolt = < 500000>;
121 + regulator-max-microvolt = <3650000>;
124 + mt6323_vtcxo_reg: ldo_vtcxo{
125 + regulator-name = "vtcxo";
126 + regulator-min-microvolt = <2800000>;
127 + regulator-max-microvolt = <2800000>;
128 + regulator-enable-ramp-delay = <90>;
129 + regulator-always-on;
133 + mt6323_vcn28_reg: ldo_vcn28{
134 + regulator-name = "vcn28";
135 + regulator-min-microvolt = <2800000>;
136 + regulator-max-microvolt = <2800000>;
137 + regulator-enable-ramp-delay = <185>;
140 + mt6323_vcn33_bt_reg: ldo_vcn33_bt{
141 + regulator-name = "vcn33_bt";
142 + regulator-min-microvolt = <3300000>;
143 + regulator-max-microvolt = <3600000>;
144 + regulator-enable-ramp-delay = <185>;
147 + mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
148 + regulator-name = "vcn33_wifi";
149 + regulator-min-microvolt = <3300000>;
150 + regulator-max-microvolt = <3600000>;
151 + regulator-enable-ramp-delay = <185>;
154 + mt6323_va_reg: ldo_va{
155 + regulator-name = "va";
156 + regulator-min-microvolt = <2800000>;
157 + regulator-max-microvolt = <2800000>;
158 + regulator-enable-ramp-delay = <216>;
159 + regulator-always-on;
163 + mt6323_vcama_reg: ldo_vcama{
164 + regulator-name = "vcama";
165 + regulator-min-microvolt = <1500000>;
166 + regulator-max-microvolt = <2800000>;
167 + regulator-enable-ramp-delay = <216>;
170 + mt6323_vio28_reg: ldo_vio28{
171 + regulator-name = "vio28";
172 + regulator-min-microvolt = <2800000>;
173 + regulator-max-microvolt = <2800000>;
174 + regulator-enable-ramp-delay = <216>;
175 + regulator-always-on;
179 + mt6323_vusb_reg: ldo_vusb{
180 + regulator-name = "vusb";
181 + regulator-min-microvolt = <3300000>;
182 + regulator-max-microvolt = <3300000>;
183 + regulator-enable-ramp-delay = <216>;
187 + mt6323_vmc_reg: ldo_vmc{
188 + regulator-name = "vmc";
189 + regulator-min-microvolt = <1800000>;
190 + regulator-max-microvolt = <3300000>;
191 + regulator-enable-ramp-delay = <36>;
195 + mt6323_vmch_reg: ldo_vmch{
196 + regulator-name = "vmch";
197 + regulator-min-microvolt = <3000000>;
198 + regulator-max-microvolt = <3300000>;
199 + regulator-enable-ramp-delay = <36>;
203 + mt6323_vemc3v3_reg: ldo_vemc3v3{
204 + regulator-name = "vemc3v3";
205 + regulator-min-microvolt = <3000000>;
206 + regulator-max-microvolt = <3300000>;
207 + regulator-enable-ramp-delay = <36>;
211 + mt6323_vgp1_reg: ldo_vgp1{
212 + regulator-name = "vgp1";
213 + regulator-min-microvolt = <1200000>;
214 + regulator-max-microvolt = <3300000>;
215 + regulator-enable-ramp-delay = <216>;
218 + mt6323_vgp2_reg: ldo_vgp2{
219 + regulator-name = "vgp2";
220 + regulator-min-microvolt = <1200000>;
221 + regulator-max-microvolt = <3000000>;
222 + regulator-enable-ramp-delay = <216>;
225 + mt6323_vgp3_reg: ldo_vgp3{
226 + regulator-name = "vgp3";
227 + regulator-min-microvolt = <1200000>;
228 + regulator-max-microvolt = <1800000>;
229 + regulator-enable-ramp-delay = <216>;
232 + mt6323_vcn18_reg: ldo_vcn18{
233 + regulator-name = "vcn18";
234 + regulator-min-microvolt = <1800000>;
235 + regulator-max-microvolt = <1800000>;
236 + regulator-enable-ramp-delay = <216>;
239 + mt6323_vsim1_reg: ldo_vsim1{
240 + regulator-name = "vsim1";
241 + regulator-min-microvolt = <1800000>;
242 + regulator-max-microvolt = <3000000>;
243 + regulator-enable-ramp-delay = <216>;
246 + mt6323_vsim2_reg: ldo_vsim2{
247 + regulator-name = "vsim2";
248 + regulator-min-microvolt = <1800000>;
249 + regulator-max-microvolt = <3000000>;
250 + regulator-enable-ramp-delay = <216>;
253 + mt6323_vrtc_reg: ldo_vrtc{
254 + regulator-name = "vrtc";
255 + regulator-min-microvolt = <2800000>;
256 + regulator-max-microvolt = <2800000>;
257 + regulator-always-on;
261 + mt6323_vcamaf_reg: ldo_vcamaf{
262 + regulator-name = "vcamaf";
263 + regulator-min-microvolt = <1200000>;
264 + regulator-max-microvolt = <3300000>;
265 + regulator-enable-ramp-delay = <216>;
268 + mt6323_vibr_reg: ldo_vibr{
269 + regulator-name = "vibr";
270 + regulator-min-microvolt = <1200000>;
271 + regulator-max-microvolt = <3300000>;
272 + regulator-enable-ramp-delay = <36>;
275 + mt6323_vrf18_reg: ldo_vrf18{
276 + regulator-name = "vrf18";
277 + regulator-min-microvolt = <1825000>;
278 + regulator-max-microvolt = <1825000>;
279 + regulator-enable-ramp-delay = <187>;
282 + mt6323_vm_reg: ldo_vm{
283 + regulator-name = "vm";
284 + regulator-min-microvolt = <1200000>;
285 + regulator-max-microvolt = <1800000>;
286 + regulator-enable-ramp-delay = <216>;
287 + regulator-always-on;
291 + mt6323_vio18_reg: ldo_vio18{
292 + regulator-name = "vio18";
293 + regulator-min-microvolt = <1800000>;
294 + regulator-max-microvolt = <1800000>;
295 + regulator-enable-ramp-delay = <216>;
296 + regulator-always-on;
300 + mt6323_vcamd_reg: ldo_vcamd{
301 + regulator-name = "vcamd";
302 + regulator-min-microvolt = <1200000>;
303 + regulator-max-microvolt = <1800000>;
304 + regulator-enable-ramp-delay = <216>;
307 + mt6323_vcamio_reg: ldo_vcamio{
308 + regulator-name = "vcamio";
309 + regulator-min-microvolt = <1800000>;
310 + regulator-max-microvolt = <1800000>;
311 + regulator-enable-ramp-delay = <216>;
322 + nand_pins_default: nanddefault {
324 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
325 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
326 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
327 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
328 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
329 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
330 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
331 + <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
332 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
334 + drive-strength = <MTK_DRIVE_8mA>;
339 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
340 + drive-strength = <MTK_DRIVE_8mA>;
341 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
345 + pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
346 + drive-strength = <MTK_DRIVE_8mA>;
347 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
353 + pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
354 + <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
355 + <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
356 + <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
357 + <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
358 + <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
359 + <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
360 + <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
361 + <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
362 + <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
363 + <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
364 + <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
365 + <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
366 + <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>,
367 + <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
371 + pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
379 + pinctrl-names = "default";
380 + pinctrl-0 = <&nand_pins_default>;
384 + compatible = "fixed-partitions";
385 + #address-cells = <1>;
389 + label = "uboot-env";
390 + reg = <0xC0000 0x40000>;
395 + reg = <0x100000 0x40000>;
400 + reg = <0x140000 0x2000000>;
403 + partition@2140000 {
404 + label = "recovery";
405 + reg = <0x2140000 0x2000000>;
408 + partition@4140000 {
410 + reg = <0x4140000 0x1000000>;
420 + vusb33-supply = <&mt6323_vusb_reg>;
421 + vbus-supply = <&usb_p1_vbus>;
438 + mac-address = [00 11 22 33 44 56];
443 + mac-address = [00 11 22 33 44 55];
448 + pinctrl-names = "default";
449 + pinctrl-0 = <ð_default>;
450 + mediatek,reset-pin = <&pio 15 0>;
454 +++ b/arch/arm/boot/dts/mt7623.dtsi
457 + * Copyright (c) 2016 MediaTek Inc.
458 + * Author: John Crispin <blogic@openwrt.org>
460 + * This program is free software; you can redistribute it and/or modify
461 + * it under the terms of the GNU General Public License version 2 as
462 + * published by the Free Software Foundation.
464 + * This program is distributed in the hope that it will be useful,
465 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
466 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
467 + * GNU General Public License for more details.
470 +#include <dt-bindings/interrupt-controller/irq.h>
471 +#include <dt-bindings/interrupt-controller/arm-gic.h>
472 +#include <dt-bindings/clock/mt2701-clk.h>
473 +#include <dt-bindings/power/mt2701-power.h>
474 +#include <dt-bindings/phy/phy.h>
475 +#include <dt-bindings/reset-controller/mt2701-resets.h>
476 +#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
477 +#include "skeleton64.dtsi"
481 + compatible = "mediatek,mt7623";
482 + interrupt-parent = <&sysirq>;
485 + #address-cells = <1>;
487 + enable-method = "mediatek,mt6589-smp";
490 + device_type = "cpu";
491 + compatible = "arm,cortex-a7";
493 + clocks = <&infracfg CLK_INFRA_CPUSEL>,
494 + <&apmixedsys CLK_APMIXED_MAINPLL>;
495 + clock-names = "cpu", "intermediate";
496 + operating-points = <
505 + device_type = "cpu";
506 + compatible = "arm,cortex-a7";
508 + clocks = <&infracfg CLK_INFRA_CPUSEL>,
509 + <&apmixedsys CLK_APMIXED_MAINPLL>;
510 + clock-names = "cpu", "intermediate";
511 + operating-points = <
520 + device_type = "cpu";
521 + compatible = "arm,cortex-a7";
523 + clocks = <&infracfg CLK_INFRA_CPUSEL>,
524 + <&apmixedsys CLK_APMIXED_MAINPLL>;
525 + clock-names = "cpu", "intermediate";
526 + operating-points = <
535 + device_type = "cpu";
536 + compatible = "arm,cortex-a7";
538 + clocks = <&infracfg CLK_INFRA_CPUSEL>,
539 + <&apmixedsys CLK_APMIXED_MAINPLL>;
540 + clock-names = "cpu", "intermediate";
541 + operating-points = <
551 + system_clk: dummy13m {
552 + compatible = "fixed-clock";
553 + clock-frequency = <13000000>;
554 + #clock-cells = <0>;
557 + rtc_clk: dummy32k {
558 + compatible = "fixed-clock";
559 + clock-frequency = <32000>;
560 + #clock-cells = <0>;
561 + clock-output-names = "clk32k";
565 + compatible = "fixed-clock";
566 + clock-frequency = <26000000>;
567 + #clock-cells = <0>;
568 + clock-output-names = "clk26m";
572 + compatible = "arm,armv7-timer";
573 + interrupt-parent = <&gic>;
574 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
575 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
576 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
577 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
578 + clock-frequency = <13000000>;
579 + arm,cpu-registers-not-fw-configured;
582 + topckgen: power-controller@10000000 {
583 + compatible = "mediatek,mt7623-topckgen",
584 + "mediatek,mt2701-topckgen",
586 + reg = <0 0x10000000 0 0x1000>;
587 + #clock-cells = <1>;
590 + infracfg: power-controller@10001000 {
591 + compatible = "mediatek,mt7623-infracfg",
592 + "mediatek,mt2701-infracfg",
594 + reg = <0 0x10001000 0 0x1000>;
595 + #clock-cells = <1>;
596 + #reset-cells = <1>;
599 + pericfg: pericfg@10003000 {
600 + compatible = "mediatek,mt7623-pericfg",
601 + "mediatek,mt2701-pericfg",
603 + reg = <0 0x10003000 0 0x1000>;
604 + #clock-cells = <1>;
605 + #reset-cells = <1>;
608 + pio: pinctrl@10005000 {
609 + compatible = "mediatek,mt7623-pinctrl";
610 + reg = <0 0x1000b000 0 0x1000>;
611 + mediatek,pctl-regmap = <&syscfg_pctl_a>;
615 + interrupt-controller;
616 + interrupt-parent = <&gic>;
617 + #interrupt-cells = <2>;
618 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
619 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
622 + syscfg_pctl_a: syscfg@10005000 {
623 + compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
624 + reg = <0 0x10005000 0 0x1000>;
627 + scpsys: scpsys@10006000 {
628 + #power-domain-cells = <1>;
629 + compatible = "mediatek,mt7623-scpsys",
630 + "mediatek,mt2701-scpsys";
631 + reg = <0 0x10006000 0 0x1000>;
632 + infracfg = <&infracfg>;
633 + clocks = <&clk26m>,
634 + <&topckgen CLK_TOP_MM_SEL>;
635 + clock-names = "mfg", "mm";
638 + watchdog: watchdog@10007000 {
639 + compatible = "mediatek,mt7623-wdt",
640 + "mediatek,mt6589-wdt";
641 + reg = <0 0x10007000 0 0x100>;
644 + timer: timer@10008000 {
645 + compatible = "mediatek,mt7623-timer",
646 + "mediatek,mt6577-timer";
647 + reg = <0 0x10008000 0 0x80>;
648 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
649 + clocks = <&system_clk>, <&rtc_clk>;
650 + clock-names = "system-clk", "rtc-clk";
653 + pwrap: pwrap@1000d000 {
654 + compatible = "mediatek,mt7623-pwrap",
655 + "mediatek,mt2701-pwrap";
656 + reg = <0 0x1000d000 0 0x1000>;
657 + reg-names = "pwrap";
658 + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
659 + resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
660 + reset-names = "pwrap";
661 + clocks = <&infracfg CLK_INFRA_PMICSPI>,
662 + <&infracfg CLK_INFRA_PMICWRAP>;
663 + clock-names = "spi", "wrap";
666 + sysirq: interrupt-controller@10200100 {
667 + compatible = "mediatek,mt7623-sysirq",
668 + "mediatek,mt6577-sysirq";
669 + interrupt-controller;
670 + #interrupt-cells = <3>;
671 + interrupt-parent = <&gic>;
672 + reg = <0 0x10200100 0 0x1c>;
675 + apmixedsys: apmixedsys@10209000 {
676 + compatible = "mediatek,mt7623-apmixedsys",
677 + "mediatek,mt2701-apmixedsys";
678 + reg = <0 0x10209000 0 0x1000>;
679 + #clock-cells = <1>;
682 + gic: interrupt-controller@10211000 {
683 + compatible = "arm,cortex-a7-gic";
684 + interrupt-controller;
685 + #interrupt-cells = <3>;
686 + interrupt-parent = <&gic>;
687 + reg = <0 0x10211000 0 0x1000>,
688 + <0 0x10212000 0 0x1000>,
689 + <0 0x10214000 0 0x2000>,
690 + <0 0x10216000 0 0x2000>;
693 + i2c0: i2c@11007000 {
694 + compatible = "mediatek,mt7623-i2c",
695 + "mediatek,mt6577-i2c";
696 + reg = <0 0x11007000 0 0x70>,
697 + <0 0x11000200 0 0x80>;
698 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
700 + clocks = <&pericfg CLK_PERI_I2C0>,
701 + <&pericfg CLK_PERI_AP_DMA>;
702 + clock-names = "main", "dma";
703 + #address-cells = <1>;
705 + status = "disabled";
708 + i2c1: i2c@11008000 {
709 + compatible = "mediatek,mt7623-i2c",
710 + "mediatek,mt6577-i2c";
711 + reg = <0 0x11008000 0 0x70>,
712 + <0 0x11000280 0 0x80>;
713 + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
715 + clocks = <&pericfg CLK_PERI_I2C1>,
716 + <&pericfg CLK_PERI_AP_DMA>;
717 + clock-names = "main", "dma";
718 + #address-cells = <1>;
720 + status = "disabled";
723 + i2c2: i2c@11009000 {
724 + compatible = "mediatek,mt7623-i2c",
725 + "mediatek,mt6577-i2c";
726 + reg = <0 0x11009000 0 0x70>,
727 + <0 0x11000300 0 0x80>;
728 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
730 + clocks = <&pericfg CLK_PERI_I2C2>,
731 + <&pericfg CLK_PERI_AP_DMA>;
732 + clock-names = "main", "dma";
733 + #address-cells = <1>;
735 + status = "disabled";
738 + uart0: serial@11002000 {
739 + compatible = "mediatek,mt7623-uart",
740 + "mediatek,mt6577-uart";
741 + reg = <0 0x11002000 0 0x400>;
742 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
743 + clocks = <&pericfg CLK_PERI_UART0_SEL>,
744 + <&pericfg CLK_PERI_UART0>;
745 + clock-names = "baud", "bus";
746 + status = "disabled";
749 + uart1: serial@11003000 {
750 + compatible = "mediatek,mt7623-uart",
751 + "mediatek,mt6577-uart";
752 + reg = <0 0x11003000 0 0x400>;
753 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
754 + clocks = <&pericfg CLK_PERI_UART1_SEL>,
755 + <&pericfg CLK_PERI_UART1>;
756 + clock-names = "baud", "bus";
757 + status = "disabled";
760 + uart2: serial@11004000 {
761 + compatible = "mediatek,mt7623-uart",
762 + "mediatek,mt6577-uart";
763 + reg = <0 0x11004000 0 0x400>;
764 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
765 + clocks = <&pericfg CLK_PERI_UART2_SEL>,
766 + <&pericfg CLK_PERI_UART2>;
767 + clock-names = "baud", "bus";
768 + status = "disabled";
771 + uart3: serial@11005000 {
772 + compatible = "mediatek,mt7623-uart",
773 + "mediatek,mt6577-uart";
774 + reg = <0 0x11005000 0 0x400>;
775 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
776 + clocks = <&pericfg CLK_PERI_UART3_SEL>,
777 + <&pericfg CLK_PERI_UART3>;
778 + clock-names = "baud", "bus";
779 + status = "disabled";
782 + spi: spi@1100a000 {
783 + compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
784 + reg = <0 0x1100a000 0 0x1000>;
785 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
786 + clocks = <&pericfg CLK_PERI_SPI0>;
787 + clock-names = "main";
789 + status = "disabled";
792 + nandc: nfi@1100d000 {
793 + compatible = "mediatek,mt2701-nfc";
794 + reg = <0 0x1100d000 0 0x1000>;
795 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
796 + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
797 + clocks = <&pericfg CLK_PERI_NFI>,
798 + <&pericfg CLK_PERI_NFI_PAD>;
799 + clock-names = "nfi_clk", "pad_clk";
800 + status = "disabled";
801 + ecc-engine = <&bch>;
802 + #address-cells = <1>;
806 + bch: ecc@1100e000 {
807 + compatible = "mediatek,mt2701-ecc";
808 + reg = <0 0x1100e000 0 0x1000>;
809 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
810 + clocks = <&pericfg CLK_PERI_NFI_ECC>;
811 + clock-names = "nfiecc_clk";
812 + status = "disabled";
815 + mmc0: mmc@11230000 {
816 + compatible = "mediatek,mt7623-mmc",
817 + "mediatek,mt8135-mmc";
818 + reg = <0 0x11230000 0 0x1000>;
819 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
820 + clocks = <&pericfg CLK_PERI_MSDC30_0>,
821 + <&topckgen CLK_TOP_MSDC30_0_SEL>;
822 + clock-names = "source", "hclk";
823 + status = "disabled";
826 + mmc1: mmc@11240000 {
827 + compatible = "mediatek,mt7623-mmc",
828 + "mediatek,mt8135-mmc";
829 + reg = <0 0x11240000 0 0x1000>;
830 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
831 + clocks = <&pericfg CLK_PERI_MSDC30_1>,
832 + <&topckgen CLK_TOP_MSDC30_1_SEL>;
833 + clock-names = "source", "hclk";
834 + status = "disabled";
837 + usb1: usb@1a1c0000 {
838 + compatible = "mediatek,mt2701-xhci",
839 + "mediatek,mt8173-xhci";
840 + reg = <0 0x1a1c0000 0 0x1000>,
841 + <0 0x1a1c4700 0 0x0100>;
842 + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
843 + clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
844 + <&topckgen CLK_TOP_ETHIF_SEL>;
845 + clock-names = "sys_ck", "ethif";
846 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
847 + phys = <&phy_port0 PHY_TYPE_USB3>;
848 + status = "disabled";
851 + u3phy1: usb-phy@1a1c4000 {
852 + compatible = "mediatek,mt2701-u3phy",
853 + "mediatek,mt8173-u3phy";
854 + reg = <0 0x1a1c4000 0 0x0700>;
855 + clocks = <&clk26m>;
856 + clock-names = "u3phya_ref";
858 + #address-cells = <2>;
861 + status = "disabled";
863 + phy_port0: phy_port0: port@1a1c4800 {
864 + reg = <0 0x1a1c4800 0 0x800>;
870 + usb2: usb@1a240000 {
871 + compatible = "mediatek,mt2701-xhci",
872 + "mediatek,mt8173-xhci";
873 + reg = <0 0x1a240000 0 0x1000>,
874 + <0 0x1a244700 0 0x0100>;
875 + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
876 + clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
877 + <&topckgen CLK_TOP_ETHIF_SEL>;
878 + clock-names = "sys_ck", "ethif";
879 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
880 + phys = <&u3phy2 0>;
881 + status = "disabled";
884 + u3phy2: usb-phy@1a244000 {
885 + compatible = "mediatek,mt2701-u3phy",
886 + "mediatek,mt8173-u3phy";
887 + reg = <0 0x1a244000 0 0x0700>,
888 + <0 0x1a244800 0 0x0800>;
889 + clocks = <&clk26m>;
890 + clock-names = "u3phya_ref";
892 + status = "disabled";
895 + hifsys: clock-controller@1a000000 {
896 + compatible = "mediatek,mt7623-hifsys",
897 + "mediatek,mt2701-hifsys",
899 + reg = <0 0x1a000000 0 0x1000>;
900 + #clock-cells = <1>;
901 + #reset-cells = <1>;
904 + pcie: pcie@1a140000 {
905 + compatible = "mediatek,mt7623-pcie";
906 + device_type = "pci";
907 + reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
908 + <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
909 + <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
910 + <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
911 + reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
912 + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
913 + <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
914 + <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
915 + interrupt-names = "pcie0", "pcie1", "pcie2";
916 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
917 + clock-names = "pcie";
918 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
919 + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
920 + <&hifsys MT2701_HIFSYS_PCIE1_RST>,
921 + <&hifsys MT2701_HIFSYS_PCIE2_RST>;
922 + reset-names = "pcie0", "pcie1", "pcie2";
924 + mediatek,hifsys = <&hifsys>;
926 + bus-range = <0x00 0xff>;
927 + #address-cells = <3>;
930 + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
931 + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
933 + status = "disabled";
936 + device_type = "pci";
937 + reg = <0x0800 0 0 0 0>;
939 + #address-cells = <3>;
945 + device_type = "pci";
946 + reg = <0x1000 0 0 0 0>;
948 + #address-cells = <3>;
954 + device_type = "pci";
955 + reg = <0x1800 0 0 0 0>;
957 + #address-cells = <3>;
963 + ethsys: syscon@1b000000 {
964 + compatible = "mediatek,mt2701-ethsys", "syscon";
965 + reg = <0 0x1b000000 0 0x1000>;
966 + #reset-cells = <1>;
967 + #clock-cells = <1>;
970 + eth: ethernet@1b100000 {
971 + compatible = "mediatek,mt7623-eth";
972 + reg = <0 0x1b100000 0 0x20000>;
974 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
975 + <ðsys CLK_ETHSYS_ESW>,
976 + <ðsys CLK_ETHSYS_GP2>,
977 + <ðsys CLK_ETHSYS_GP1>;
978 + clock-names = "ethif", "esw", "gp2", "gp1";
979 + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
980 + GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
981 + GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
982 + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
984 + resets = <ðsys 6>;
985 + reset-names = "eth";
987 + mediatek,ethsys = <ðsys>;
988 + mediatek,pctl = <&syscfg_pctl_a>;
990 + mediatek,switch = <&gsw>;
992 + #address-cells = <1>;
995 + status = "disabled";
998 + compatible = "mediatek,eth-mac";
1001 + status = "disabled";
1003 + phy-mode = "rgmii";
1013 + compatible = "mediatek,eth-mac";
1016 + status = "disabled";
1018 + phy-mode = "rgmii";
1028 + #address-cells = <1>;
1029 + #size-cells = <0>;
1031 + phy5: ethernet-phy@5 {
1033 + phy-mode = "rgmii-rxid";
1036 + phy1f: ethernet-phy@1f {
1038 + phy-mode = "rgmii";
1043 + gsw: switch@1b100000 {
1044 + compatible = "mediatek,mt7623-gsw";
1045 + interrupt-parent = <&pio>;
1046 + interrupts = <168 IRQ_TYPE_EDGE_RISING>;
1047 + resets = <ðsys 2>;
1048 + reset-names = "eth";
1049 + clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
1050 + clock-names = "trgpll";
1051 + mt7530-supply = <&mt6323_vpa_reg>;
1052 + mediatek,pctl-regmap = <&syscfg_pctl_a>;
1053 + mediatek,ethsys = <ðsys>;
1054 + status = "disabled";
1057 --- a/arch/arm/mach-mediatek/Kconfig
1058 +++ b/arch/arm/mach-mediatek/Kconfig
1059 @@ -21,6 +21,10 @@ config MACH_MT6592
1060 bool "MediaTek MT6592 SoCs support"
1061 default ARCH_MEDIATEK
1064 + bool "MediaTek MT7623 SoCs support"
1065 + default ARCH_MEDIATEK
1068 bool "MediaTek MT8127 SoCs support"
1069 default ARCH_MEDIATEK
1070 --- a/arch/arm/mach-mediatek/mediatek.c
1071 +++ b/arch/arm/mach-mediatek/mediatek.c
1072 @@ -46,6 +46,7 @@ static void __init mediatek_timer_init(v
1073 static const char * const mediatek_board_dt_compat[] = {
1076 + "mediatek,mt7623",