1 From 242801fc94db9ceb1e3e2a8b19fb2c57122e53f3 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 21 Mar 2016 16:36:22 +0100
4 Subject: [PATCH] net: out of tree fixes
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/arm/boot/dts/mt7623-evb.dts | 1 -
9 arch/arm/boot/dts/mt7623.dtsi | 40 +-
10 drivers/net/ethernet/mediatek/Makefile | 2 +-
11 drivers/net/ethernet/mediatek/gsw_mt7620.h | 250 +++++++
12 drivers/net/ethernet/mediatek/gsw_mt7623.c | 966 +++++++++++++++++++++++++++
13 drivers/net/ethernet/mediatek/mt7530.c | 808 ++++++++++++++++++++++
14 drivers/net/ethernet/mediatek/mt7530.h | 20 +
15 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 59 +-
16 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 +
17 lib/dynamic_queue_limits.c | 6 +-
18 10 files changed, 2110 insertions(+), 47 deletions(-)
19 create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7620.h
20 create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7623.c
21 create mode 100644 drivers/net/ethernet/mediatek/mt7530.c
22 create mode 100644 drivers/net/ethernet/mediatek/mt7530.h
24 diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
25 index 5e9381d..bc2b3f1 100644
26 --- a/arch/arm/boot/dts/mt7623-evb.dts
27 +++ b/arch/arm/boot/dts/mt7623-evb.dts
30 vusb33-supply = <&mt6323_vusb_reg>;
31 vbus-supply = <&usb_p1_vbus>;
32 -// mediatek,wakeup-src = <1>;
36 diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
37 index 1ba7790..5926e14 100644
38 --- a/arch/arm/boot/dts/mt7623.dtsi
39 +++ b/arch/arm/boot/dts/mt7623.dtsi
43 ethsys: syscon@1b000000 {
44 - #address-cells = <1>;
46 compatible = "mediatek,mt2701-ethsys", "syscon";
47 reg = <0 0x1b000000 0 0x1000>;
52 eth: ethernet@1b100000 {
53 compatible = "mediatek,mt7623-eth";
54 - reg = <0 0x1b100000 0 0x10000>;
55 + reg = <0 0x1b100000 0 0x20000>;
57 - clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
58 - clock-names = "ethif";
59 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
60 + <ðsys CLK_ETHSYS_ESW>,
61 + <ðsys CLK_ETHSYS_GP2>,
62 + <ðsys CLK_ETHSYS_GP1>;
63 + clock-names = "ethif", "esw", "gp2", "gp1";
64 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
65 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
67 + resets = <ðsys 6>;
68 + reset-names = "eth";
70 mediatek,ethsys = <ðsys>;
71 + mediatek,pctl = <&syscfg_pctl_a>;
73 mediatek,switch = <&gsw>;
77 compatible = "mediatek,eth-mac";
80 + phy-handle = <&phy4>;
86 compatible = "mediatek,eth-mac";
89 + phy-handle = <&phy5>;
97 + phy4: ethernet-phy@4 {
102 + phy5: ethernet-phy@5 {
104 + phy-mode = "rgmii";
107 phy1f: ethernet-phy@1f {
110 @@ -491,14 +511,12 @@
112 gsw: switch@1b100000 {
113 compatible = "mediatek,mt7623-gsw";
114 - reg = <0 0x1b110000 0 0x300000>;
115 interrupt-parent = <&pio>;
116 interrupts = <168 IRQ_TYPE_EDGE_RISING>;
117 - clocks = <&apmixedsys CLK_APMIXED_TRGPLL>,
118 - <ðsys CLK_ETHSYS_ESW>,
119 - <ðsys CLK_ETHSYS_GP2>,
120 - <ðsys CLK_ETHSYS_GP1>;
121 - clock-names = "trgpll", "esw", "gp2", "gp1";
122 + resets = <ðsys 2>;
123 + reset-names = "eth";
124 + clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
125 + clock-names = "trgpll";
126 mt7530-supply = <&mt6323_vpa_reg>;
127 mediatek,pctl-regmap = <&syscfg_pctl_a>;
128 mediatek,ethsys = <ðsys>;
129 diff --git a/drivers/net/ethernet/mediatek/Makefile b/drivers/net/ethernet/mediatek/Makefile
130 index aa3f1c8..82001c4 100644
131 --- a/drivers/net/ethernet/mediatek/Makefile
132 +++ b/drivers/net/ethernet/mediatek/Makefile
134 # Makefile for the Mediatek SoCs built-in ethernet macs
137 -obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth_soc.o
138 +obj-$(CONFIG_NET_MEDIATEK_SOC) += mt7530.o gsw_mt7623.o mtk_eth_soc.o
139 diff --git a/drivers/net/ethernet/mediatek/gsw_mt7620.h b/drivers/net/ethernet/mediatek/gsw_mt7620.h
141 index 0000000..7013803
143 +++ b/drivers/net/ethernet/mediatek/gsw_mt7620.h
145 +/* This program is free software; you can redistribute it and/or modify
146 + * it under the terms of the GNU General Public License as published by
147 + * the Free Software Foundation; version 2 of the License
149 + * This program is distributed in the hope that it will be useful,
150 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
151 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
152 + * GNU General Public License for more details.
154 + * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
155 + * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
156 + * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
159 +#ifndef _RALINK_GSW_MT7620_H__
160 +#define _RALINK_GSW_MT7620_H__
162 +#define GSW_REG_PHY_TIMEOUT (5 * HZ)
164 +#define MT7620_GSW_REG_PIAC 0x0004
166 +#define GSW_NUM_VLANS 16
167 +#define GSW_NUM_VIDS 4096
168 +#define GSW_NUM_PORTS 7
171 +#define GSW_MDIO_ACCESS BIT(31)
172 +#define GSW_MDIO_READ BIT(19)
173 +#define GSW_MDIO_WRITE BIT(18)
174 +#define GSW_MDIO_START BIT(16)
175 +#define GSW_MDIO_ADDR_SHIFT 20
176 +#define GSW_MDIO_REG_SHIFT 25
178 +#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
179 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
180 +#define GSW_REG_SMACCR0 0x3fE4
181 +#define GSW_REG_SMACCR1 0x3fE8
182 +#define GSW_REG_CKGCR 0x3ff0
184 +#define GSW_REG_IMR 0x7008
185 +#define GSW_REG_ISR 0x700c
186 +#define GSW_REG_GPC1 0x7014
188 +#define SYSC_REG_CHIP_REV_ID 0x0c
189 +#define SYSC_REG_CFG 0x10
190 +#define SYSC_REG_CFG1 0x14
191 +#define RST_CTRL_MCM BIT(2)
192 +#define SYSC_PAD_RGMII2_MDIO 0x58
193 +#define SYSC_GPIO_MODE 0x60
195 +#define PORT_IRQ_ST_CHG 0x7f
197 +#define MT7621_ESW_PHY_POLLING 0x0000
198 +#define MT7620_ESW_PHY_POLLING 0x7000
200 +#define PMCR_IPG BIT(18)
201 +#define PMCR_MAC_MODE BIT(16)
202 +#define PMCR_FORCE BIT(15)
203 +#define PMCR_TX_EN BIT(14)
204 +#define PMCR_RX_EN BIT(13)
205 +#define PMCR_BACKOFF BIT(9)
206 +#define PMCR_BACKPRES BIT(8)
207 +#define PMCR_RX_FC BIT(5)
208 +#define PMCR_TX_FC BIT(4)
209 +#define PMCR_SPEED(_x) (_x << 2)
210 +#define PMCR_DUPLEX BIT(1)
211 +#define PMCR_LINK BIT(0)
213 +#define PHY_AN_EN BIT(31)
214 +#define PHY_PRE_EN BIT(30)
215 +#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
217 +/* ethernet subsystem config register */
218 +#define ETHSYS_SYSCFG0 0x14
219 +/* ethernet subsystem clock register */
220 +#define ETHSYS_CLKCFG0 0x2c
221 +#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
223 +/* p5 RGMII wrapper TX clock control register */
224 +#define MT7530_P5RGMIITXCR 0x7b04
225 +/* p5 RGMII wrapper RX clock control register */
226 +#define MT7530_P5RGMIIRXCR 0x7b00
227 +/* TRGMII TDX ODT registers */
228 +#define MT7530_TRGMII_TD0_ODT 0x7a54
229 +#define MT7530_TRGMII_TD1_ODT 0x7a5c
230 +#define MT7530_TRGMII_TD2_ODT 0x7a64
231 +#define MT7530_TRGMII_TD3_ODT 0x7a6c
232 +#define MT7530_TRGMII_TD4_ODT 0x7a74
233 +#define MT7530_TRGMII_TD5_ODT 0x7a7c
234 +/* TRGMII TCK ctrl register */
235 +#define MT7530_TRGMII_TCK_CTRL 0x7a78
236 +/* TRGMII Tx ctrl register */
237 +#define MT7530_TRGMII_TXCTRL 0x7a40
238 +/* port 6 extended control register */
239 +#define MT7530_P6ECR 0x7830
240 +/* IO driver control register */
241 +#define MT7530_IO_DRV_CR 0x7810
242 +/* top signal control register */
243 +#define MT7530_TOP_SIG_CTRL 0x7808
244 +/* modified hwtrap register */
245 +#define MT7530_MHWTRAP 0x7804
246 +/* hwtrap status register */
247 +#define MT7530_HWTRAP 0x7800
248 +/* status interrupt register */
249 +#define MT7530_SYS_INT_STS 0x700c
250 +/* system nterrupt register */
251 +#define MT7530_SYS_INT_EN 0x7008
252 +/* system control register */
253 +#define MT7530_SYS_CTRL 0x7000
254 +/* port MAC status register */
255 +#define MT7530_PMSR_P(x) (0x3008 + (x * 0x100))
256 +/* port MAC control register */
257 +#define MT7530_PMCR_P(x) (0x3000 + (x * 0x100))
259 +#define MT7621_XTAL_SHIFT 6
260 +#define MT7621_XTAL_MASK 0x7
261 +#define MT7621_XTAL_25 6
262 +#define MT7621_XTAL_40 3
263 +#define MT7621_MDIO_DRV_MASK (3 << 4)
264 +#define MT7621_GE1_MODE_MASK (3 << 12)
266 +#define TRGMII_TXCTRL_TXC_INV BIT(30)
267 +#define P6ECR_INTF_MODE_RGMII BIT(1)
268 +#define P5RGMIIRXCR_C_ALIGN BIT(8)
269 +#define P5RGMIIRXCR_DELAY_2 BIT(1)
270 +#define P5RGMIITXCR_DELAY_2 (BIT(8) | BIT(2))
272 +/* TOP_SIG_CTRL bits */
273 +#define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
276 +#define MHWTRAP_MANUAL BIT(16)
277 +#define MHWTRAP_P5_MAC_SEL BIT(13)
278 +#define MHWTRAP_P6_DIS BIT(8)
279 +#define MHWTRAP_P5_RGMII_MODE BIT(7)
280 +#define MHWTRAP_P5_DIS BIT(6)
281 +#define MHWTRAP_PHY_ACCESS BIT(5)
284 +#define HWTRAP_XTAL_SHIFT 9
285 +#define HWTRAP_XTAL_MASK 0x3
288 +#define SYS_CTRL_SW_RST BIT(1)
289 +#define SYS_CTRL_REG_RST BIT(0)
292 +#define PMCR_IFG_XMIT_96 BIT(18)
293 +#define PMCR_MAC_MODE BIT(16)
294 +#define PMCR_FORCE_MODE BIT(15)
295 +#define PMCR_TX_EN BIT(14)
296 +#define PMCR_RX_EN BIT(13)
297 +#define PMCR_BACK_PRES_EN BIT(9)
298 +#define PMCR_BACKOFF_EN BIT(8)
299 +#define PMCR_TX_FC_EN BIT(5)
300 +#define PMCR_RX_FC_EN BIT(4)
301 +#define PMCR_FORCE_SPEED_1000 BIT(3)
302 +#define PMCR_FORCE_FDX BIT(1)
303 +#define PMCR_FORCE_LNK BIT(0)
304 +#define PMCR_FIXED_LINK (PMCR_IFG_XMIT_96 | PMCR_MAC_MODE | \
305 + PMCR_FORCE_MODE | PMCR_TX_EN | PMCR_RX_EN | \
306 + PMCR_BACK_PRES_EN | PMCR_BACKOFF_EN | \
307 + PMCR_FORCE_SPEED_1000 | PMCR_FORCE_FDX | \
310 +#define PMCR_FIXED_LINK_FC (PMCR_FIXED_LINK | \
311 + PMCR_TX_FC_EN | PMCR_RX_FC_EN)
313 +/* TRGMII control registers */
314 +#define GSW_INTF_MODE 0x390
315 +#define GSW_TRGMII_TD0_ODT 0x354
316 +#define GSW_TRGMII_TD1_ODT 0x35c
317 +#define GSW_TRGMII_TD2_ODT 0x364
318 +#define GSW_TRGMII_TD3_ODT 0x36c
319 +#define GSW_TRGMII_TXCTL_ODT 0x374
320 +#define GSW_TRGMII_TCK_ODT 0x37c
321 +#define GSW_TRGMII_RCK_CTRL 0x300
323 +#define INTF_MODE_TRGMII BIT(1)
324 +#define TRGMII_RCK_CTRL_RX_RST BIT(31)
327 +/* possible XTAL speed */
328 +#define MT7623_XTAL_40 0
329 +#define MT7623_XTAL_20 1
330 +#define MT7623_XTAL_25 3
332 +/* GPIO port control registers */
333 +#define GPIO_OD33_CTRL8 0x4c0
334 +#define GPIO_BIAS_CTRL 0xed0
335 +#define GPIO_DRV_SEL10 0xf00
337 +/* on MT7620 the functio of port 4 can be software configured */
343 +/* struct mt7620_gsw - the structure that holds the SoC specific data
344 + * @dev: The Device struct
345 + * @base: The base address
346 + * @piac_offset: The PIAC base may change depending on SoC
347 + * @irq: The IRQ we are using
348 + * @port4: The port4 mode on MT7620
349 + * @autopoll: Is MDIO autopolling enabled
350 + * @ethsys: The ethsys register map
351 + * @pctl: The pin control register map
352 + * @clk_trgpll: The trgmii pll clock
355 + struct mtk_eth *eth;
356 + struct device *dev;
357 + void __iomem *base;
361 + unsigned long int autopoll;
363 + struct regmap *ethsys;
364 + struct regmap *pctl;
366 + struct clk *clk_trgpll;
371 +/* switch register I/O wrappers */
372 +void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
373 +u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
375 +/* the callback used by the driver core to bringup the switch */
376 +int mtk_gsw_init(struct mtk_eth *eth);
378 +/* MDIO access wrappers */
379 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
380 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
381 +void mt7620_mdio_link_adjust(struct mtk_eth *eth, int port);
382 +int mt7620_has_carrier(struct mtk_eth *eth);
383 +void mt7620_print_link_state(struct mtk_eth *eth, int port, int link,
384 + int speed, int duplex);
385 +void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
386 +u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
387 +void mt7530_mdio_m32(struct mt7620_gsw *gsw, u32 mask, u32 set, u32 reg);
389 +u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
390 + u32 phy_register, u32 write_data);
391 +u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg);
392 +void mt7620_handle_carrier(struct mtk_eth *eth);
395 diff --git a/drivers/net/ethernet/mediatek/gsw_mt7623.c b/drivers/net/ethernet/mediatek/gsw_mt7623.c
397 index 0000000..78c36c7
399 +++ b/drivers/net/ethernet/mediatek/gsw_mt7623.c
401 +/* This program is free software; you can redistribute it and/or modify
402 + * it under the terms of the GNU General Public License as published by
403 + * the Free Software Foundation; version 2 of the License
405 + * This program is distributed in the hope that it will be useful,
406 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
407 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
408 + * GNU General Public License for more details.
410 + * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
411 + * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
412 + * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
415 +#include <linux/module.h>
416 +#include <linux/kernel.h>
417 +#include <linux/types.h>
418 +#include <linux/platform_device.h>
419 +#include <linux/of_device.h>
420 +#include <linux/of_irq.h>
421 +#include <linux/of_gpio.h>
422 +#include <linux/clk.h>
423 +#include <linux/mfd/syscon.h>
424 +#include <linux/regulator/consumer.h>
425 +#include <linux/pm_runtime.h>
426 +#include <linux/regmap.h>
427 +#include <linux/reset.h>
428 +#include <linux/mii.h>
429 +#include <linux/interrupt.h>
430 +#include <linux/netdevice.h>
431 +#include <linux/dma-mapping.h>
432 +#include <linux/phy.h>
433 +#include <linux/ethtool.h>
434 +#include <linux/version.h>
435 +#include <linux/atomic.h>
437 +#include "mtk_eth_soc.h"
438 +#include "gsw_mt7620.h"
441 +void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
443 + _mtk_mdio_write(gsw->eth, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
444 + _mtk_mdio_write(gsw->eth, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
445 + _mtk_mdio_write(gsw->eth, 0x1f, 0x10, val >> 16);
448 +u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
452 + _mtk_mdio_write(gsw->eth, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
453 + low = _mtk_mdio_read(gsw->eth, 0x1f, (reg >> 2) & 0xf);
454 + high = _mtk_mdio_read(gsw->eth, 0x1f, 0x10);
456 + return (high << 16) | (low & 0xffff);
459 +void mt7530_mdio_m32(struct mt7620_gsw *gsw, u32 mask, u32 set, u32 reg)
461 + u32 val = mt7530_mdio_r32(gsw, reg);
465 + mt7530_mdio_w32(gsw, reg, val);
468 +void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
470 + mtk_w32(gsw->eth, val, reg + 0x10000);
473 +u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
475 + return mtk_r32(gsw->eth, reg + 0x10000);
478 +void mtk_switch_m32(struct mt7620_gsw *gsw, u32 mask, u32 set, unsigned reg)
480 + u32 val = mtk_switch_r32(gsw, reg);
485 + mtk_switch_w32(gsw, val, reg);
488 +static irqreturn_t gsw_interrupt_mt7623(int irq, void *_eth)
490 + struct mtk_eth *eth = (struct mtk_eth *)_eth;
491 + struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
494 + reg = mt7530_mdio_r32(gsw, MT7530_SYS_INT_STS);
496 + for (i = 0; i < 5; i++) {
499 + if ((reg & BIT(i)) == 0)
502 + link = mt7530_mdio_r32(gsw, MT7530_PMSR_P(i)) & 0x1;
505 + dev_info(gsw->dev, "port %d link up\n", i);
507 + dev_info(gsw->dev, "port %d link down\n", i);
510 + mt7530_mdio_w32(gsw, MT7530_SYS_INT_STS, 0x1f);
512 + return IRQ_HANDLED;
515 +static void wait_loop(struct mt7620_gsw *gsw)
520 + for (i = 0; i < 320; i = i + 1)
521 + read_data = mtk_switch_r32(gsw, 0x610);
524 +int mt7623_gsw_config(struct mtk_eth *eth)
526 + if (eth->mii_bus && eth->mii_bus->phy_map[0x1f])
527 + mt7530_probe(eth->dev, NULL, eth->mii_bus, 1);
532 +static void trgmii_calibration_7623(struct mt7620_gsw *gsw)
535 + unsigned int tap_a[5] = { 0, 0, 0, 0, 0 }; /* minumum delay for all correct */
536 + unsigned int tap_b[5] = { 0, 0, 0, 0, 0 }; /* maximum delay for all correct */
537 + unsigned int final_tap[5];
538 + unsigned int rxc_step_size;
539 + unsigned int rxd_step_size;
540 + unsigned int read_data;
542 + unsigned int rd_wd;
544 + unsigned int err_cnt[5];
545 + unsigned int init_toggle_data;
546 + unsigned int err_flag[5];
547 + unsigned int err_total_flag;
548 + unsigned int training_word;
549 + unsigned int rd_tap;
552 + u32 TRGMII_7623_base;
553 + u32 TRGMII_7623_RD_0;
554 + u32 TRGMII_RCK_CTRL;
556 + TRGMII_7623_base = 0x300; /* 0xFB110300 */
557 + TRGMII_7623_RD_0 = TRGMII_7623_base + 0x10;
558 + TRGMII_RCK_CTRL = TRGMII_7623_base;
559 + rxd_step_size = 0x1;
560 + rxc_step_size = 0x4;
561 + init_toggle_data = 0x00000055;
562 + training_word = 0x000000AC;
564 + /* RX clock gating in MT7623 */
565 + mtk_switch_m32(gsw, 0x3fffffff, 0, TRGMII_7623_base + 0x04);
567 + /* Assert RX reset in MT7623 */
568 + mtk_switch_m32(gsw, 0, 0x80000000, TRGMII_7623_base + 0x00);
570 + /* Set TX OE edge in MT7623 */
571 + mtk_switch_m32(gsw, 0, 0x00002000, TRGMII_7623_base + 0x78);
573 + /* Disable RX clock gating in MT7623 */
574 + mtk_switch_m32(gsw, 0, 0xC0000000, TRGMII_7623_base + 0x04);
576 + /* Release RX reset in MT7623 */
577 + mtk_switch_m32(gsw, 0x7fffffff, 0, TRGMII_7623_base);
579 + for (i = 0; i < 5; i++)
580 + mtk_switch_m32(gsw, 0, 0x80000000, TRGMII_7623_RD_0 + i * 8);
582 + /* Enable Training Mode in MT7530 */
583 + mt7530_mdio_m32(gsw, 0, 0xC0000000, 0x7A40);
585 + /* Adjust RXC delay in MT7623 */
587 + err_total_flag = 0;
588 + while (err_total_flag == 0 && read_data != 0x68) {
589 + /* Enable EDGE CHK in MT7623 */
590 + for (i = 0; i < 5; i++)
591 + mtk_switch_m32(gsw, 0x4fffffff, 0x40000000, TRGMII_7623_RD_0 + i * 8);
594 + err_total_flag = 1;
595 + for (i = 0; i < 5; i++) {
597 + mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8) >> 8;
598 + err_cnt[i] &= 0x0000000f;
599 + rd_wd = mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8) >> 16;
600 + rd_wd &= 0x000000ff;
601 + val = mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8);
602 + pr_err("ERR_CNT = %d, RD_WD =%x, TRGMII_7623_RD_0=%x\n",
603 + err_cnt[i], rd_wd, val);
604 + if (err_cnt[i] != 0) {
606 + } else if (rd_wd != 0x55) {
611 + err_total_flag = err_flag[i] & err_total_flag;
614 + pr_err("2nd Disable EDGE CHK in MT7623\n");
615 + /* Disable EDGE CHK in MT7623 */
616 + for (i = 0; i < 5; i++)
617 + mtk_switch_m32(gsw, 0x4fffffff, 0x40000000, TRGMII_7623_RD_0 + i * 8);
619 + pr_err("2nd Disable EDGE CHK in MT7623\n");
620 + /* Adjust RXC delay */
621 + /* RX clock gating in MT7623 */
622 + mtk_switch_m32(gsw, 0x3fffffff, 0, TRGMII_7623_base + 0x04);
623 + read_data = mtk_switch_r32(gsw, TRGMII_7623_base);
624 + if (err_total_flag == 0) {
625 + tmp = (read_data & 0x0000007f) + rxc_step_size;
626 + pr_err(" RXC delay = %d\n", tmp);
628 + read_data &= 0xffffff80;
631 + read_data &= 0xffffff80;
633 + mtk_switch_w32(gsw, read_data, TRGMII_7623_base);
635 + tmp = (read_data & 0x0000007f) + 16;
636 + pr_err(" RXC delay = %d\n", tmp);
638 + read_data &= 0xffffff80;
641 + read_data &= 0xffffff80;
643 + mtk_switch_w32(gsw, read_data, TRGMII_7623_base);
645 + read_data &= 0x000000ff;
647 + /* Disable RX clock gating in MT7623 */
648 + mtk_switch_m32(gsw, 0, 0xC0000000, TRGMII_7623_base + 0x04);
649 + for (i = 0; i < 5; i++)
650 + mtk_switch_m32(gsw, 0, 0x80000000, TRGMII_7623_RD_0 + i * 8);
653 + /* Read RD_WD MT7623 */
654 + for (i = 0; i < 5; i++) {
656 + while (err_flag[i] != 0 && rd_tap != 128) {
657 + /* Enable EDGE CHK in MT7623 */
658 + mtk_switch_m32(gsw, 0x4fffffff, 0x40000000, TRGMII_7623_RD_0 + i * 8);
661 + read_data = mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8);
662 + err_cnt[i] = (read_data >> 8) & 0x0000000f; /* Read MT7623 Errcnt */
663 + rd_wd = (read_data >> 16) & 0x000000ff;
664 + if (err_cnt[i] != 0 || rd_wd != 0x55) {
669 + /* Disable EDGE CHK in MT7623 */
670 + mtk_switch_m32(gsw, 0x4fffffff, 0x40000000, TRGMII_7623_RD_0 + i * 8);
672 + if (err_flag[i] != 0) {
673 + rd_tap = (read_data & 0x0000007f) + rxd_step_size; /* Add RXD delay in MT7623 */
674 + read_data = (read_data & 0xffffff80) | rd_tap;
675 + mtk_switch_w32(gsw, read_data,
676 + TRGMII_7623_RD_0 + i * 8);
679 + rd_tap = (read_data & 0x0000007f) + 48;
680 + read_data = (read_data & 0xffffff80) | rd_tap;
681 + mtk_switch_w32(gsw, read_data,
682 + TRGMII_7623_RD_0 + i * 8);
686 + pr_err("MT7623 %dth bit Tap_a = %d\n", i, tap_a[i]);
688 + /* pr_err("Last While Loop\n"); */
689 + for (i = 0; i < 5; i++) {
690 + while ((err_flag[i] == 0) && (rd_tap != 128)) {
691 + read_data = mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8);
692 + rd_tap = (read_data & 0x0000007f) + rxd_step_size; /* Add RXD delay in MT7623 */
693 + read_data = (read_data & 0xffffff80) | rd_tap;
694 + mtk_switch_w32(gsw, read_data, TRGMII_7623_RD_0 + i * 8);
695 + /* Enable EDGE CHK in MT7623 */
697 + mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8) | 0x40000000;
699 + mtk_switch_w32(gsw, val, TRGMII_7623_RD_0 + i * 8);
701 + read_data = mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8);
702 + err_cnt[i] = (read_data >> 8) & 0x0000000f; /* Read MT7623 Errcnt */
703 + rd_wd = (read_data >> 16) & 0x000000ff;
704 + if (err_cnt[i] != 0 || rd_wd != 0x55) {
710 + /* Disable EDGE CHK in MT7623 */
711 + mtk_switch_m32(gsw, 0x4fffffff, 0x40000000, TRGMII_7623_RD_0 + i * 8);
716 + tap_b[i] = rd_tap; /* -rxd_step_size; */
717 + pr_err("MT7623 %dth bit Tap_b = %d\n", i, tap_b[i]);
718 + final_tap[i] = (tap_a[i] + tap_b[i]) / 2; /* Calculate RXD delay = (TAP_A + TAP_B)/2 */
719 + read_data = (read_data & 0xffffff80) | final_tap[i];
720 + mtk_switch_w32(gsw, read_data, TRGMII_7623_RD_0 + i * 8);
723 + read_data = mt7530_mdio_r32(gsw, 0x7A40);
724 + read_data &= 0x3fffffff;
725 + mt7530_mdio_w32(gsw, 0x7A40, read_data);
728 +static void trgmii_calibration_7530(struct mt7620_gsw *gsw)
731 + unsigned int tap_a[5] = { 0, 0, 0, 0, 0 };
732 + unsigned int tap_b[5] = { 0, 0, 0, 0, 0 };
733 + unsigned int final_tap[5];
734 + unsigned int rxc_step_size;
735 + unsigned int rxd_step_size;
736 + unsigned int read_data;
737 + unsigned int tmp = 0;
739 + unsigned int err_cnt[5];
740 + unsigned int rd_wd;
741 + unsigned int init_toggle_data;
742 + unsigned int err_flag[5];
743 + unsigned int err_total_flag;
744 + unsigned int training_word;
745 + unsigned int rd_tap;
747 + u32 TRGMII_7623_base;
748 + u32 TRGMII_7530_RD_0;
749 + u32 TRGMII_RCK_CTRL;
750 + u32 TRGMII_7530_base;
751 + u32 TRGMII_7530_TX_base;
753 + TRGMII_7623_base = 0x300;
754 + TRGMII_7530_base = 0x7A00;
755 + TRGMII_7530_RD_0 = TRGMII_7530_base + 0x10;
756 + TRGMII_RCK_CTRL = TRGMII_7623_base;
757 + rxd_step_size = 0x1;
758 + rxc_step_size = 0x8;
759 + init_toggle_data = 0x00000055;
760 + training_word = 0x000000AC;
762 + TRGMII_7530_TX_base = TRGMII_7530_base + 0x50;
764 + /* Calibration begin */
765 + mtk_switch_m32(gsw, 0, 0x80000000, TRGMII_7623_base + 0x40);
767 + /* RX clock gating in MT7530 */
768 + mt7530_mdio_m32(gsw, 0x3fffffff, 0, TRGMII_7530_base + 0x04);
770 + /* Set TX OE edge in MT7530 */
771 + mt7530_mdio_m32(gsw, 0, 0x2000, TRGMII_7530_base + 0x78);
773 + /* Assert RX reset in MT7530 */
774 + mt7530_mdio_m32(gsw, 0, 0x80000000, TRGMII_7530_base);
776 + /* Release RX reset in MT7530 */
777 + mt7530_mdio_m32(gsw, 0x7fffffff, 0, TRGMII_7530_base);
779 + /* Disable RX clock gating in MT7530 */
780 + mt7530_mdio_m32(gsw, 0, 0xC0000000, TRGMII_7530_base + 0x04);
782 + /* Enable Training Mode in MT7623 */
783 + mtk_switch_m32(gsw, 0, 0x80000000, TRGMII_7623_base + 0x40);
784 + if (gsw->trgmii_force == 2000)
785 + mtk_switch_m32(gsw, 0, 0xC0000000, TRGMII_7623_base + 0x40);
787 + mtk_switch_m32(gsw, 0, 0x80000000, TRGMII_7623_base + 0x40);
788 + mtk_switch_m32(gsw, 0xfffff0ff, 0, TRGMII_7623_base + 0x078);
789 + mtk_switch_m32(gsw, 0xfffff0ff, 0, TRGMII_7623_base + 0x50);
790 + mtk_switch_m32(gsw, 0xfffff0ff, 0, TRGMII_7623_base + 0x58);
791 + mtk_switch_m32(gsw, 0xfffff0ff, 0, TRGMII_7623_base + 0x60);
792 + mtk_switch_m32(gsw, 0xfffff0ff, 0, TRGMII_7623_base + 0x68);
793 + mtk_switch_m32(gsw, 0xfffff0ff, 0, TRGMII_7623_base + 0x70);
794 + mtk_switch_m32(gsw, 0x00000800, 0, TRGMII_7623_base + 0x78);
796 + /* Adjust RXC delay in MT7530 */
797 + err_total_flag = 0;
799 + while (err_total_flag == 0 && (read_data != 0x68)) {
800 + /* Enable EDGE CHK in MT7530 */
801 + for (i = 0; i < 5; i++) {
802 + mt7530_mdio_m32(gsw, 0x4fffffff, 0x40000000,
803 + TRGMII_7530_RD_0 + i * 8);
806 + /* 2nd Disable EDGE CHK in MT7530 */
807 + err_cnt[i] = mt7530_mdio_r32(gsw, TRGMII_7530_RD_0 + i * 8);
809 + err_cnt[i] &= 0x0000ff0f;
811 + rd_wd = err_cnt[i] >> 8;
812 + rd_wd &= 0x000000ff;
814 + err_cnt[i] &= 0x0000000f;
815 + if (err_cnt[i] != 0)
817 + else if (rd_wd != 0x55)
822 + err_total_flag = err_flag[i];
824 + err_total_flag = err_flag[i] & err_total_flag;
826 + /* Disable EDGE CHK in MT7530 */
827 + mt7530_mdio_m32(gsw, 0x4fffffff, 0x40000000,
828 + TRGMII_7530_RD_0 + i * 8);
832 + /* Adjust RXC delay */
833 + if (err_total_flag == 0) {
834 + /* Assert RX reset in MT7530 */
835 + mt7530_mdio_m32(gsw, 0, 0x80000000, TRGMII_7530_base);
837 + /* RX clock gating in MT7530 */
838 + mt7530_mdio_m32(gsw, 0x3fffffff, 0, TRGMII_7530_base + 0x04);
840 + read_data = mt7530_mdio_r32(gsw, TRGMII_7530_base);
843 + tmp += rxc_step_size;
844 + /* pr_err("Current rxc delay = %d\n", tmp); */
845 + read_data &= 0xffffff80;
847 + mt7530_mdio_w32(gsw, TRGMII_7530_base, read_data);
848 + read_data = mt7530_mdio_r32(gsw, TRGMII_7530_base);
849 + /* pr_err("Current RXC delay = %x\n", read_data); */
851 + read_data = mt7530_mdio_r32(gsw, TRGMII_7530_base);
852 + read_data &= 0x7fffffff;
853 + mt7530_mdio_w32(gsw, TRGMII_7530_base, read_data); /* Release RX reset in MT7530 */
856 + mt7530_mdio_r32(gsw, TRGMII_7530_base + 0x04);
857 + read_data |= 0xc0000000;
858 + mt7530_mdio_w32(gsw, TRGMII_7530_base + 0x04, read_data); /* Disable RX clock gating in MT7530 */
859 + pr_err("####### MT7530 RXC delay is %d\n", tmp);
863 + pr_err("Finish RXC Adjustment while loop\n");
865 + /* pr_err("Read RD_WD MT7530\n"); */
866 + /* Read RD_WD MT7530 */
867 + for (i = 0; i < 5; i++) {
869 + while (err_flag[i] != 0 && rd_tap != 128) {
870 + /* Enable EDGE CHK in MT7530 */
872 + mt7530_mdio_r32(gsw, TRGMII_7530_RD_0 + i * 8);
873 + read_data |= 0x40000000;
874 + read_data &= 0x4fffffff;
875 + mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
878 + err_cnt[i] = (read_data >> 8) & 0x0000000f;
879 + rd_wd = (read_data >> 16) & 0x000000ff;
880 + if (err_cnt[i] != 0 || rd_wd != 0x55) {
885 + if (err_flag[i] != 0) {
886 + rd_tap = (read_data & 0x0000007f) + rxd_step_size; /* Add RXD delay in MT7530 */
887 + read_data = (read_data & 0xffffff80) | rd_tap;
888 + mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
892 + tap_a[i] = (read_data & 0x0000007f); /* Record the min delay TAP_A */
893 + rd_tap = tap_a[i] + 0x4;
894 + read_data = (read_data & 0xffffff80) | rd_tap;
895 + mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
899 + /* Disable EDGE CHK in MT7530 */
901 + mt7530_mdio_r32(gsw, TRGMII_7530_RD_0 + i * 8);
902 + read_data |= 0x40000000;
903 + read_data &= 0x4fffffff;
904 + mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
909 + pr_err("MT7530 %dth bit Tap_a = %d\n", i, tap_a[i]);
912 + /* pr_err("Last While Loop\n"); */
913 + for (i = 0; i < 5; i++) {
915 + while (err_flag[i] == 0 && (rd_tap != 128)) {
916 + /* Enable EDGE CHK in MT7530 */
917 + read_data = mt7530_mdio_r32(gsw, TRGMII_7530_RD_0 + i * 8);
918 + read_data |= 0x40000000;
919 + read_data &= 0x4fffffff;
920 + mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
923 + err_cnt[i] = (read_data >> 8) & 0x0000000f;
924 + rd_wd = (read_data >> 16) & 0x000000ff;
925 + if (err_cnt[i] != 0 || rd_wd != 0x55)
930 + if (err_flag[i] == 0 && (rd_tap != 128)) {
931 + /* Add RXD delay in MT7530 */
932 + rd_tap = (read_data & 0x0000007f) + rxd_step_size;
933 + read_data = (read_data & 0xffffff80) | rd_tap;
934 + mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
937 + /* Disable EDGE CHK in MT7530 */
939 + mt7530_mdio_r32(gsw, TRGMII_7530_RD_0 + i * 8);
940 + read_data |= 0x40000000;
941 + read_data &= 0x4fffffff;
942 + mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
946 + tap_b[i] = rd_tap; /* - rxd_step_size; */
947 + pr_err("MT7530 %dth bit Tap_b = %d\n", i, tap_b[i]);
948 + final_tap[i] = (tap_a[i] + tap_b[i]) / 2;
950 + read_data = (read_data & 0xffffff80) | final_tap[i];
951 + mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8, read_data);
954 + if (gsw->trgmii_force == 2000)
955 + mtk_switch_m32(gsw, 0x7fffffff, 0, TRGMII_7623_base + 0x40);
957 + mtk_switch_m32(gsw, 0x3fffffff, 0, TRGMII_7623_base + 0x40);
961 +static void mt7530_trgmii_clock_setting(struct mt7620_gsw *gsw, u32 xtal_mode)
964 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
965 + _mtk_mdio_write(gsw->eth, 0, 14, 0x410);
966 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
967 + _mtk_mdio_write(gsw->eth, 0, 14, 0x1);
968 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
969 + _mtk_mdio_write(gsw->eth, 0, 14, 0x404);
970 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
972 + if (xtal_mode == 1) {
974 + if (gsw->trgmii_force == 2600)
976 + _mtk_mdio_write(gsw->eth, 0, 14, 0x1a00);
977 + else if (gsw->trgmii_force == 2000)
979 + _mtk_mdio_write(gsw->eth, 0, 14, 0x1400);
980 + } else if (xtal_mode == 2) {
982 + if (gsw->trgmii_force == 2600)
984 + _mtk_mdio_write(gsw->eth, 0, 14, 0x1040);
985 + else if (gsw->trgmii_force == 2000)
987 + _mtk_mdio_write(gsw->eth, 0, 14, 0x0c80);
989 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
990 + _mtk_mdio_write(gsw->eth, 0, 14, 0x405);
991 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
992 + _mtk_mdio_write(gsw->eth, 0, 14, 0x0);
993 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
994 + _mtk_mdio_write(gsw->eth, 0, 14, 0x409);
995 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
996 + if (xtal_mode == 1)
998 + _mtk_mdio_write(gsw->eth, 0, 14, 0x0057);
1001 + _mtk_mdio_write(gsw->eth, 0, 14, 0x0087);
1002 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
1003 + _mtk_mdio_write(gsw->eth, 0, 14, 0x40a);
1004 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
1005 + if (xtal_mode == 1)
1007 + _mtk_mdio_write(gsw->eth, 0, 14, 0x0057);
1010 + _mtk_mdio_write(gsw->eth, 0, 14, 0x0087);
1012 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
1013 + _mtk_mdio_write(gsw->eth, 0, 14, 0x403);
1014 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
1015 + _mtk_mdio_write(gsw->eth, 0, 14, 0x1800);
1017 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
1018 + _mtk_mdio_write(gsw->eth, 0, 14, 0x403);
1019 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
1020 + _mtk_mdio_write(gsw->eth, 0, 14, 0x1c00);
1022 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
1023 + _mtk_mdio_write(gsw->eth, 0, 14, 0x401);
1024 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
1025 + _mtk_mdio_write(gsw->eth, 0, 14, 0xc020);
1027 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
1028 + _mtk_mdio_write(gsw->eth, 0, 14, 0x406);
1029 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
1030 + _mtk_mdio_write(gsw->eth, 0, 14, 0xa030);
1032 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
1033 + _mtk_mdio_write(gsw->eth, 0, 14, 0x406);
1034 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
1035 + _mtk_mdio_write(gsw->eth, 0, 14, 0xa038);
1037 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
1038 + _mtk_mdio_write(gsw->eth, 0, 14, 0x410);
1039 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
1040 + _mtk_mdio_write(gsw->eth, 0, 14, 0x3);
1042 + mt7530_mdio_m32(gsw, 0xfffffffc, 0x1, 0x7830);
1043 + mt7530_mdio_m32(gsw, 0xcfffffff, 0, 0x7a40);
1044 + mt7530_mdio_w32(gsw, 0x7a78, 0x55);
1045 + mtk_switch_m32(gsw, 0x7fffffff, 0, 0x300);
1047 + trgmii_calibration_7623(gsw);
1048 + trgmii_calibration_7530(gsw);
1050 + mtk_switch_m32(gsw, 0, 0x80000000, 0x300);
1051 + mtk_switch_m32(gsw, 0, 0x7fffffff, 0x300);
1053 + /* MT7530 RXC reset */
1054 + mt7530_mdio_m32(gsw, 0, BIT(31), 0x7a00);
1057 + mt7530_mdio_m32(gsw, ~BIT(31), 0, 0x7a00);
1061 +static void mt7623_hw_init(struct mtk_eth *eth, struct mt7620_gsw *gsw,
1062 + struct device_node *np)
1068 + regmap_update_bits(gsw->ethsys, ETHSYS_CLKCFG0,
1069 + ETHSYS_TRGMII_CLK_SEL362_5,
1070 + ETHSYS_TRGMII_CLK_SEL362_5);
1072 + /* reset the TRGMII core */
1073 + mtk_switch_m32(gsw, 0, INTF_MODE_TRGMII, GSW_INTF_MODE);
1074 + mtk_switch_m32(gsw, 0, TRGMII_RCK_CTRL_RX_RST, GSW_TRGMII_RCK_CTRL);
1076 + /* Hardware reset Switch */
1077 + //device_reset(eth->dev);
1078 + printk("%s:%s[%d]reset_switch\n", __FILE__, __func__, __LINE__);
1080 + /* Wait for Switch Reset Completed*/
1081 + for (i = 0; i < 100; i++) {
1083 + if (mt7530_mdio_r32(gsw, MT7530_HWTRAP))
1087 + /* turn off all PHYs */
1088 + for (i = 0; i <= 4; i++) {
1089 + val = _mtk_mdio_read(gsw->eth, i, 0x0);
1091 + _mtk_mdio_write(gsw->eth, i, 0x0, val);
1094 + /* reset the switch */
1095 + mt7530_mdio_w32(gsw, MT7530_SYS_CTRL,
1096 + SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
1099 + /* GE1, Force 1000M/FD, FC ON */
1100 + mt7530_mdio_w32(gsw, MT7530_PMCR_P(6), PMCR_FIXED_LINK_FC);
1102 + /* GE2, Force 1000M/FD, FC ON */
1103 + mt7530_mdio_w32(gsw, MT7530_PMCR_P(5), PMCR_FIXED_LINK_FC);
1105 + /* Enable Port 6, P5 as GMAC5, P5 disable */
1106 + val = mt7530_mdio_r32(gsw, MT7530_MHWTRAP);
1107 + /* Enable Port 6 */
1108 + val &= ~MHWTRAP_P6_DIS;
1109 + /* Enable Port 5 */
1110 + val &= ~MHWTRAP_P5_DIS;
1111 + /* Port 5 as GMAC */
1112 + val |= MHWTRAP_P5_MAC_SEL;
1113 + /* Port 5 Interface mode */
1114 + val |= MHWTRAP_P5_RGMII_MODE;
1115 + /* Set MT7530 phy direct access mode**/
1116 + val &= ~MHWTRAP_PHY_ACCESS;
1117 + /* manual override of HW-Trap */
1118 + val |= MHWTRAP_MANUAL;
1119 + mt7530_mdio_w32(gsw, MT7530_MHWTRAP, val);
1121 + xtal_mode = mt7530_mdio_r32(gsw, MT7530_HWTRAP);
1122 + xtal_mode >>= HWTRAP_XTAL_SHIFT;
1123 + xtal_mode &= HWTRAP_XTAL_MASK;
1124 + if (xtal_mode == MT7623_XTAL_40) {
1125 + /* disable MT7530 core clock */
1126 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
1127 + _mtk_mdio_write(gsw->eth, 0, 14, 0x410);
1128 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
1129 + _mtk_mdio_write(gsw->eth, 0, 14, 0x0);
1131 + /* disable MT7530 PLL */
1132 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
1133 + _mtk_mdio_write(gsw->eth, 0, 14, 0x40d);
1134 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
1135 + _mtk_mdio_write(gsw->eth, 0, 14, 0x2020);
1137 + /* for MT7530 core clock = 500Mhz */
1138 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
1139 + _mtk_mdio_write(gsw->eth, 0, 14, 0x40e);
1140 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
1141 + _mtk_mdio_write(gsw->eth, 0, 14, 0x119);
1143 + /* enable MT7530 PLL */
1144 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
1145 + _mtk_mdio_write(gsw->eth, 0, 14, 0x40d);
1146 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
1147 + _mtk_mdio_write(gsw->eth, 0, 14, 0x2820);
1151 + /* enable MT7530 core clock */
1152 + _mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
1153 + _mtk_mdio_write(gsw->eth, 0, 14, 0x410);
1154 + _mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
1158 + _mtk_mdio_write(gsw->eth, 0, 14, 0x1);
1160 + /* set MT7530 central align */
1161 + mt7530_mdio_m32(gsw, ~BIT(0), BIT(1), MT7530_P6ECR);
1162 + mt7530_mdio_m32(gsw, ~BIT(30), 0, MT7530_TRGMII_TXCTRL);
1163 + mt7530_mdio_w32(gsw, MT7530_TRGMII_TCK_CTRL, 0x855);
1165 + /* delay setting for 10/1000M */
1166 + mt7530_mdio_w32(gsw, MT7530_P5RGMIIRXCR, 0x104);
1167 + mt7530_mdio_w32(gsw, MT7530_P5RGMIITXCR, 0x10);
1169 + /* lower Tx Driving */
1170 + mt7530_mdio_w32(gsw, MT7530_TRGMII_TD0_ODT, 0x88);
1171 + mt7530_mdio_w32(gsw, MT7530_TRGMII_TD1_ODT, 0x88);
1172 + mt7530_mdio_w32(gsw, MT7530_TRGMII_TD2_ODT, 0x88);
1173 + mt7530_mdio_w32(gsw, MT7530_TRGMII_TD3_ODT, 0x88);
1174 + mt7530_mdio_w32(gsw, MT7530_TRGMII_TD4_ODT, 0x88);
1175 + mt7530_mdio_w32(gsw, MT7530_TRGMII_TD5_ODT, 0x88);
1176 + mt7530_mdio_w32(gsw, MT7530_IO_DRV_CR, 0x11);
1178 + /* Set MT7623/MT7683 TX Driving */
1179 + mtk_switch_w32(gsw, 0x88, GSW_TRGMII_TD0_ODT);
1180 + mtk_switch_w32(gsw, 0x88, GSW_TRGMII_TD0_ODT);
1181 + mtk_switch_w32(gsw, 0x88, GSW_TRGMII_TD0_ODT);
1182 + mtk_switch_w32(gsw, 0x88, GSW_TRGMII_TD0_ODT);
1183 + mtk_switch_w32(gsw, 0x88, GSW_TRGMII_TXCTL_ODT);
1184 + mtk_switch_w32(gsw, 0x88, GSW_TRGMII_TCK_ODT);
1186 +// mt7530_trgmii_clock_setting(gsw, xtal_mode);
1189 + for (i = 0; i <= 4; i++) {
1190 + _mtk_mdio_write(gsw->eth, i, 13, 0x7);
1191 + _mtk_mdio_write(gsw->eth, i, 14, 0x3C);
1192 + _mtk_mdio_write(gsw->eth, i, 13, 0x4007);
1193 + _mtk_mdio_write(gsw->eth, i, 14, 0x0);
1195 + /* Increase SlvDPSready time */
1196 + _mtk_mdio_write(gsw->eth, i, 31, 0x52b5);
1197 + _mtk_mdio_write(gsw->eth, i, 16, 0xafae);
1198 + _mtk_mdio_write(gsw->eth, i, 18, 0x2f);
1199 + _mtk_mdio_write(gsw->eth, i, 16, 0x8fae);
1201 + /* Incease post_update_timer */
1202 + _mtk_mdio_write(gsw->eth, i, 31, 0x3);
1203 + _mtk_mdio_write(gsw->eth, i, 17, 0x4b);
1205 + /* Adjust 100_mse_threshold */
1206 + _mtk_mdio_write(gsw->eth, i, 13, 0x1e);
1207 + _mtk_mdio_write(gsw->eth, i, 14, 0x123);
1208 + _mtk_mdio_write(gsw->eth, i, 13, 0x401e);
1209 + _mtk_mdio_write(gsw->eth, i, 14, 0xffff);
1212 + _mtk_mdio_write(gsw->eth, i, 13, 0x1e);
1213 + _mtk_mdio_write(gsw->eth, i, 14, 0xa6);
1214 + _mtk_mdio_write(gsw->eth, i, 13, 0x401e);
1215 + _mtk_mdio_write(gsw->eth, i, 14, 0x300);
1217 + /* Disable HW auto downshift*/
1218 + _mtk_mdio_write(gsw->eth, i, 31, 0x1);
1219 + val = _mtk_mdio_read(gsw->eth, i, 0x14);
1221 + _mtk_mdio_write(gsw->eth, i, 0x14, val);
1224 + /* turn on all PHYs */
1225 + for (i = 0; i <= 4; i++) {
1226 + val = _mtk_mdio_read(gsw->eth, i, 0);
1228 + _mtk_mdio_write(gsw->eth, i, 0, val);
1232 + mt7530_mdio_m32(gsw, 0, TOP_SIG_CTRL_NORMAL, MT7530_TOP_SIG_CTRL);
1235 +static const struct of_device_id mediatek_gsw_match[] = {
1236 + { .compatible = "mediatek,mt7623-gsw" },
1239 +MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
1241 +int mtk_gsw_init(struct mtk_eth *eth)
1243 + struct device_node *np = eth->switch_np;
1244 + struct platform_device *pdev = of_find_device_by_node(np);
1245 + struct mt7620_gsw *gsw;
1250 + if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
1253 + gsw = platform_get_drvdata(pdev);
1256 + eth->sw_priv = gsw;
1259 + mt7623_hw_init(eth, gsw, np);
1261 + request_threaded_irq(gsw->irq, gsw_interrupt_mt7623, NULL, 0,
1263 + mt7530_mdio_w32(gsw, MT7530_SYS_INT_EN, 0x1f);
1268 +static int mt7623_gsw_probe(struct platform_device *pdev)
1270 + struct device_node *np = pdev->dev.of_node;
1271 + struct device_node *pctl;
1272 + int reset_pin, ret;
1273 + struct mt7620_gsw *gsw;
1274 + struct regulator *supply;
1276 + gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
1280 + gsw->dev = &pdev->dev;
1281 + gsw->irq = irq_of_parse_and_map(np, 0);
1285 + gsw->ethsys = syscon_regmap_lookup_by_phandle(np, "mediatek,ethsys");
1286 + if (IS_ERR(gsw->ethsys))
1287 + return PTR_ERR(gsw->ethsys);
1289 + reset_pin = of_get_named_gpio(np, "mediatek,reset-pin", 0);
1290 + if (reset_pin < 0)
1293 + pctl = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1295 + return PTR_ERR(pctl);
1297 + gsw->pctl = syscon_node_to_regmap(pctl);
1299 + return PTR_ERR(pctl);
1301 + ret = devm_gpio_request(&pdev->dev, reset_pin, "mt7530-reset");
1305 + gsw->clk_trgpll = devm_clk_get(&pdev->dev, "trgpll");
1306 + if (IS_ERR(gsw->clk_trgpll))
1309 + supply = devm_regulator_get(&pdev->dev, "mt7530");
1310 + if (IS_ERR(supply))
1311 + return PTR_ERR(supply);
1313 + regulator_set_voltage(supply, 1000000, 1000000);
1314 + ret = regulator_enable(supply);
1316 + dev_err(&pdev->dev, "Failed to enable reg-7530: %d\n", ret);
1319 + pm_runtime_enable(&pdev->dev);
1320 + pm_runtime_get_sync(&pdev->dev);
1322 + ret = clk_set_rate(gsw->clk_trgpll, 500000000);
1326 + clk_prepare_enable(gsw->clk_trgpll);
1328 + gpio_direction_output(reset_pin, 0);
1330 + gpio_set_value(reset_pin, 1);
1333 + platform_set_drvdata(pdev, gsw);
1338 +static int mt7623_gsw_remove(struct platform_device *pdev)
1340 + struct mt7620_gsw *gsw = platform_get_drvdata(pdev);
1342 + clk_disable_unprepare(gsw->clk_trgpll);
1344 + pm_runtime_put_sync(&pdev->dev);
1345 + pm_runtime_disable(&pdev->dev);
1347 + platform_set_drvdata(pdev, NULL);
1352 +static struct platform_driver gsw_driver = {
1353 + .probe = mt7623_gsw_probe,
1354 + .remove = mt7623_gsw_remove,
1356 + .name = "mt7623-gsw",
1357 + .owner = THIS_MODULE,
1358 + .of_match_table = mediatek_gsw_match,
1362 +module_platform_driver(gsw_driver);
1364 +MODULE_LICENSE("GPL");
1365 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1366 +MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7623 SoC");
1367 diff --git a/drivers/net/ethernet/mediatek/mt7530.c b/drivers/net/ethernet/mediatek/mt7530.c
1368 new file mode 100644
1369 index 0000000..2e9d280
1371 +++ b/drivers/net/ethernet/mediatek/mt7530.c
1374 + * This program is free software; you can redistribute it and/or
1375 + * modify it under the terms of the GNU General Public License
1376 + * as published by the Free Software Foundation; either version 2
1377 + * of the License, or (at your option) any later version.
1379 + * This program is distributed in the hope that it will be useful,
1380 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1381 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1382 + * GNU General Public License for more details.
1384 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
1387 +#include <linux/if.h>
1388 +#include <linux/module.h>
1389 +#include <linux/init.h>
1390 +#include <linux/list.h>
1391 +#include <linux/if_ether.h>
1392 +#include <linux/skbuff.h>
1393 +#include <linux/netdevice.h>
1394 +#include <linux/netlink.h>
1395 +#include <linux/bitops.h>
1396 +#include <net/genetlink.h>
1397 +#include <linux/switch.h>
1398 +#include <linux/delay.h>
1399 +#include <linux/phy.h>
1400 +#include <linux/netdevice.h>
1401 +#include <linux/etherdevice.h>
1402 +#include <linux/lockdep.h>
1403 +#include <linux/workqueue.h>
1404 +#include <linux/of_device.h>
1406 +#include "mt7530.h"
1408 +#define MT7530_CPU_PORT 6
1409 +#define MT7530_NUM_PORTS 8
1410 +#define MT7530_NUM_VLANS 16
1411 +#define MT7530_MAX_VID 4095
1412 +#define MT7530_MIN_VID 0
1415 +#define REG_ESW_VLAN_VTCR 0x90
1416 +#define REG_ESW_VLAN_VAWD1 0x94
1417 +#define REG_ESW_VLAN_VAWD2 0x98
1418 +#define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
1420 +#define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
1421 +#define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
1422 +#define REG_ESW_VLAN_VAWD1_VALID BIT(0)
1424 +/* vlan egress mode */
1426 + ETAG_CTRL_UNTAG = 0,
1427 + ETAG_CTRL_TAG = 2,
1428 + ETAG_CTRL_SWAP = 1,
1429 + ETAG_CTRL_STACK = 3,
1432 +#define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
1433 +#define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
1434 +#define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
1436 +#define REG_HWTRAP 0x7804
1438 +#define MIB_DESC(_s , _o, _n) \
1445 +struct mt7xxx_mib_desc {
1446 + unsigned int size;
1447 + unsigned int offset;
1451 +#define MT7621_MIB_COUNTER_BASE 0x4000
1452 +#define MT7621_MIB_COUNTER_PORT_OFFSET 0x100
1453 +#define MT7621_STATS_TDPC 0x00
1454 +#define MT7621_STATS_TCRC 0x04
1455 +#define MT7621_STATS_TUPC 0x08
1456 +#define MT7621_STATS_TMPC 0x0C
1457 +#define MT7621_STATS_TBPC 0x10
1458 +#define MT7621_STATS_TCEC 0x14
1459 +#define MT7621_STATS_TSCEC 0x18
1460 +#define MT7621_STATS_TMCEC 0x1C
1461 +#define MT7621_STATS_TDEC 0x20
1462 +#define MT7621_STATS_TLCEC 0x24
1463 +#define MT7621_STATS_TXCEC 0x28
1464 +#define MT7621_STATS_TPPC 0x2C
1465 +#define MT7621_STATS_TL64PC 0x30
1466 +#define MT7621_STATS_TL65PC 0x34
1467 +#define MT7621_STATS_TL128PC 0x38
1468 +#define MT7621_STATS_TL256PC 0x3C
1469 +#define MT7621_STATS_TL512PC 0x40
1470 +#define MT7621_STATS_TL1024PC 0x44
1471 +#define MT7621_STATS_TOC 0x48
1472 +#define MT7621_STATS_RDPC 0x60
1473 +#define MT7621_STATS_RFPC 0x64
1474 +#define MT7621_STATS_RUPC 0x68
1475 +#define MT7621_STATS_RMPC 0x6C
1476 +#define MT7621_STATS_RBPC 0x70
1477 +#define MT7621_STATS_RAEPC 0x74
1478 +#define MT7621_STATS_RCEPC 0x78
1479 +#define MT7621_STATS_RUSPC 0x7C
1480 +#define MT7621_STATS_RFEPC 0x80
1481 +#define MT7621_STATS_ROSPC 0x84
1482 +#define MT7621_STATS_RJEPC 0x88
1483 +#define MT7621_STATS_RPPC 0x8C
1484 +#define MT7621_STATS_RL64PC 0x90
1485 +#define MT7621_STATS_RL65PC 0x94
1486 +#define MT7621_STATS_RL128PC 0x98
1487 +#define MT7621_STATS_RL256PC 0x9C
1488 +#define MT7621_STATS_RL512PC 0xA0
1489 +#define MT7621_STATS_RL1024PC 0xA4
1490 +#define MT7621_STATS_ROC 0xA8
1491 +#define MT7621_STATS_RDPC_CTRL 0xB0
1492 +#define MT7621_STATS_RDPC_ING 0xB4
1493 +#define MT7621_STATS_RDPC_ARL 0xB8
1495 +static const struct mt7xxx_mib_desc mt7621_mibs[] = {
1496 + MIB_DESC(1, MT7621_STATS_TDPC, "TxDrop"),
1497 + MIB_DESC(1, MT7621_STATS_TCRC, "TxCRC"),
1498 + MIB_DESC(1, MT7621_STATS_TUPC, "TxUni"),
1499 + MIB_DESC(1, MT7621_STATS_TMPC, "TxMulti"),
1500 + MIB_DESC(1, MT7621_STATS_TBPC, "TxBroad"),
1501 + MIB_DESC(1, MT7621_STATS_TCEC, "TxCollision"),
1502 + MIB_DESC(1, MT7621_STATS_TSCEC, "TxSingleCol"),
1503 + MIB_DESC(1, MT7621_STATS_TMCEC, "TxMultiCol"),
1504 + MIB_DESC(1, MT7621_STATS_TDEC, "TxDefer"),
1505 + MIB_DESC(1, MT7621_STATS_TLCEC, "TxLateCol"),
1506 + MIB_DESC(1, MT7621_STATS_TXCEC, "TxExcCol"),
1507 + MIB_DESC(1, MT7621_STATS_TPPC, "TxPause"),
1508 + MIB_DESC(1, MT7621_STATS_TL64PC, "Tx64Byte"),
1509 + MIB_DESC(1, MT7621_STATS_TL65PC, "Tx65Byte"),
1510 + MIB_DESC(1, MT7621_STATS_TL128PC, "Tx128Byte"),
1511 + MIB_DESC(1, MT7621_STATS_TL256PC, "Tx256Byte"),
1512 + MIB_DESC(1, MT7621_STATS_TL512PC, "Tx512Byte"),
1513 + MIB_DESC(1, MT7621_STATS_TL1024PC, "Tx1024Byte"),
1514 + MIB_DESC(2, MT7621_STATS_TOC, "TxByte"),
1515 + MIB_DESC(1, MT7621_STATS_RDPC, "RxDrop"),
1516 + MIB_DESC(1, MT7621_STATS_RFPC, "RxFiltered"),
1517 + MIB_DESC(1, MT7621_STATS_RUPC, "RxUni"),
1518 + MIB_DESC(1, MT7621_STATS_RMPC, "RxMulti"),
1519 + MIB_DESC(1, MT7621_STATS_RBPC, "RxBroad"),
1520 + MIB_DESC(1, MT7621_STATS_RAEPC, "RxAlignErr"),
1521 + MIB_DESC(1, MT7621_STATS_RCEPC, "RxCRC"),
1522 + MIB_DESC(1, MT7621_STATS_RUSPC, "RxUnderSize"),
1523 + MIB_DESC(1, MT7621_STATS_RFEPC, "RxFragment"),
1524 + MIB_DESC(1, MT7621_STATS_ROSPC, "RxOverSize"),
1525 + MIB_DESC(1, MT7621_STATS_RJEPC, "RxJabber"),
1526 + MIB_DESC(1, MT7621_STATS_RPPC, "RxPause"),
1527 + MIB_DESC(1, MT7621_STATS_RL64PC, "Rx64Byte"),
1528 + MIB_DESC(1, MT7621_STATS_RL65PC, "Rx65Byte"),
1529 + MIB_DESC(1, MT7621_STATS_RL128PC, "Rx128Byte"),
1530 + MIB_DESC(1, MT7621_STATS_RL256PC, "Rx256Byte"),
1531 + MIB_DESC(1, MT7621_STATS_RL512PC, "Rx512Byte"),
1532 + MIB_DESC(1, MT7621_STATS_RL1024PC, "Rx1024Byte"),
1533 + MIB_DESC(2, MT7621_STATS_ROC, "RxByte"),
1534 + MIB_DESC(1, MT7621_STATS_RDPC_CTRL, "RxCtrlDrop"),
1535 + MIB_DESC(1, MT7621_STATS_RDPC_ING, "RxIngDrop"),
1536 + MIB_DESC(1, MT7621_STATS_RDPC_ARL, "RxARLDrop")
1540 + /* Global attributes. */
1541 + MT7530_ATTR_ENABLE_VLAN,
1544 +struct mt7530_port_entry {
1548 +struct mt7530_vlan_entry {
1554 +struct mt7530_priv {
1555 + void __iomem *base;
1556 + struct mii_bus *bus;
1557 + struct switch_dev swdev;
1559 + bool global_vlan_enable;
1560 + struct mt7530_vlan_entry vlan_entries[MT7530_NUM_VLANS];
1561 + struct mt7530_port_entry port_entries[MT7530_NUM_PORTS];
1564 +struct mt7530_mapping {
1566 + u16 pvids[MT7530_NUM_PORTS];
1567 + u8 members[MT7530_NUM_VLANS];
1568 + u8 etags[MT7530_NUM_VLANS];
1569 + u16 vids[MT7530_NUM_VLANS];
1570 +} mt7530_defaults[] = {
1573 + .pvids = { 1, 1, 1, 1, 2, 1, 1 },
1574 + .members = { 0, 0x6f, 0x50 },
1575 + .etags = { 0, 0x40, 0x40 },
1576 + .vids = { 0, 1, 2 },
1579 + .pvids = { 2, 1, 1, 1, 1, 1, 1 },
1580 + .members = { 0, 0x7e, 0x41 },
1581 + .etags = { 0, 0x40, 0x40 },
1582 + .vids = { 0, 1, 2 },
1586 +struct mt7530_mapping*
1587 +mt7530_find_mapping(struct device_node *np)
1592 + if (of_property_read_string(np, "mediatek,portmap", &map))
1595 + for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
1596 + if (!strcmp(map, mt7530_defaults[i].name))
1597 + return &mt7530_defaults[i];
1603 +mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
1607 + for (i = 0; i < MT7530_NUM_PORTS; i++)
1608 + mt7530->port_entries[i].pvid = map->pvids[i];
1610 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
1611 + mt7530->vlan_entries[i].member = map->members[i];
1612 + mt7530->vlan_entries[i].etags = map->etags[i];
1613 + mt7530->vlan_entries[i].vid = map->vids[i];
1618 +mt7530_reset_switch(struct switch_dev *dev)
1620 + struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
1623 + memset(eth->port_entries, 0, sizeof(eth->port_entries));
1624 + memset(eth->vlan_entries, 0, sizeof(eth->vlan_entries));
1626 + /* set default vid of each vlan to the same number of vlan, so the vid
1627 + * won't need be set explicitly.
1629 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
1630 + eth->vlan_entries[i].vid = i;
1637 +mt7530_get_vlan_enable(struct switch_dev *dev,
1638 + const struct switch_attr *attr,
1639 + struct switch_val *val)
1641 + struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
1643 + val->value.i = eth->global_vlan_enable;
1649 +mt7530_set_vlan_enable(struct switch_dev *dev,
1650 + const struct switch_attr *attr,
1651 + struct switch_val *val)
1653 + struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
1655 + eth->global_vlan_enable = val->value.i != 0;
1661 +mt7530_r32(struct mt7530_priv *eth, u32 reg)
1667 + mdiobus_write(eth->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
1668 + low = mdiobus_read(eth->bus, 0x1f, (reg >> 2) & 0xf);
1669 + high = mdiobus_read(eth->bus, 0x1f, 0x10);
1671 + return (high << 16) | (low & 0xffff);
1674 + val = ioread32(eth->base + reg);
1675 + pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
1681 +mt7530_w32(struct mt7530_priv *eth, u32 reg, u32 val)
1684 + mdiobus_write(eth->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
1685 + mdiobus_write(eth->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
1686 + mdiobus_write(eth->bus, 0x1f, 0x10, val >> 16);
1690 + pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
1691 + iowrite32(val, eth->base + reg);
1695 +mt7530_vtcr(struct mt7530_priv *eth, u32 cmd, u32 val)
1699 + mt7530_w32(eth, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
1701 + for (i = 0; i < 20; i++) {
1702 + u32 val = mt7530_r32(eth, REG_ESW_VLAN_VTCR);
1704 + if ((val & BIT(31)) == 0)
1710 + printk("mt7530: vtcr timeout\n");
1714 +mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
1716 + struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
1718 + if (port >= MT7530_NUM_PORTS)
1721 + *val = mt7530_r32(eth, REG_ESW_PORT_PPBV1(port));
1728 +mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
1730 + struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
1732 + if (port >= MT7530_NUM_PORTS)
1735 + if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
1738 + eth->port_entries[port].pvid = pvid;
1744 +mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1746 + struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
1753 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
1756 + mt7530_vtcr(eth, 0, val->port_vlan);
1758 + member = mt7530_r32(eth, REG_ESW_VLAN_VAWD1);
1762 + etags = mt7530_r32(eth, REG_ESW_VLAN_VAWD2);
1764 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
1765 + struct switch_port *p;
1768 + if (!(member & BIT(i)))
1771 + p = &val->value.ports[val->len++];
1774 + etag = (etags >> (i * 2)) & 0x3;
1776 + if (etag == ETAG_CTRL_TAG)
1777 + p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
1778 + else if (etag != ETAG_CTRL_UNTAG)
1779 + printk("vlan egress tag control neither untag nor tag.\n");
1786 +mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1788 + struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
1793 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
1794 + val->len > MT7530_NUM_PORTS)
1797 + for (i = 0; i < val->len; i++) {
1798 + struct switch_port *p = &val->value.ports[i];
1800 + if (p->id >= MT7530_NUM_PORTS)
1803 + member |= BIT(p->id);
1805 + if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
1806 + etags |= BIT(p->id);
1808 + eth->vlan_entries[val->port_vlan].member = member;
1809 + eth->vlan_entries[val->port_vlan].etags = etags;
1815 +mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1816 + struct switch_val *val)
1818 + struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
1822 + vlan = val->port_vlan;
1823 + vid = (u16)val->value.i;
1825 + if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
1828 + if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
1831 + eth->vlan_entries[vlan].vid = vid;
1836 +mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1837 + struct switch_val *val)
1839 + struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
1843 + vlan = val->port_vlan;
1845 + vid = mt7530_r32(eth, REG_ESW_VLAN_VTIM(vlan));
1850 + val->value.i = vid;
1855 +mt7530_apply_config(struct switch_dev *dev)
1857 + struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
1862 + if (!eth->global_vlan_enable) {
1863 + for (i = 0; i < MT7530_NUM_PORTS; i++)
1864 + mt7530_w32(eth, REG_ESW_PORT_PCR(i), 0x00ff0000);
1866 + for (i = 0; i < MT7530_NUM_PORTS; i++)
1867 + mt7530_w32(eth, REG_ESW_PORT_PVC(i), 0x810000c0);
1872 + /* set all ports as security mode */
1873 + for (i = 0; i < MT7530_NUM_PORTS; i++)
1874 + mt7530_w32(eth, REG_ESW_PORT_PCR(i), 0x00ff0003);
1876 + /* check if a port is used in tag/untag vlan egress mode */
1880 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
1881 + u8 member = eth->vlan_entries[i].member;
1882 + u8 etags = eth->vlan_entries[i].etags;
1887 + for (j = 0; j < MT7530_NUM_PORTS; j++) {
1888 + if (!(member & BIT(j)))
1891 + if (etags & BIT(j))
1892 + tag_ports |= 1u << j;
1894 + untag_ports |= 1u << j;
1898 + /* set all untag-only ports as transparent and the rest as user port */
1899 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
1900 + u32 pvc_mode = 0x81000000;
1902 + if (untag_ports & BIT(i) && !(tag_ports & BIT(i)))
1903 + pvc_mode = 0x810000c0;
1905 + mt7530_w32(eth, REG_ESW_PORT_PVC(i), pvc_mode);
1908 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
1909 + u16 vid = eth->vlan_entries[i].vid;
1910 + u8 member = eth->vlan_entries[i].member;
1911 + u8 etags = eth->vlan_entries[i].etags;
1915 + val = mt7530_r32(eth, REG_ESW_VLAN_VTIM(i));
1921 + val |= (vid << 12);
1923 + mt7530_w32(eth, REG_ESW_VLAN_VTIM(i), val);
1925 + /* vlan port membership */
1927 + mt7530_w32(eth, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
1928 + REG_ESW_VLAN_VAWD1_VTAG_EN | (member << 16) |
1929 + REG_ESW_VLAN_VAWD1_VALID);
1931 + mt7530_w32(eth, REG_ESW_VLAN_VAWD1, 0);
1935 + for (j = 0; j < MT7530_NUM_PORTS; j++) {
1936 + if (etags & BIT(j))
1937 + val |= ETAG_CTRL_TAG << (j * 2);
1939 + val |= ETAG_CTRL_UNTAG << (j * 2);
1941 + mt7530_w32(eth, REG_ESW_VLAN_VAWD2, val);
1943 + /* write to vlan table */
1944 + mt7530_vtcr(eth, 1, i);
1947 + /* Port Default PVID */
1948 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
1950 + val = mt7530_r32(eth, REG_ESW_PORT_PPBV1(i));
1952 + val |= eth->port_entries[i].pvid;
1953 + mt7530_w32(eth, REG_ESW_PORT_PPBV1(i), val);
1960 +mt7530_get_port_link(struct switch_dev *dev, int port,
1961 + struct switch_port_link *link)
1963 + struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
1966 + if (port < 0 || port >= MT7530_NUM_PORTS)
1969 + pmsr = mt7530_r32(eth, 0x3008 + (0x100 * port));
1971 + link->link = pmsr & 1;
1972 + link->duplex = (pmsr >> 1) & 1;
1973 + speed = (pmsr >> 2) & 3;
1977 + link->speed = SWITCH_PORT_SPEED_10;
1980 + link->speed = SWITCH_PORT_SPEED_100;
1983 + case 3: /* forced gige speed can be 2 or 3 */
1984 + link->speed = SWITCH_PORT_SPEED_1000;
1987 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1994 +static const struct switch_attr mt7530_global[] = {
1996 + .type = SWITCH_TYPE_INT,
1997 + .name = "enable_vlan",
1998 + .description = "VLAN mode (1:enabled)",
2000 + .id = MT7530_ATTR_ENABLE_VLAN,
2001 + .get = mt7530_get_vlan_enable,
2002 + .set = mt7530_set_vlan_enable,
2006 +static u64 get_mib_counter(struct mt7530_priv *eth, int i, int port)
2008 + unsigned int port_base;
2011 + port_base = MT7621_MIB_COUNTER_BASE +
2012 + MT7621_MIB_COUNTER_PORT_OFFSET * port;
2014 + t = mt7530_r32(eth, port_base + mt7621_mibs[i].offset);
2015 + if (mt7621_mibs[i].size == 2) {
2018 + hi = mt7530_r32(eth, port_base + mt7621_mibs[i].offset + 4);
2025 +static int mt7621_sw_get_port_mib(struct switch_dev *dev,
2026 + const struct switch_attr *attr,
2027 + struct switch_val *val)
2029 + static char buf[4096];
2030 + struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
2033 + if (val->port_vlan >= MT7530_NUM_PORTS)
2036 + len += snprintf(buf + len, sizeof(buf) - len,
2037 + "Port %d MIB counters\n", val->port_vlan);
2039 + for (i = 0; i < sizeof(mt7621_mibs) / sizeof(*mt7621_mibs); ++i) {
2041 + len += snprintf(buf + len, sizeof(buf) - len,
2042 + "%-11s: ", mt7621_mibs[i].name);
2043 + counter = get_mib_counter(eth, i, val->port_vlan);
2044 + len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
2048 + val->value.s = buf;
2053 +static const struct switch_attr mt7621_port[] = {
2055 + .type = SWITCH_TYPE_STRING,
2057 + .description = "Get MIB counters for port",
2058 + .get = mt7621_sw_get_port_mib,
2063 +static const struct switch_attr mt7530_port[] = {
2066 +static const struct switch_attr mt7530_vlan[] = {
2068 + .type = SWITCH_TYPE_INT,
2070 + .description = "VLAN ID (0-4094)",
2071 + .set = mt7530_set_vid,
2072 + .get = mt7530_get_vid,
2077 +static const struct switch_dev_ops mt7621_ops = {
2079 + .attr = mt7530_global,
2080 + .n_attr = ARRAY_SIZE(mt7530_global),
2083 + .attr = mt7621_port,
2084 + .n_attr = ARRAY_SIZE(mt7621_port),
2087 + .attr = mt7530_vlan,
2088 + .n_attr = ARRAY_SIZE(mt7530_vlan),
2090 + .get_vlan_ports = mt7530_get_vlan_ports,
2091 + .set_vlan_ports = mt7530_set_vlan_ports,
2092 + .get_port_pvid = mt7530_get_port_pvid,
2093 + .set_port_pvid = mt7530_set_port_pvid,
2094 + .get_port_link = mt7530_get_port_link,
2095 + .apply_config = mt7530_apply_config,
2096 + .reset_switch = mt7530_reset_switch,
2099 +static const struct switch_dev_ops mt7530_ops = {
2101 + .attr = mt7530_global,
2102 + .n_attr = ARRAY_SIZE(mt7530_global),
2105 + .attr = mt7530_port,
2106 + .n_attr = ARRAY_SIZE(mt7530_port),
2109 + .attr = mt7530_vlan,
2110 + .n_attr = ARRAY_SIZE(mt7530_vlan),
2112 + .get_vlan_ports = mt7530_get_vlan_ports,
2113 + .set_vlan_ports = mt7530_set_vlan_ports,
2114 + .get_port_pvid = mt7530_get_port_pvid,
2115 + .set_port_pvid = mt7530_set_port_pvid,
2116 + .get_port_link = mt7530_get_port_link,
2117 + .apply_config = mt7530_apply_config,
2118 + .reset_switch = mt7530_reset_switch,
2122 +mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
2124 + struct switch_dev *swdev;
2125 + struct mt7530_priv *mt7530;
2126 + struct mt7530_mapping *map;
2129 + mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
2133 + mt7530->base = base;
2134 + mt7530->bus = bus;
2135 + mt7530->global_vlan_enable = vlan;
2137 + swdev = &mt7530->swdev;
2139 + swdev->alias = "mt7530";
2140 + swdev->name = "mt7530";
2141 + } else if (IS_ENABLED(CONFIG_MACH_MT7623)) {
2142 + swdev->alias = "mt7623";
2143 + swdev->name = "mt7623";
2144 + } else if (IS_ENABLED(CONFIG_SOC_MT7621)) {
2145 + swdev->alias = "mt7621";
2146 + swdev->name = "mt7621";
2148 + swdev->alias = "mt7620";
2149 + swdev->name = "mt7620";
2151 + swdev->cpu_port = MT7530_CPU_PORT;
2152 + swdev->ports = MT7530_NUM_PORTS;
2153 + swdev->vlans = MT7530_NUM_VLANS;
2154 + if (IS_ENABLED(CONFIG_SOC_MT7621) || IS_ENABLED(CONFIG_MACH_MT7623))
2155 + swdev->ops = &mt7621_ops;
2157 + swdev->ops = &mt7530_ops;
2159 + ret = register_switch(swdev, NULL);
2161 + dev_err(dev, "failed to register mt7530\n");
2165 + mt7530_reset_switch(swdev);
2167 + map = mt7530_find_mapping(dev->of_node);
2169 + mt7530_apply_mapping(mt7530, map);
2170 + mt7530_apply_config(swdev);
2173 + if (!(IS_ENABLED(CONFIG_SOC_MT7621) || IS_ENABLED(CONFIG_MACH_MT7623)) && bus && mt7530_r32(mt7530, REG_HWTRAP) != 0x1117edf) {
2174 + dev_info(dev, "fixing up MHWTRAP register - bootloader probably played with it\n");
2175 + mt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);
2177 + dev_info(dev, "loaded %s driver\n", swdev->name);
2181 diff --git a/drivers/net/ethernet/mediatek/mt7530.h b/drivers/net/ethernet/mediatek/mt7530.h
2182 new file mode 100644
2183 index 0000000..1fc8c62
2185 +++ b/drivers/net/ethernet/mediatek/mt7530.h
2188 + * This program is free software; you can redistribute it and/or
2189 + * modify it under the terms of the GNU General Public License
2190 + * as published by the Free Software Foundation; either version 2
2191 + * of the License, or (at your option) any later version.
2193 + * This program is distributed in the hope that it will be useful,
2194 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2195 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2196 + * GNU General Public License for more details.
2198 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
2201 +#ifndef _MT7530_H__
2202 +#define _MT7530_H__
2204 +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
2207 diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
2208 index ba3afa5..62058a2 100644
2209 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
2210 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
2213 #include "mtk_eth_soc.h"
2215 +/* the callback used by the driver core to bringup the switch */
2216 +int mtk_gsw_init(struct mtk_eth *eth);
2218 static int mtk_msg_level = -1;
2219 module_param_named(msg_level, mtk_msg_level, int, 0);
2220 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
2221 @@ -69,7 +72,7 @@ static int mtk_mdio_busy_wait(struct mtk_eth *eth)
2223 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
2225 - usleep_range(10, 20);
2226 +// usleep_range(10, 20);
2229 dev_err(eth->dev, "mdio: MDIO timeout\n");
2230 @@ -132,36 +135,20 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2232 static void mtk_phy_link_adjust(struct net_device *dev)
2236 struct mtk_mac *mac = netdev_priv(dev);
2237 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
2238 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
2239 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
2242 - switch (mac->phy_dev->speed) {
2244 - mcr |= MAC_MCR_SPEED_1000;
2247 - mcr |= MAC_MCR_SPEED_100;
2251 - if (mac->phy_dev->link)
2252 - mcr |= MAC_MCR_FORCE_LINK;
2254 - if (mac->phy_dev->duplex)
2255 - mcr |= MAC_MCR_FORCE_DPX;
2257 - if (mac->phy_dev->pause)
2258 - mcr |= MAC_MCR_FORCE_RX_FC | MAC_MCR_FORCE_TX_FC;
2260 + mcr |= MAC_MCR_SPEED_1000;
2261 + mcr |= MAC_MCR_FORCE_LINK;
2262 + mcr |= MAC_MCR_FORCE_DPX;
2263 + mcr |= MAC_MCR_FORCE_RX_FC | MAC_MCR_FORCE_TX_FC;
2264 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
2266 - if (mac->phy_dev->link)
2267 - netif_carrier_on(dev);
2269 - netif_carrier_off(dev);
2273 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
2274 @@ -193,7 +180,7 @@ static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
2277 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
2278 - mac->id, phydev_name(phydev), phydev->phy_id,
2279 + mac->id, dev_name(&phydev->dev), phydev->phy_id,
2282 mac->phy_dev = phydev;
2283 @@ -634,7 +621,6 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
2285 spin_unlock_irqrestore(ð->page_lock, flags);
2287 - netdev_sent_queue(dev, skb->len);
2288 skb_tx_timestamp(skb);
2290 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
2291 @@ -882,7 +868,6 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
2292 for (i = 0; i < MTK_MAC_COUNT; i++) {
2293 if (!eth->netdev[i] || !done[i])
2295 - netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
2299 @@ -1249,6 +1234,8 @@ static int mtk_open(struct net_device *dev)
2300 phy_start(mac->phy_dev);
2301 netif_start_queue(dev);
2303 + netif_carrier_on(dev);
2308 @@ -1281,6 +1268,7 @@ static int mtk_stop(struct net_device *dev)
2309 struct mtk_mac *mac = netdev_priv(dev);
2310 struct mtk_eth *eth = mac->hw;
2312 + netif_carrier_off(dev);
2313 netif_tx_disable(dev);
2314 phy_stop(mac->phy_dev);
2316 @@ -1326,6 +1314,7 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
2317 /* Enable RX VLan Offloading */
2318 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
2320 + mtk_gsw_init(eth);
2321 err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
2322 dev_name(eth->dev), eth);
2324 @@ -1358,6 +1347,8 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
2325 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2328 + mt7623_gsw_config(eth);
2333 @@ -1464,11 +1455,13 @@ static int mtk_set_settings(struct net_device *dev,
2335 struct mtk_mac *mac = netdev_priv(dev);
2337 - if (cmd->phy_address != mac->phy_dev->mdio.addr) {
2338 - mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
2339 - cmd->phy_address);
2340 - if (!mac->phy_dev)
2341 + if (cmd->phy_address != mac->phy_dev->addr) {
2342 + if (mac->hw->mii_bus->phy_map[cmd->phy_address]) {
2344 + mac->hw->mii_bus->phy_map[cmd->phy_address];
2350 return phy_ethtool_sset(mac->phy_dev, cmd);
2351 @@ -1561,7 +1554,6 @@ static void mtk_get_ethtool_stats(struct net_device *dev,
2352 data_src = (u64*)hwstats;
2354 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2356 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2357 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2358 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2359 @@ -1733,6 +1725,9 @@ static int mtk_probe(struct platform_device *pdev)
2360 clk_prepare_enable(eth->clk_gp1);
2361 clk_prepare_enable(eth->clk_gp2);
2363 + eth->switch_np = of_parse_phandle(pdev->dev.of_node,
2364 + "mediatek,switch", 0);
2366 eth->dev = &pdev->dev;
2367 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
2369 diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
2370 index 48a5292..d737d61 100644
2371 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
2372 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
2373 @@ -389,6 +389,9 @@ struct mtk_eth {
2374 struct clk *clk_gp1;
2375 struct clk *clk_gp2;
2376 struct mii_bus *mii_bus;
2378 + struct device_node *switch_np;
2382 /* struct mtk_mac - the structure that holds the info about the MACs of the
2383 @@ -418,4 +421,6 @@ void mtk_stats_update_mac(struct mtk_mac *mac);
2384 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
2385 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
2387 +int mt7623_gsw_config(struct mtk_eth *eth);
2389 #endif /* MTK_ETH_H */
2390 diff --git a/lib/dynamic_queue_limits.c b/lib/dynamic_queue_limits.c
2391 index f346715..b04f8e6 100644
2392 --- a/lib/dynamic_queue_limits.c
2393 +++ b/lib/dynamic_queue_limits.c
2394 @@ -23,8 +23,10 @@ void dql_completed(struct dql *dql, unsigned int count)
2395 num_queued = ACCESS_ONCE(dql->num_queued);
2397 /* Can't complete more than what's in queue */
2398 - BUG_ON(count > num_queued - dql->num_completed);
2400 + if (count > num_queued - dql->num_completed) {
2401 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
2404 completed = dql->num_completed + count;
2406 ovlimit = POSDIFF(num_queued - dql->num_completed, limit);