1 From 1ecb38eabd90efe93957d0a822a167560c39308a Mon Sep 17 00:00:00 2001
2 From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
3 Date: Wed, 20 Mar 2019 16:19:51 +0800
4 Subject: [PATCH 6/6] spi: spi-mem: MediaTek: Add SPI NAND Flash interface
5 driver for MediaTek MT7622
7 Change-Id: I3e78406bb9b46b0049d3988a5c71c7069e4f809c
8 Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
10 drivers/spi/Kconfig | 9 +
11 drivers/spi/Makefile | 1 +
12 drivers/spi/spi-mtk-snfi.c | 1183 ++++++++++++++++++++++++++++++++++++
13 3 files changed, 1193 insertions(+)
14 create mode 100644 drivers/spi/spi-mtk-snfi.c
16 --- a/drivers/spi/Makefile
17 +++ b/drivers/spi/Makefile
18 @@ -67,6 +67,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mp
19 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
20 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
21 obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
22 +obj-$(CONFIG_SPI_MTK_SNFI) += spi-mtk-snfi.o
23 obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
24 obj-$(CONFIG_SPI_MTK_NOR) += spi-mtk-nor.o
25 obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
26 --- a/drivers/spi/Kconfig
27 +++ b/drivers/spi/Kconfig
28 @@ -495,6 +495,15 @@ config SPI_MT65XX
29 say Y or M here.If you are not sure, say N.
30 SPI drivers for Mediatek MT65XX and MT81XX series ARM SoCs.
33 + tristate "MediaTek SPI NAND interface"
36 + This selects the SPI NAND FLASH interface(SNFI),
37 + which could be found on MediaTek Soc.
38 + Say Y or M here.If you are not sure, say N.
39 + Note Parallel Nand and SPI NAND is alternative on MediaTek SoCs.
42 tristate "MediaTek MT7621 SPI Controller"
43 depends on RALINK || COMPILE_TEST
45 +++ b/drivers/spi/spi-mtk-snfi.c
47 +// SPDX-License-Identifier: GPL-2.0
49 + * Driver for MediaTek SPI Nand interface
51 + * Copyright (C) 2018 MediaTek Inc.
52 + * Authors: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
56 +#include <linux/clk.h>
57 +#include <linux/delay.h>
58 +#include <linux/dma-mapping.h>
59 +#include <linux/interrupt.h>
60 +#include <linux/iopoll.h>
61 +#include <linux/mtd/mtd.h>
62 +#include <linux/mtd/mtk_ecc.h>
63 +#include <linux/mtd/spinand.h>
64 +#include <linux/module.h>
65 +#include <linux/of.h>
66 +#include <linux/of_device.h>
67 +#include <linux/platform_device.h>
68 +#include <linux/spi/spi.h>
69 +#include <linux/spi/spi-mem.h>
71 +/* NAND controller register definition */
73 +#define NFI_CNFG 0x00
74 +#define CNFG_DMA BIT(0)
75 +#define CNFG_READ_EN BIT(1)
76 +#define CNFG_DMA_BURST_EN BIT(2)
77 +#define CNFG_BYTE_RW BIT(6)
78 +#define CNFG_HW_ECC_EN BIT(8)
79 +#define CNFG_AUTO_FMT_EN BIT(9)
80 +#define CNFG_OP_PROGRAM (3UL << 12)
81 +#define CNFG_OP_CUST (6UL << 12)
82 +#define NFI_PAGEFMT 0x04
83 +#define PAGEFMT_512 0
86 +#define PAGEFMT_FDM_SHIFT 8
87 +#define PAGEFMT_FDM_ECC_SHIFT 12
89 +#define CON_FIFO_FLUSH BIT(0)
90 +#define CON_NFI_RST BIT(1)
91 +#define CON_BRD BIT(8)
92 +#define CON_BWR BIT(9)
93 +#define CON_SEC_SHIFT 12
94 +#define NFI_INTR_EN 0x10
95 +#define INTR_AHB_DONE_EN BIT(6)
96 +#define NFI_INTR_STA 0x14
99 +#define STA_EMP_PAGE BIT(12)
100 +#define NAND_FSM_MASK (0x1f << 24)
101 +#define NFI_FSM_MASK (0xf << 16)
102 +#define NFI_ADDRCNTR 0x70
103 +#define CNTR_MASK GENMASK(16, 12)
104 +#define ADDRCNTR_SEC_SHIFT 12
105 +#define ADDRCNTR_SEC(val) \
106 + (((val) & CNTR_MASK) >> ADDRCNTR_SEC_SHIFT)
107 +#define NFI_STRADDR 0x80
108 +#define NFI_BYTELEN 0x84
109 +#define NFI_CSEL 0x90
110 +#define NFI_FDML(x) (0xa0 + (x) * sizeof(u32) * 2)
111 +#define NFI_FDMM(x) (0xa4 + (x) * sizeof(u32) * 2)
112 +#define NFI_MASTER_STA 0x224
113 +#define MASTER_STA_MASK 0x0fff
114 +/* NFI_SPI control */
115 +#define SNFI_MAC_OUTL 0x504
116 +#define SNFI_MAC_INL 0x508
117 +#define SNFI_RD_CTL2 0x510
118 +#define RD_CMD_MASK 0x00ff
119 +#define RD_DUMMY_SHIFT 8
120 +#define SNFI_RD_CTL3 0x514
121 +#define RD_ADDR_MASK 0xffff
122 +#define SNFI_MISC_CTL 0x538
123 +#define RD_MODE_X2 BIT(16)
124 +#define RD_MODE_X4 (2UL << 16)
125 +#define RD_QDUAL_IO (4UL << 16)
126 +#define RD_MODE_MASK (7UL << 16)
127 +#define RD_CUSTOM_EN BIT(6)
128 +#define WR_CUSTOM_EN BIT(7)
129 +#define WR_X4_EN BIT(20)
130 +#define SW_RST BIT(28)
131 +#define SNFI_MISC_CTL2 0x53c
132 +#define WR_LEN_SHIFT 16
133 +#define SNFI_PG_CTL1 0x524
134 +#define WR_LOAD_CMD_SHIFT 8
135 +#define SNFI_PG_CTL2 0x528
136 +#define WR_LOAD_ADDR_MASK 0xffff
137 +#define SNFI_MAC_CTL 0x500
138 +#define MAC_WIP BIT(0)
139 +#define MAC_WIP_READY BIT(1)
140 +#define MAC_TRIG BIT(2)
141 +#define MAC_EN BIT(3)
142 +#define MAC_SIO_SEL BIT(4)
143 +#define SNFI_STA_CTL1 0x550
144 +#define SPI_STATE_IDLE 0xf
145 +#define SNFI_CNFG 0x55c
146 +#define SNFI_MODE_EN BIT(0)
147 +#define SNFI_GPRAM_DATA 0x800
148 +#define SNFI_GPRAM_MAX_LEN 16
150 +/* Dummy command trigger NFI to spi mode */
151 +#define NAND_CMD_DUMMYREAD 0x00
152 +#define NAND_CMD_DUMMYPROG 0x80
154 +#define MTK_TIMEOUT 500000
155 +#define MTK_RESET_TIMEOUT 1000000
156 +#define MTK_SNFC_MIN_SPARE 16
157 +#define KB(x) ((x) * 1024UL)
160 + * supported spare size of each IP.
161 + * order should be the same with the spare size bitfiled defination of
162 + * register NFI_PAGEFMT.
164 +static const u8 spare_size_mt7622[] = {
168 +struct mtk_snfi_caps {
169 + const u8 *spare_size;
173 + u8 nand_fdm_ecc_size;
174 + u8 ecc_parity_bits;
175 + u8 pageformat_spare_shift;
179 +struct mtk_snfi_bad_mark_ctl {
180 + void (*bm_swap)(struct spi_mem *mem, u8 *buf, int raw);
185 +struct mtk_snfi_nand_chip {
186 + struct mtk_snfi_bad_mark_ctl bad_mark;
187 + u32 spare_per_sector;
190 +struct mtk_snfi_clk {
191 + struct clk *nfi_clk;
192 + struct clk *spi_clk;
196 + const struct mtk_snfi_caps *caps;
197 + struct mtk_snfi_nand_chip snfi_nand;
198 + struct mtk_snfi_clk clk;
199 + struct mtk_ecc_config ecc_cfg;
200 + struct mtk_ecc *ecc;
201 + struct completion done;
202 + struct device *dev;
204 + void __iomem *regs;
209 +static inline u8 *oob_ptr(struct spi_mem *mem, int i)
211 + struct spinand_device *spinand = spi_mem_get_drvdata(mem);
212 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
213 + struct mtk_snfi_nand_chip *snfi_nand = &snfi->snfi_nand;
216 + /* map the sector's FDM data to free oob:
217 + * the beginning of the oob area stores the FDM data of bad mark
220 + if (i < snfi_nand->bad_mark.sec)
221 + poi = spinand->oobbuf + (i + 1) * snfi->caps->nand_fdm_size;
222 + else if (i == snfi_nand->bad_mark.sec)
223 + poi = spinand->oobbuf;
225 + poi = spinand->oobbuf + i * snfi->caps->nand_fdm_size;
230 +static inline int mtk_data_len(struct spi_mem *mem)
232 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
233 + struct mtk_snfi_nand_chip *snfi_nand = &snfi->snfi_nand;
235 + return snfi->caps->nand_sec_size + snfi_nand->spare_per_sector;
238 +static inline u8 *mtk_oob_ptr(struct spi_mem *mem,
239 + const u8 *p, int i)
241 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
243 + return (u8 *)p + i * mtk_data_len(mem) + snfi->caps->nand_sec_size;
246 +static void mtk_snfi_bad_mark_swap(struct spi_mem *mem,
249 + struct spinand_device *spinand = spi_mem_get_drvdata(mem);
250 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
251 + struct mtk_snfi_nand_chip *snfi_nand = &snfi->snfi_nand;
252 + u32 bad_pos = snfi_nand->bad_mark.pos;
255 + bad_pos += snfi_nand->bad_mark.sec * mtk_data_len(mem);
257 + bad_pos += snfi_nand->bad_mark.sec * snfi->caps->nand_sec_size;
259 + swap(spinand->oobbuf[0], buf[bad_pos]);
262 +static void mtk_snfi_set_bad_mark_ctl(struct mtk_snfi_bad_mark_ctl *bm_ctl,
263 + struct spi_mem *mem)
265 + struct spinand_device *spinand = spi_mem_get_drvdata(mem);
266 + struct mtd_info *mtd = spinand_to_mtd(spinand);
268 + bm_ctl->bm_swap = mtk_snfi_bad_mark_swap;
269 + bm_ctl->sec = mtd->writesize / mtk_data_len(mem);
270 + bm_ctl->pos = mtd->writesize % mtk_data_len(mem);
273 +static void mtk_snfi_mac_enable(struct mtk_snfi *snfi)
277 + mac = readl(snfi->regs + SNFI_MAC_CTL);
278 + mac &= ~MAC_SIO_SEL;
281 + writel(mac, snfi->regs + SNFI_MAC_CTL);
284 +static int mtk_snfi_mac_trigger(struct mtk_snfi *snfi)
289 + mac = readl(snfi->regs + SNFI_MAC_CTL);
291 + writel(mac, snfi->regs + SNFI_MAC_CTL);
293 + ret = readl_poll_timeout_atomic(snfi->regs + SNFI_MAC_CTL, reg,
294 + reg & MAC_WIP_READY, 10,
297 + dev_err(snfi->dev, "polling wip ready for read timeout\n");
301 + ret = readl_poll_timeout_atomic(snfi->regs + SNFI_MAC_CTL, reg,
302 + !(reg & MAC_WIP), 10,
305 + dev_err(snfi->dev, "polling flash update timeout\n");
312 +static void mtk_snfi_mac_leave(struct mtk_snfi *snfi)
316 + mac = readl(snfi->regs + SNFI_MAC_CTL);
317 + mac &= ~(MAC_TRIG | MAC_EN | MAC_SIO_SEL);
318 + writel(mac, snfi->regs + SNFI_MAC_CTL);
321 +static int mtk_snfi_mac_op(struct mtk_snfi *snfi)
325 + mtk_snfi_mac_enable(snfi);
327 + ret = mtk_snfi_mac_trigger(snfi);
331 + mtk_snfi_mac_leave(snfi);
336 +static irqreturn_t mtk_snfi_irq(int irq, void *id)
338 + struct mtk_snfi *snfi = id;
341 + sta = readw(snfi->regs + NFI_INTR_STA);
342 + ien = readw(snfi->regs + NFI_INTR_EN);
347 + writew(~sta & ien, snfi->regs + NFI_INTR_EN);
348 + complete(&snfi->done);
350 + return IRQ_HANDLED;
353 +static int mtk_snfi_enable_clk(struct device *dev, struct mtk_snfi_clk *clk)
357 + ret = clk_prepare_enable(clk->nfi_clk);
359 + dev_err(dev, "failed to enable nfi clk\n");
363 + ret = clk_prepare_enable(clk->spi_clk);
365 + dev_err(dev, "failed to enable spi clk\n");
366 + clk_disable_unprepare(clk->nfi_clk);
373 +static void mtk_snfi_disable_clk(struct mtk_snfi_clk *clk)
375 + clk_disable_unprepare(clk->nfi_clk);
376 + clk_disable_unprepare(clk->spi_clk);
379 +static int mtk_snfi_reset(struct mtk_snfi *snfi)
384 + /* SW reset controller */
385 + val = readl(snfi->regs + SNFI_MISC_CTL) | SW_RST;
386 + writel(val, snfi->regs + SNFI_MISC_CTL);
388 + ret = readw_poll_timeout(snfi->regs + SNFI_STA_CTL1, val,
389 + !(val & SPI_STATE_IDLE), 50,
390 + MTK_RESET_TIMEOUT);
392 + dev_warn(snfi->dev, "spi state active in reset [0x%x] = 0x%x\n",
393 + SNFI_STA_CTL1, val);
397 + val = readl(snfi->regs + SNFI_MISC_CTL);
399 + writel(val, snfi->regs + SNFI_MISC_CTL);
401 + /* reset all registers and force the NFI master to terminate */
402 + writew(CON_FIFO_FLUSH | CON_NFI_RST, snfi->regs + NFI_CON);
403 + ret = readw_poll_timeout(snfi->regs + NFI_STA, val,
404 + !(val & (NFI_FSM_MASK | NAND_FSM_MASK)), 50,
405 + MTK_RESET_TIMEOUT);
407 + dev_warn(snfi->dev, "nfi active in reset [0x%x] = 0x%x\n",
415 +static int mtk_snfi_set_spare_per_sector(struct spinand_device *spinand,
416 + const struct mtk_snfi_caps *caps,
419 + struct mtd_info *mtd = spinand_to_mtd(spinand);
420 + const u8 *spare = caps->spare_size;
421 + u32 sectors, i, closest_spare = 0;
423 + sectors = mtd->writesize / caps->nand_sec_size;
424 + *sps = mtd->oobsize / sectors;
426 + if (*sps < MTK_SNFC_MIN_SPARE)
429 + for (i = 0; i < caps->num_spare_size; i++) {
430 + if (*sps >= spare[i] && spare[i] >= spare[closest_spare]) {
432 + if (*sps == spare[i])
437 + *sps = spare[closest_spare];
442 +static void mtk_snfi_read_fdm_data(struct spi_mem *mem,
445 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
446 + const struct mtk_snfi_caps *caps = snfi->caps;
451 + for (i = 0; i < sectors; i++) {
452 + oobptr = oob_ptr(mem, i);
453 + vall = readl(snfi->regs + NFI_FDML(i));
454 + valm = readl(snfi->regs + NFI_FDMM(i));
456 + for (j = 0; j < caps->nand_fdm_size; j++)
457 + oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);
461 +static void mtk_snfi_write_fdm_data(struct spi_mem *mem,
464 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
465 + const struct mtk_snfi_caps *caps = snfi->caps;
470 + for (i = 0; i < sectors; i++) {
471 + oobptr = oob_ptr(mem, i);
474 + for (j = 0; j < 8; j++) {
476 + vall |= (j < caps->nand_fdm_size ? oobptr[j] :
479 + valm |= (j < caps->nand_fdm_size ? oobptr[j] :
480 + 0xff) << ((j - 4) * 8);
482 + writel(vall, snfi->regs + NFI_FDML(i));
483 + writel(valm, snfi->regs + NFI_FDMM(i));
487 +static int mtk_snfi_update_ecc_stats(struct spi_mem *mem,
488 + u8 *buf, u32 sectors)
490 + struct spinand_device *spinand = spi_mem_get_drvdata(mem);
491 + struct mtd_info *mtd = spinand_to_mtd(spinand);
492 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
493 + struct mtk_ecc_stats stats;
496 + rc = readl(snfi->regs + NFI_STA) & STA_EMP_PAGE;
498 + memset(buf, 0xff, sectors * snfi->caps->nand_sec_size);
499 + for (i = 0; i < sectors; i++)
500 + memset(spinand->oobbuf, 0xff,
501 + snfi->caps->nand_fdm_size);
505 + mtk_ecc_get_stats(snfi->ecc, &stats, sectors);
506 + mtd->ecc_stats.corrected += stats.corrected;
507 + mtd->ecc_stats.failed += stats.failed;
512 +static int mtk_snfi_hw_runtime_config(struct spi_mem *mem)
514 + struct spinand_device *spinand = spi_mem_get_drvdata(mem);
515 + struct mtd_info *mtd = spinand_to_mtd(spinand);
516 + struct nand_device *nand = mtd_to_nanddev(mtd);
517 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
518 + const struct mtk_snfi_caps *caps = snfi->caps;
519 + struct mtk_snfi_nand_chip *snfi_nand = &snfi->snfi_nand;
520 + u32 fmt, spare, i = 0;
523 + ret = mtk_snfi_set_spare_per_sector(spinand, caps, &spare);
527 + /* calculate usable oob bytes for ecc parity data */
528 + snfi_nand->spare_per_sector = spare;
529 + spare -= caps->nand_fdm_size;
531 + nand->memorg.oobsize = snfi_nand->spare_per_sector
532 + * (mtd->writesize / caps->nand_sec_size);
533 + mtd->oobsize = nanddev_per_page_oobsize(nand);
535 + snfi->ecc_cfg.strength = (spare << 3) / caps->ecc_parity_bits;
536 + mtk_ecc_adjust_strength(snfi->ecc, &snfi->ecc_cfg.strength);
538 + switch (mtd->writesize) {
549 + dev_err(snfi->dev, "invalid page len: %d\n", mtd->writesize);
553 + /* Setup PageFormat */
554 + while (caps->spare_size[i] != snfi_nand->spare_per_sector) {
556 + if (i == (caps->num_spare_size - 1)) {
557 + dev_err(snfi->dev, "invalid spare size %d\n",
558 + snfi_nand->spare_per_sector);
563 + fmt |= i << caps->pageformat_spare_shift;
564 + fmt |= caps->nand_fdm_size << PAGEFMT_FDM_SHIFT;
565 + fmt |= caps->nand_fdm_ecc_size << PAGEFMT_FDM_ECC_SHIFT;
566 + writel(fmt, snfi->regs + NFI_PAGEFMT);
568 + snfi->ecc_cfg.len = caps->nand_sec_size + caps->nand_fdm_ecc_size;
570 + mtk_snfi_set_bad_mark_ctl(&snfi_nand->bad_mark, mem);
575 +static int mtk_snfi_read_from_cache(struct spi_mem *mem,
576 + const struct spi_mem_op *op, int oob_on)
578 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
579 + struct spinand_device *spinand = spi_mem_get_drvdata(mem);
580 + struct mtd_info *mtd = spinand_to_mtd(spinand);
581 + u32 sectors = mtd->writesize / snfi->caps->nand_sec_size;
582 + struct mtk_snfi_nand_chip *snfi_nand = &snfi->snfi_nand;
583 + u32 reg, len, col_addr = 0;
584 + int dummy_cycle, ret;
585 + dma_addr_t dma_addr;
587 + len = sectors * (snfi->caps->nand_sec_size
588 + + snfi_nand->spare_per_sector);
590 + dma_addr = dma_map_single(snfi->dev, snfi->buffer,
591 + len, DMA_FROM_DEVICE);
592 + ret = dma_mapping_error(snfi->dev, dma_addr);
594 + dev_err(snfi->dev, "dma mapping error\n");
598 + /* set Read cache command and dummy cycle */
599 + dummy_cycle = (op->dummy.nbytes << 3) >> (ffs(op->dummy.buswidth) - 1);
600 + reg = ((op->cmd.opcode & RD_CMD_MASK) |
601 + (dummy_cycle << RD_DUMMY_SHIFT));
602 + writel(reg, snfi->regs + SNFI_RD_CTL2);
604 + writel((col_addr & RD_ADDR_MASK), snfi->regs + SNFI_RD_CTL3);
606 + reg = readl(snfi->regs + SNFI_MISC_CTL);
607 + reg |= RD_CUSTOM_EN;
608 + reg &= ~(RD_MODE_MASK | WR_X4_EN);
610 + /* set data and addr buswidth */
611 + if (op->data.buswidth == 4)
613 + else if (op->data.buswidth == 2)
616 + if (op->addr.buswidth == 4 || op->addr.buswidth == 2)
617 + reg |= RD_QDUAL_IO;
618 + writel(reg, snfi->regs + SNFI_MISC_CTL);
620 + writel(len, snfi->regs + SNFI_MISC_CTL2);
621 + writew(sectors << CON_SEC_SHIFT, snfi->regs + NFI_CON);
622 + reg = readw(snfi->regs + NFI_CNFG);
623 + reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_DMA | CNFG_OP_CUST;
626 + reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN;
627 + writew(reg, snfi->regs + NFI_CNFG);
629 + snfi->ecc_cfg.mode = ECC_NFI_MODE;
630 + snfi->ecc_cfg.sectors = sectors;
631 + snfi->ecc_cfg.op = ECC_DECODE;
632 + ret = mtk_ecc_enable(snfi->ecc, &snfi->ecc_cfg);
634 + dev_err(snfi->dev, "ecc enable failed\n");
635 + /* clear NFI_CNFG */
636 + reg &= ~(CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_DMA |
637 + CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
638 + writew(reg, snfi->regs + NFI_CNFG);
642 + writew(reg, snfi->regs + NFI_CNFG);
645 + writel(lower_32_bits(dma_addr), snfi->regs + NFI_STRADDR);
646 + readw(snfi->regs + NFI_INTR_STA);
647 + writew(INTR_AHB_DONE_EN, snfi->regs + NFI_INTR_EN);
649 + init_completion(&snfi->done);
651 + /* set dummy command to trigger NFI enter SPI mode */
652 + writew(NAND_CMD_DUMMYREAD, snfi->regs + NFI_CMD);
653 + reg = readl(snfi->regs + NFI_CON) | CON_BRD;
654 + writew(reg, snfi->regs + NFI_CON);
656 + ret = wait_for_completion_timeout(&snfi->done, msecs_to_jiffies(500));
658 + dev_err(snfi->dev, "read ahb done timeout\n");
659 + writew(0, snfi->regs + NFI_INTR_EN);
664 + ret = readl_poll_timeout_atomic(snfi->regs + NFI_BYTELEN, reg,
665 + ADDRCNTR_SEC(reg) >= sectors, 10,
668 + dev_err(snfi->dev, "polling read byte len timeout\n");
672 + ret = mtk_ecc_wait_done(snfi->ecc, ECC_DECODE);
674 + dev_warn(snfi->dev, "wait ecc done timeout\n");
676 + mtk_snfi_update_ecc_stats(mem, snfi->buffer,
678 + mtk_snfi_read_fdm_data(mem, sectors);
686 + mtk_ecc_disable(snfi->ecc);
688 + dma_unmap_single(snfi->dev, dma_addr, len, DMA_FROM_DEVICE);
689 + writel(0, snfi->regs + NFI_CON);
690 + writel(0, snfi->regs + NFI_CNFG);
691 + reg = readl(snfi->regs + SNFI_MISC_CTL);
692 + reg &= ~RD_CUSTOM_EN;
693 + writel(reg, snfi->regs + SNFI_MISC_CTL);
698 +static int mtk_snfi_write_to_cache(struct spi_mem *mem,
699 + const struct spi_mem_op *op,
702 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
703 + struct spinand_device *spinand = spi_mem_get_drvdata(mem);
704 + struct mtd_info *mtd = spinand_to_mtd(spinand);
705 + u32 sectors = mtd->writesize / snfi->caps->nand_sec_size;
706 + struct mtk_snfi_nand_chip *snfi_nand = &snfi->snfi_nand;
707 + u32 reg, len, col_addr = 0;
708 + dma_addr_t dma_addr;
711 + len = sectors * (snfi->caps->nand_sec_size
712 + + snfi_nand->spare_per_sector);
714 + dma_addr = dma_map_single(snfi->dev, snfi->buffer, len,
716 + ret = dma_mapping_error(snfi->dev, dma_addr);
718 + dev_err(snfi->dev, "dma mapping error\n");
722 + /* set program load cmd and address */
723 + reg = (op->cmd.opcode << WR_LOAD_CMD_SHIFT);
724 + writel(reg, snfi->regs + SNFI_PG_CTL1);
725 + writel(col_addr & WR_LOAD_ADDR_MASK, snfi->regs + SNFI_PG_CTL2);
727 + reg = readl(snfi->regs + SNFI_MISC_CTL);
728 + reg |= WR_CUSTOM_EN;
729 + reg &= ~(RD_MODE_MASK | WR_X4_EN);
731 + if (op->data.buswidth == 4)
733 + writel(reg, snfi->regs + SNFI_MISC_CTL);
735 + writel(len << WR_LEN_SHIFT, snfi->regs + SNFI_MISC_CTL2);
736 + writew(sectors << CON_SEC_SHIFT, snfi->regs + NFI_CON);
738 + reg = readw(snfi->regs + NFI_CNFG);
739 + reg &= ~(CNFG_READ_EN | CNFG_BYTE_RW);
740 + reg |= CNFG_DMA | CNFG_DMA_BURST_EN | CNFG_OP_PROGRAM;
743 + reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN;
744 + writew(reg, snfi->regs + NFI_CNFG);
746 + snfi->ecc_cfg.mode = ECC_NFI_MODE;
747 + snfi->ecc_cfg.op = ECC_ENCODE;
748 + ret = mtk_ecc_enable(snfi->ecc, &snfi->ecc_cfg);
750 + dev_err(snfi->dev, "ecc enable failed\n");
751 + /* clear NFI_CNFG */
752 + reg &= ~(CNFG_DMA_BURST_EN | CNFG_DMA |
753 + CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
754 + writew(reg, snfi->regs + NFI_CNFG);
755 + dma_unmap_single(snfi->dev, dma_addr, len,
759 + /* write OOB into the FDM registers (OOB area in MTK NAND) */
760 + mtk_snfi_write_fdm_data(mem, sectors);
762 + writew(reg, snfi->regs + NFI_CNFG);
764 + writel(lower_32_bits(dma_addr), snfi->regs + NFI_STRADDR);
765 + readw(snfi->regs + NFI_INTR_STA);
766 + writew(INTR_AHB_DONE_EN, snfi->regs + NFI_INTR_EN);
768 + init_completion(&snfi->done);
770 + /* set dummy command to trigger NFI enter SPI mode */
771 + writew(NAND_CMD_DUMMYPROG, snfi->regs + NFI_CMD);
772 + reg = readl(snfi->regs + NFI_CON) | CON_BWR;
773 + writew(reg, snfi->regs + NFI_CON);
775 + ret = wait_for_completion_timeout(&snfi->done, msecs_to_jiffies(500));
777 + dev_err(snfi->dev, "custom program done timeout\n");
778 + writew(0, snfi->regs + NFI_INTR_EN);
783 + ret = readl_poll_timeout_atomic(snfi->regs + NFI_ADDRCNTR, reg,
784 + ADDRCNTR_SEC(reg) >= sectors,
787 + dev_err(snfi->dev, "hwecc write timeout\n");
790 + mtk_ecc_disable(snfi->ecc);
793 + dma_unmap_single(snfi->dev, dma_addr, len, DMA_TO_DEVICE);
794 + writel(0, snfi->regs + NFI_CON);
795 + writel(0, snfi->regs + NFI_CNFG);
796 + reg = readl(snfi->regs + SNFI_MISC_CTL);
797 + reg &= ~WR_CUSTOM_EN;
798 + writel(reg, snfi->regs + SNFI_MISC_CTL);
803 +static int mtk_snfi_read(struct spi_mem *mem,
804 + const struct spi_mem_op *op)
806 + struct spinand_device *spinand = spi_mem_get_drvdata(mem);
807 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
808 + struct mtd_info *mtd = spinand_to_mtd(spinand);
809 + struct mtk_snfi_nand_chip *snfi_nand = &snfi->snfi_nand;
810 + u32 col_addr = op->addr.val;
811 + int i, ret, sectors, oob_on = false;
813 + if (col_addr == mtd->writesize)
816 + ret = mtk_snfi_read_from_cache(mem, op, oob_on);
818 + dev_warn(snfi->dev, "read from cache fail\n");
822 + sectors = mtd->writesize / snfi->caps->nand_sec_size;
823 + for (i = 0; i < sectors; i++) {
825 + memcpy(oob_ptr(mem, i),
826 + mtk_oob_ptr(mem, snfi->buffer, i),
827 + snfi->caps->nand_fdm_size);
829 + if (i == snfi_nand->bad_mark.sec && snfi->caps->bad_mark_swap)
830 + snfi_nand->bad_mark.bm_swap(mem, snfi->buffer,
835 + memcpy(spinand->databuf, snfi->buffer, mtd->writesize);
840 +static int mtk_snfi_write(struct spi_mem *mem,
841 + const struct spi_mem_op *op)
843 + struct spinand_device *spinand = spi_mem_get_drvdata(mem);
844 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
845 + struct mtd_info *mtd = spinand_to_mtd(spinand);
846 + struct mtk_snfi_nand_chip *snfi_nand = &snfi->snfi_nand;
847 + u32 ret, i, sectors, col_addr = op->addr.val;
848 + int oob_on = false;
850 + if (col_addr == mtd->writesize)
853 + sectors = mtd->writesize / snfi->caps->nand_sec_size;
854 + memset(snfi->buffer, 0xff, mtd->writesize + mtd->oobsize);
857 + memcpy(snfi->buffer, spinand->databuf, mtd->writesize);
859 + for (i = 0; i < sectors; i++) {
860 + if (i == snfi_nand->bad_mark.sec && snfi->caps->bad_mark_swap)
861 + snfi_nand->bad_mark.bm_swap(mem, snfi->buffer, oob_on);
864 + memcpy(mtk_oob_ptr(mem, snfi->buffer, i),
866 + snfi->caps->nand_fdm_size);
869 + ret = mtk_snfi_write_to_cache(mem, op, oob_on);
871 + dev_warn(snfi->dev, "write to cache fail\n");
876 +static int mtk_snfi_command_exec(struct mtk_snfi *snfi,
877 + const u8 *txbuf, u8 *rxbuf,
878 + const u32 txlen, const u32 rxlen)
880 + u32 tmp, i, j, reg, m;
881 + u8 *p_tmp = (u8 *)(&tmp);
884 + /* Moving tx data to NFI_SPI GPRAM */
885 + for (i = 0, m = 0; i < txlen; ) {
886 + for (j = 0, tmp = 0; i < txlen && j < 4; i++, j++)
887 + p_tmp[j] = txbuf[i];
889 + writel(tmp, snfi->regs + SNFI_GPRAM_DATA + m);
893 + writel(txlen, snfi->regs + SNFI_MAC_OUTL);
894 + writel(rxlen, snfi->regs + SNFI_MAC_INL);
895 + ret = mtk_snfi_mac_op(snfi);
899 + /* For NULL input data, this loop will be skipped */
901 + for (i = 0, m = 0; i < rxlen; ) {
902 + reg = readl(snfi->regs +
903 + SNFI_GPRAM_DATA + m);
904 + for (j = 0; i < rxlen && j < 4; i++, j++, rxbuf++) {
905 + if (m == 0 && i == 0)
907 + *rxbuf = (reg >> (j * 8)) & 0xFF;
916 + * mtk_snfi_exec_op - to process command/data to send to the
917 + * SPI NAND by mtk controller
919 +static int mtk_snfi_exec_op(struct spi_mem *mem,
920 + const struct spi_mem_op *op)
923 + struct mtk_snfi *snfi = spi_controller_get_devdata(mem->spi->master);
924 + struct spinand_device *spinand = spi_mem_get_drvdata(mem);
925 + struct mtd_info *mtd = spinand_to_mtd(spinand);
926 + struct nand_device *nand = mtd_to_nanddev(mtd);
927 + const struct spi_mem_op *read_cache;
928 + const struct spi_mem_op *write_cache;
929 + const struct spi_mem_op *update_cache;
930 + u32 tmpbufsize, txlen = 0, rxlen = 0;
931 + u8 *txbuf, *rxbuf = NULL, *buf;
934 + ret = mtk_snfi_reset(snfi);
936 + dev_warn(snfi->dev, "reset spi memory controller fail\n");
940 + /*if bbt initial, framework have detect nand information */
941 + if (nand->bbt.cache) {
942 + read_cache = spinand->op_templates.read_cache;
943 + write_cache = spinand->op_templates.write_cache;
944 + update_cache = spinand->op_templates.update_cache;
946 + ret = mtk_snfi_hw_runtime_config(mem);
950 + /* For Read/Write with cache, Erase use framework flow */
951 + if (op->cmd.opcode == read_cache->cmd.opcode) {
952 + ret = mtk_snfi_read(mem, op);
954 + dev_warn(snfi->dev, "snfi read fail\n");
957 + } else if ((op->cmd.opcode == write_cache->cmd.opcode)
958 + || (op->cmd.opcode == update_cache->cmd.opcode)) {
959 + ret = mtk_snfi_write(mem, op);
961 + dev_warn(snfi->dev, "snfi write fail\n");
967 + tmpbufsize = sizeof(op->cmd.opcode) + op->addr.nbytes +
968 + op->dummy.nbytes + op->data.nbytes;
970 + txbuf = kzalloc(tmpbufsize, GFP_KERNEL);
974 + txbuf[txlen++] = op->cmd.opcode;
976 + if (op->addr.nbytes)
977 + for (i = 0; i < op->addr.nbytes; i++)
978 + txbuf[txlen++] = op->addr.val >>
979 + (8 * (op->addr.nbytes - i - 1));
981 + txlen += op->dummy.nbytes;
983 + if (op->data.dir == SPI_MEM_DATA_OUT)
984 + for (i = 0; i < op->data.nbytes; i++) {
985 + buf = (u8 *)op->data.buf.out;
986 + txbuf[txlen++] = buf[i];
989 + if (op->data.dir == SPI_MEM_DATA_IN) {
990 + rxbuf = (u8 *)op->data.buf.in;
991 + rxlen += op->data.nbytes;
994 + ret = mtk_snfi_command_exec(snfi, txbuf, rxbuf, txlen, rxlen);
1000 +static int mtk_snfi_init(struct mtk_snfi *snfi)
1004 + /* Reset the state machine and data FIFO */
1005 + ret = mtk_snfi_reset(snfi);
1007 + dev_warn(snfi->dev, "MTK reset controller fail\n");
1011 + snfi->buffer = devm_kzalloc(snfi->dev, 4096 + 256, GFP_KERNEL);
1012 + if (!snfi->buffer)
1015 + /* Clear interrupt, read clear. */
1016 + readw(snfi->regs + NFI_INTR_STA);
1017 + writew(0, snfi->regs + NFI_INTR_EN);
1019 + writel(0, snfi->regs + NFI_CON);
1020 + writel(0, snfi->regs + NFI_CNFG);
1022 + /* Change to NFI_SPI mode. */
1023 + writel(SNFI_MODE_EN, snfi->regs + SNFI_CNFG);
1028 +static int mtk_snfi_check_buswidth(u8 width)
1043 +static bool mtk_snfi_supports_op(struct spi_mem *mem,
1044 + const struct spi_mem_op *op)
1048 + /* For MTK Spi Nand controller, cmd buswidth just support 1 bit*/
1049 + if (op->cmd.buswidth != 1)
1052 + if (op->addr.nbytes)
1053 + ret |= mtk_snfi_check_buswidth(op->addr.buswidth);
1055 + if (op->dummy.nbytes)
1056 + ret |= mtk_snfi_check_buswidth(op->dummy.buswidth);
1058 + if (op->data.nbytes)
1059 + ret |= mtk_snfi_check_buswidth(op->data.buswidth);
1067 +static const struct spi_controller_mem_ops mtk_snfi_ops = {
1068 + .supports_op = mtk_snfi_supports_op,
1069 + .exec_op = mtk_snfi_exec_op,
1072 +static const struct mtk_snfi_caps snfi_mt7622 = {
1073 + .spare_size = spare_size_mt7622,
1074 + .num_spare_size = 4,
1075 + .nand_sec_size = 512,
1076 + .nand_fdm_size = 8,
1077 + .nand_fdm_ecc_size = 1,
1078 + .ecc_parity_bits = 13,
1079 + .pageformat_spare_shift = 4,
1080 + .bad_mark_swap = 0,
1083 +static const struct mtk_snfi_caps snfi_mt7629 = {
1084 + .spare_size = spare_size_mt7622,
1085 + .num_spare_size = 4,
1086 + .nand_sec_size = 512,
1087 + .nand_fdm_size = 8,
1088 + .nand_fdm_ecc_size = 1,
1089 + .ecc_parity_bits = 13,
1090 + .pageformat_spare_shift = 4,
1091 + .bad_mark_swap = 1,
1094 +static const struct of_device_id mtk_snfi_id_table[] = {
1095 + { .compatible = "mediatek,mt7622-snfi", .data = &snfi_mt7622, },
1096 + { .compatible = "mediatek,mt7629-snfi", .data = &snfi_mt7629, },
1097 + { /* sentinel */ }
1100 +static int mtk_snfi_probe(struct platform_device *pdev)
1102 + struct device *dev = &pdev->dev;
1103 + struct device_node *np = dev->of_node;
1104 + struct spi_controller *ctlr;
1105 + struct mtk_snfi *snfi;
1106 + struct resource *res;
1109 + ctlr = spi_alloc_master(&pdev->dev, sizeof(*snfi));
1113 + snfi = spi_controller_get_devdata(ctlr);
1114 + snfi->caps = of_device_get_match_data(dev);
1117 + snfi->ecc = of_mtk_ecc_get(np);
1118 + if (IS_ERR_OR_NULL(snfi->ecc))
1119 + goto err_put_master;
1121 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1122 + snfi->regs = devm_ioremap_resource(dev, res);
1123 + if (IS_ERR(snfi->regs)) {
1124 + ret = PTR_ERR(snfi->regs);
1128 + /* find the clocks */
1129 + snfi->clk.nfi_clk = devm_clk_get(dev, "nfi_clk");
1130 + if (IS_ERR(snfi->clk.nfi_clk)) {
1131 + dev_err(dev, "no nfi clk\n");
1132 + ret = PTR_ERR(snfi->clk.nfi_clk);
1136 + snfi->clk.spi_clk = devm_clk_get(dev, "spi_clk");
1137 + if (IS_ERR(snfi->clk.spi_clk)) {
1138 + dev_err(dev, "no spi clk\n");
1139 + ret = PTR_ERR(snfi->clk.spi_clk);
1143 + ret = mtk_snfi_enable_clk(dev, &snfi->clk);
1147 + /* find the irq */
1148 + irq = platform_get_irq(pdev, 0);
1150 + dev_err(dev, "no snfi irq resource\n");
1155 + ret = devm_request_irq(dev, irq, mtk_snfi_irq, 0, "mtk-snfi", snfi);
1157 + dev_err(dev, "failed to request snfi irq\n");
1161 + ret = dma_set_mask(dev, DMA_BIT_MASK(32));
1163 + dev_err(dev, "failed to set dma mask\n");
1167 + ctlr->dev.of_node = np;
1168 + ctlr->mem_ops = &mtk_snfi_ops;
1170 + platform_set_drvdata(pdev, snfi);
1171 + ret = mtk_snfi_init(snfi);
1173 + dev_err(dev, "failed to init snfi\n");
1177 + ret = devm_spi_register_master(dev, ctlr);
1184 + mtk_snfi_disable_clk(&snfi->clk);
1187 + mtk_ecc_release(snfi->ecc);
1190 + spi_master_put(ctlr);
1192 + dev_err(dev, "MediaTek SPI NAND interface probe failed %d\n", ret);
1196 +static int mtk_snfi_remove(struct platform_device *pdev)
1198 + struct mtk_snfi *snfi = platform_get_drvdata(pdev);
1200 + mtk_snfi_disable_clk(&snfi->clk);
1205 +static int mtk_snfi_suspend(struct platform_device *pdev, pm_message_t state)
1207 + struct mtk_snfi *snfi = platform_get_drvdata(pdev);
1209 + mtk_snfi_disable_clk(&snfi->clk);
1214 +static int mtk_snfi_resume(struct platform_device *pdev)
1216 + struct device *dev = &pdev->dev;
1217 + struct mtk_snfi *snfi = dev_get_drvdata(dev);
1220 + ret = mtk_snfi_enable_clk(dev, &snfi->clk);
1224 + ret = mtk_snfi_init(snfi);
1226 + dev_err(dev, "failed to init snfi controller\n");
1231 +static struct platform_driver mtk_snfi_driver = {
1233 + .name = "mtk-snfi",
1234 + .of_match_table = mtk_snfi_id_table,
1236 + .probe = mtk_snfi_probe,
1237 + .remove = mtk_snfi_remove,
1238 + .suspend = mtk_snfi_suspend,
1239 + .resume = mtk_snfi_resume,
1242 +module_platform_driver(mtk_snfi_driver);
1244 +MODULE_LICENSE("GPL v2");
1245 +MODULE_AUTHOR("Xiangsheng Hou <xiangsheng.hou@mediatek.com>");
1246 +MODULE_DESCRIPTION("Mediatek SPI Memory Interface Driver");