mediatek: filogic: add support for hw i2c, pwm and thermal
[openwrt/openwrt.git] / target / linux / mediatek / patches-5.15 / 805-thermal-drivers-mediatek-add-support-for-MT7986-and-.patch
1 From cd47d86ab09f1f3ec5c86441d4fe95e0cf597c06 Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Tue, 13 Sep 2022 00:56:24 +0100
4 Subject: [PATCH] thermal/drivers/mediatek: add support for MT7986 and MT7981
5
6 Add support for V3 generation thermal found in MT7986 and MT7981 SoCs.
7
8 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
9 ---
10 drivers/thermal/mtk_thermal.c | 202 +++++++++++++++++++++++++++++++++-
11 1 file changed, 198 insertions(+), 4 deletions(-)
12
13 --- a/drivers/thermal/mtk_thermal.c
14 +++ b/drivers/thermal/mtk_thermal.c
15 @@ -150,6 +150,21 @@
16 #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
17 #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
18
19 +/*
20 + * Layout of the fuses providing the calibration data
21 + * These macros could be used for MT7981 and MT7986.
22 + */
23 +#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff)
24 +#define CALIB_BUF0_ADC_OE_V3(x) (((x) >> 10) & 0x3ff)
25 +#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f)
26 +#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f)
27 +#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff)
28 +#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff)
29 +#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff)
30 +#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1)
31 +#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1)
32 +#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1)
33 +
34 enum {
35 VTS1,
36 VTS2,
37 @@ -163,6 +178,7 @@ enum {
38 enum mtk_thermal_version {
39 MTK_THERMAL_V1 = 1,
40 MTK_THERMAL_V2,
41 + MTK_THERMAL_V3,
42 };
43
44 /* MT2701 thermal sensors */
45 @@ -245,6 +261,27 @@ enum mtk_thermal_version {
46 /* The calibration coefficient of sensor */
47 #define MT8183_CALIBRATION 153
48
49 +/* AUXADC channel 11 is used for the temperature sensors */
50 +#define MT7986_TEMP_AUXADC_CHANNEL 11
51 +
52 +/* The total number of temperature sensors in the MT7986 */
53 +#define MT7986_NUM_SENSORS 1
54 +
55 +/* The number of banks in the MT7986 */
56 +#define MT7986_NUM_ZONES 1
57 +
58 +/* The number of sensing points per bank */
59 +#define MT7986_NUM_SENSORS_PER_ZONE 1
60 +
61 +/* MT7986 thermal sensors */
62 +#define MT7986_TS1 0
63 +
64 +/* The number of controller in the MT7986 */
65 +#define MT7986_NUM_CONTROLLER 1
66 +
67 +/* The calibration coefficient of sensor */
68 +#define MT7986_CALIBRATION 165
69 +
70 struct mtk_thermal;
71
72 struct thermal_bank_cfg {
73 @@ -279,6 +316,7 @@ struct mtk_thermal {
74
75 struct clk *clk_peri_therm;
76 struct clk *clk_auxadc;
77 + struct clk *clk_adc_32k;
78 /* lock: for getting and putting banks */
79 struct mutex lock;
80
81 @@ -386,6 +424,14 @@ static const int mt7622_mux_values[MT762
82 static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
83 static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
84
85 +/* MT7986 thermal sensor data */
86 +static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
87 +static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
88 +static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
89 +static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
90 +static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
91 +static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
92 +
93 /*
94 * The MT8173 thermal controller has four banks. Each bank can read up to
95 * four temperature sensors simultaneously. The MT8173 has a total of 5
96 @@ -549,6 +595,30 @@ static const struct mtk_thermal_data mt8
97 .version = MTK_THERMAL_V1,
98 };
99
100 +/*
101 + * MT7986 uses AUXADC Channel 11 for raw data access.
102 + */
103 +static const struct mtk_thermal_data mt7986_thermal_data = {
104 + .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
105 + .num_banks = MT7986_NUM_ZONES,
106 + .num_sensors = MT7986_NUM_SENSORS,
107 + .vts_index = mt7986_vts_index,
108 + .cali_val = MT7986_CALIBRATION,
109 + .num_controller = MT7986_NUM_CONTROLLER,
110 + .controller_offset = mt7986_tc_offset,
111 + .need_switch_bank = true,
112 + .bank_data = {
113 + {
114 + .num_sensors = 1,
115 + .sensors = mt7986_bank_data,
116 + },
117 + },
118 + .msr = mt7986_msr,
119 + .adcpnp = mt7986_adcpnp,
120 + .sensor_mux_values = mt7986_mux_values,
121 + .version = MTK_THERMAL_V3,
122 +};
123 +
124 /**
125 * raw_to_mcelsius - convert a raw ADC value to mcelsius
126 * @mt: The thermal controller
127 @@ -603,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk
128 return (format_2 - tmp) * 100;
129 }
130
131 +static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
132 +{
133 + s32 tmp;
134 +
135 + if (raw == 0)
136 + return 0;
137 +
138 + raw &= 0xfff;
139 + tmp = 100000 * 15 / 16 * 10000;
140 + tmp /= 4096 - 512 + mt->adc_ge;
141 + tmp /= 1490;
142 + tmp *= raw - mt->vts[sensno] - 2900;
143 +
144 + return mt->degc_cali * 500 - tmp;
145 +}
146 +
147 /**
148 * mtk_thermal_get_bank - get bank
149 * @bank: The bank
150 @@ -659,9 +745,12 @@ static int mtk_thermal_bank_temperature(
151 if (mt->conf->version == MTK_THERMAL_V1) {
152 temp = raw_to_mcelsius_v1(
153 mt, conf->bank_data[bank->id].sensors[i], raw);
154 - } else {
155 + } else if (mt->conf->version == MTK_THERMAL_V2) {
156 temp = raw_to_mcelsius_v2(
157 mt, conf->bank_data[bank->id].sensors[i], raw);
158 + } else {
159 + temp = raw_to_mcelsius_v3(
160 + mt, conf->bank_data[bank->id].sensors[i], raw);
161 }
162
163 /*
164 @@ -887,6 +976,26 @@ static int mtk_thermal_extract_efuse_v2(
165 return 0;
166 }
167
168 +static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
169 +{
170 + if (!CALIB_BUF1_VALID_V3(buf[1]))
171 + return -EINVAL;
172 +
173 + mt->adc_oe = CALIB_BUF0_ADC_OE_V3(buf[0]);
174 + mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
175 + mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
176 + mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
177 + mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
178 + mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
179 + mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
180 + mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
181 +
182 + if (CALIB_BUF1_ID_V3(buf[1]) == 0)
183 + mt->o_slope = 0;
184 +
185 + return 0;
186 +}
187 +
188 static int mtk_thermal_get_calibration_data(struct device *dev,
189 struct mtk_thermal *mt)
190 {
191 @@ -897,6 +1006,7 @@ static int mtk_thermal_get_calibration_d
192
193 /* Start with default values */
194 mt->adc_ge = 512;
195 + mt->adc_oe = 512;
196 for (i = 0; i < mt->conf->num_sensors; i++)
197 mt->vts[i] = 260;
198 mt->degc_cali = 40;
199 @@ -924,8 +1034,10 @@ static int mtk_thermal_get_calibration_d
200
201 if (mt->conf->version == MTK_THERMAL_V1)
202 ret = mtk_thermal_extract_efuse_v1(mt, buf);
203 - else
204 + else if (mt->conf->version == MTK_THERMAL_V2)
205 ret = mtk_thermal_extract_efuse_v2(mt, buf);
206 + else
207 + ret = mtk_thermal_extract_efuse_v3(mt, buf);
208
209 if (ret) {
210 dev_info(dev, "Device not calibrated, using default calibration values\n");
211 @@ -956,6 +1068,10 @@ static const struct of_device_id mtk_the
212 .data = (void *)&mt7622_thermal_data,
213 },
214 {
215 + .compatible = "mediatek,mt7986-thermal",
216 + .data = (void *)&mt7986_thermal_data,
217 + },
218 + {
219 .compatible = "mediatek,mt8183-thermal",
220 .data = (void *)&mt8183_thermal_data,
221 }, {
222 @@ -1009,6 +1125,12 @@ static int mtk_thermal_probe(struct plat
223 if (IS_ERR(mt->clk_auxadc))
224 return PTR_ERR(mt->clk_auxadc);
225
226 + if (mt->conf->version == MTK_THERMAL_V3) {
227 + mt->clk_adc_32k = devm_clk_get(&pdev->dev, "adc_32k");
228 + if (IS_ERR(mt->clk_adc_32k))
229 + return PTR_ERR(mt->clk_adc_32k);
230 + }
231 +
232 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
233 mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
234 if (IS_ERR(mt->thermal_base))
235 @@ -1058,10 +1180,18 @@ static int mtk_thermal_probe(struct plat
236 if (ret)
237 return ret;
238
239 + if (mt->conf->version == MTK_THERMAL_V3) {
240 + ret = clk_prepare_enable(mt->clk_adc_32k);
241 + if (ret) {
242 + dev_err(&pdev->dev, "Can't enable auxadc 32k clk: %d\n", ret);
243 + return ret;
244 + }
245 + }
246 +
247 ret = clk_prepare_enable(mt->clk_auxadc);
248 if (ret) {
249 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
250 - return ret;
251 + goto err_disable_clk_adc_32k;
252 }
253
254 ret = clk_prepare_enable(mt->clk_peri_therm);
255 @@ -1070,7 +1200,8 @@ static int mtk_thermal_probe(struct plat
256 goto err_disable_clk_auxadc;
257 }
258
259 - if (mt->conf->version == MTK_THERMAL_V2) {
260 + if (mt->conf->version == MTK_THERMAL_V2 ||
261 + mt->conf->version == MTK_THERMAL_V3) {
262 mtk_thermal_turn_on_buffer(apmixed_base);
263 mtk_thermal_release_periodic_ts(mt, auxadc_base);
264 }
265 @@ -1099,6 +1230,9 @@ err_disable_clk_peri_therm:
266 clk_disable_unprepare(mt->clk_peri_therm);
267 err_disable_clk_auxadc:
268 clk_disable_unprepare(mt->clk_auxadc);
269 +err_disable_clk_adc_32k:
270 + if (mt->conf->version == MTK_THERMAL_V3)
271 + clk_disable_unprepare(mt->clk_adc_32k);
272
273 return ret;
274 }
275 @@ -1110,6 +1244,9 @@ static int mtk_thermal_remove(struct pla
276 clk_disable_unprepare(mt->clk_peri_therm);
277 clk_disable_unprepare(mt->clk_auxadc);
278
279 + if (mt->conf->version == MTK_THERMAL_V3)
280 + clk_disable_unprepare(mt->clk_adc_32k);
281 +
282 return 0;
283 }
284