1 From 4b4719437d85f0173d344f2c76fa1a5b7f7d184b Mon Sep 17 00:00:00 2001
2 From: Sam Shih <sam.shih@mediatek.com>
3 Date: Sun, 17 Dec 2023 21:50:15 +0000
4 Subject: [PATCH 4/4] clk: mediatek: add drivers for MT7988 SoC
6 Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
7 typical MediaTek designs.
9 Also add driver for XFIPLL clock generating the 156.25MHz clock for
10 the XFI SerDes. It needs an undocumented software workaround and has
11 an unknown internal design.
13 Signed-off-by: Sam Shih <sam.shih@mediatek.com>
14 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
15 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
16 Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org
17 [sboyd@kernel.org: Add module license to infracfg file]
18 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
20 drivers/clk/mediatek/Kconfig | 9 +
21 drivers/clk/mediatek/Makefile | 5 +
22 drivers/clk/mediatek/clk-mt7988-apmixed.c | 114 ++++++++
23 drivers/clk/mediatek/clk-mt7988-eth.c | 150 ++++++++++
24 drivers/clk/mediatek/clk-mt7988-infracfg.c | 275 +++++++++++++++++
25 drivers/clk/mediatek/clk-mt7988-topckgen.c | 325 +++++++++++++++++++++
26 drivers/clk/mediatek/clk-mt7988-xfipll.c | 82 ++++++
27 7 files changed, 960 insertions(+)
28 create mode 100644 drivers/clk/mediatek/clk-mt7988-apmixed.c
29 create mode 100644 drivers/clk/mediatek/clk-mt7988-eth.c
30 create mode 100644 drivers/clk/mediatek/clk-mt7988-infracfg.c
31 create mode 100644 drivers/clk/mediatek/clk-mt7988-topckgen.c
32 create mode 100644 drivers/clk/mediatek/clk-mt7988-xfipll.c
34 --- a/drivers/clk/mediatek/Kconfig
35 +++ b/drivers/clk/mediatek/Kconfig
36 @@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS
37 This driver adds support for clocks for Ethernet and SGMII
38 required on MediaTek MT7986 SoC.
40 +config COMMON_CLK_MT7988
41 + tristate "Clock driver for MediaTek MT7988"
42 + depends on ARCH_MEDIATEK || COMPILE_TEST
43 + select COMMON_CLK_MEDIATEK
44 + default ARCH_MEDIATEK
46 + This driver supports MediaTek MT7988 basic clocks and clocks
47 + required for various periperals found on this SoC.
49 config COMMON_CLK_MT8135
50 bool "Clock driver for MediaTek MT8135"
51 depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
52 --- a/drivers/clk/mediatek/Makefile
53 +++ b/drivers/clk/mediatek/Makefile
54 @@ -60,6 +60,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
55 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
56 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
57 obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
58 +obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
59 +obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
60 +obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
61 +obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
62 +obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o
63 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
64 obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
65 obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
67 +++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c
69 +// SPDX-License-Identifier: GPL-2.0
71 + * Copyright (c) 2023 MediaTek Inc.
72 + * Author: Sam Shih <sam.shih@mediatek.com>
73 + * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
76 +#include <linux/clk-provider.h>
77 +#include <linux/of.h>
78 +#include <linux/of_address.h>
79 +#include <linux/of_device.h>
80 +#include <linux/platform_device.h>
82 +#include "clk-gate.h"
85 +#include <dt-bindings/clock/mediatek,mt7988-clk.h>
87 +#define MT7988_PLL_FMAX (2500UL * MHZ)
88 +#define MT7988_PCW_CHG_BIT 2
90 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \
91 + _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift, \
97 + .pwr_reg = _pwr_reg, \
98 + .en_mask = _en_mask, \
100 + .rst_bar_mask = BIT(_rst_bar_mask), \
101 + .fmax = MT7988_PLL_FMAX, \
102 + .pcwbits = _pcwbits, \
103 + .pd_reg = _pd_reg, \
104 + .pd_shift = _pd_shift, \
105 + .tuner_reg = _tuner_reg, \
106 + .tuner_en_reg = _tuner_en_reg, \
107 + .tuner_en_bit = _tuner_en_bit, \
108 + .pcw_reg = _pcw_reg, \
109 + .pcw_shift = _pcw_shift, \
110 + .pcw_chg_reg = _pcw_chg_reg, \
111 + .pcw_chg_bit = MT7988_PCW_CHG_BIT, \
112 + .parent_name = "clkxtal", \
115 +static const struct mtk_pll_data plls[] = {
116 + PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
117 + 0, 0, 0x0108, 0, 0x0104),
118 + PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
119 + 0, 0, 0, 0x0118, 0, 0x0114),
120 + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
121 + 0, 0, 0, 0x0128, 0, 0x0124),
122 + PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
123 + 0x0700, 1, 0x0138, 0, 0x0134),
124 + PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
125 + 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
126 + PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23,
127 + 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154),
128 + PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0,
129 + 0, 0, 0x0168, 0, 0x0164),
130 + PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0,
131 + 0x0178, 0, 0x0174),
132 + PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32,
133 + 0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204),
134 + PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32,
135 + 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
136 + PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32,
137 + 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
138 + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0,
139 + 0, 0x0318, 0, 0x0314),
142 +static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
143 + { .compatible = "mediatek,mt7988-apmixedsys" },
147 +static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
149 + struct clk_hw_onecell_data *clk_data;
150 + struct device_node *node = pdev->dev.of_node;
153 + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
157 + r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
159 + goto free_apmixed_data;
161 + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
163 + goto unregister_plls;
168 + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
170 + mtk_free_clk_data(clk_data);
174 +static struct platform_driver clk_mt7988_apmixed_drv = {
175 + .probe = clk_mt7988_apmixed_probe,
177 + .name = "clk-mt7988-apmixed",
178 + .of_match_table = of_match_clk_mt7988_apmixed,
181 +builtin_platform_driver(clk_mt7988_apmixed_drv);
182 +MODULE_LICENSE("GPL");
184 +++ b/drivers/clk/mediatek/clk-mt7988-eth.c
186 +// SPDX-License-Identifier: GPL-2.0
188 + * Copyright (c) 2023 MediaTek Inc.
189 + * Author: Sam Shih <sam.shih@mediatek.com>
190 + * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
193 +#include <linux/clk-provider.h>
194 +#include <linux/of.h>
195 +#include <linux/of_address.h>
196 +#include <linux/of_device.h>
197 +#include <linux/platform_device.h>
198 +#include "clk-mtk.h"
199 +#include "clk-gate.h"
201 +#include <dt-bindings/clock/mediatek,mt7988-clk.h>
202 +#include <dt-bindings/reset/mediatek,mt7988-resets.h>
204 +static const struct mtk_gate_regs ethdma_cg_regs = {
210 +#define GATE_ETHDMA(_id, _name, _parent, _shift) \
214 + .parent_name = _parent, \
215 + .regs = ðdma_cg_regs, \
217 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
220 +static const struct mtk_gate ethdma_clks[] = {
221 + GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
222 + GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
223 + GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
224 + GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
225 + GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
226 + GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
227 + GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
228 + GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
229 + GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29),
232 +static const struct mtk_clk_desc ethdma_desc = {
233 + .clks = ethdma_clks,
234 + .num_clks = ARRAY_SIZE(ethdma_clks),
237 +static const struct mtk_gate_regs sgmii_cg_regs = {
243 +#define GATE_SGMII(_id, _name, _parent, _shift) \
247 + .parent_name = _parent, \
248 + .regs = &sgmii_cg_regs, \
250 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
253 +static const struct mtk_gate sgmii0_clks[] = {
254 + GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
255 + GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
258 +static const struct mtk_clk_desc sgmii0_desc = {
259 + .clks = sgmii0_clks,
260 + .num_clks = ARRAY_SIZE(sgmii0_clks),
263 +static const struct mtk_gate sgmii1_clks[] = {
264 + GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
265 + GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
268 +static const struct mtk_clk_desc sgmii1_desc = {
269 + .clks = sgmii1_clks,
270 + .num_clks = ARRAY_SIZE(sgmii1_clks),
273 +static const struct mtk_gate_regs ethwarp_cg_regs = {
279 +#define GATE_ETHWARP(_id, _name, _parent, _shift) \
283 + .parent_name = _parent, \
284 + .regs = ðwarp_cg_regs, \
286 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
289 +static const struct mtk_gate ethwarp_clks[] = {
290 + GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13),
291 + GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14),
292 + GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15),
295 +static u16 ethwarp_rst_ofs[] = { 0x8 };
297 +static u16 ethwarp_idx_map[] = {
298 + [MT7988_ETHWARP_RST_SWITCH] = 9,
301 +static const struct mtk_clk_rst_desc ethwarp_rst_desc = {
302 + .version = MTK_RST_SIMPLE,
303 + .rst_bank_ofs = ethwarp_rst_ofs,
304 + .rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs),
305 + .rst_idx_map = ethwarp_idx_map,
306 + .rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map),
309 +static const struct mtk_clk_desc ethwarp_desc = {
310 + .clks = ethwarp_clks,
311 + .num_clks = ARRAY_SIZE(ethwarp_clks),
312 + .rst_desc = ðwarp_rst_desc,
315 +static const struct of_device_id of_match_clk_mt7988_eth[] = {
316 + { .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc },
317 + { .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc },
318 + { .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc },
319 + { .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc },
322 +MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
324 +static struct platform_driver clk_mt7988_eth_drv = {
326 + .name = "clk-mt7988-eth",
327 + .of_match_table = of_match_clk_mt7988_eth,
329 + .probe = mtk_clk_simple_probe,
330 + .remove = mtk_clk_simple_remove,
332 +module_platform_driver(clk_mt7988_eth_drv);
334 +MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
335 +MODULE_LICENSE("GPL");
337 +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
339 +// SPDX-License-Identifier: GPL-2.0
341 + * Copyright (c) 2023 MediaTek Inc.
342 + * Author: Sam Shih <sam.shih@mediatek.com>
343 + * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
346 +#include <linux/clk-provider.h>
347 +#include <linux/of.h>
348 +#include <linux/of_address.h>
349 +#include <linux/of_device.h>
350 +#include <linux/platform_device.h>
351 +#include "clk-mtk.h"
352 +#include "clk-gate.h"
353 +#include "clk-mux.h"
354 +#include <dt-bindings/clock/mediatek,mt7988-clk.h>
356 +static DEFINE_SPINLOCK(mt7988_clk_lock);
358 +static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel",
361 +static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel",
364 +static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel",
367 +static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" };
369 +static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" };
371 +static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k",
372 + "csw_infra_f26m_sel", "sysaxi_sel",
375 +static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
376 + "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel"
379 +static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
380 + "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel"
383 +static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
384 + "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel"
387 +static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
388 + "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel"
391 +static const struct mtk_mux infra_muxes[] = {
392 + /* MODULE_CLK_SEL_0 */
393 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
394 + infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
395 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
396 + infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
397 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
398 + infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
399 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,
400 + 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
401 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,
402 + 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
403 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,
404 + 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
405 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
406 + 0x0010, 0x0014, 14, 2, -1, -1, -1),
407 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,
408 + 0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),
409 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,
410 + 0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),
411 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,
412 + 0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),
413 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,
414 + 0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),
415 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,
416 + 0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),
417 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,
418 + 0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),
419 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,
420 + 0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),
421 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,
422 + 0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),
423 + /* MODULE_CLK_SEL_1 */
424 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",
425 + infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1,
427 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",
428 + infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1,
430 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",
431 + infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1,
433 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",
434 + infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1,
438 +static const struct mtk_gate_regs infra0_cg_regs = {
444 +static const struct mtk_gate_regs infra1_cg_regs = {
450 +static const struct mtk_gate_regs infra2_cg_regs = {
456 +static const struct mtk_gate_regs infra3_cg_regs = {
462 +#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \
463 + GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
466 +#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \
467 + GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
470 +#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \
471 + GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
474 +#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \
475 + GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
478 +#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
480 +#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
482 +#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
484 +#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
486 +static const struct mtk_gate infra_clks[] = {
488 + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0",
489 + "csw_infra_f26m_sel", 7),
490 + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
491 + "csw_infra_f26m_sel", 8),
492 + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
493 + "csw_infra_f26m_sel", 9),
494 + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
495 + "csw_infra_f26m_sel", 10),
497 + GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0),
498 + GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1),
499 + GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2),
500 + GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3),
501 + GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4),
502 + GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5),
503 + GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6),
504 + GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7),
505 + GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8),
506 + GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9),
507 + GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10),
508 + GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12),
509 + GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13),
510 + GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14),
511 + GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
512 + GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
513 + GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
514 + GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19,
517 + GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20,
519 + GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21),
520 + GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29),
521 + GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30),
523 + GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel",
525 + GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
526 + GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3),
527 + GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4),
528 + GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5),
529 + GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
530 + GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
531 + GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
533 + GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
535 + GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
536 + GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
537 + GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
539 + GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
540 + GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
541 + GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),
542 + GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL),
543 + GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20),
544 + GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21),
545 + GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22),
546 + GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23),
547 + GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24),
548 + GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25),
549 + GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26),
550 + GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
551 + GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
552 + GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
554 + GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0),
555 + GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1),
556 + GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2),
557 + GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3),
558 + GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
559 + GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5),
560 + GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
561 + GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
562 + GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8,
564 + GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel",
565 + 9, CLK_IS_CRITICAL),
566 + GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
567 + GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11),
568 + GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
569 + GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13),
570 + GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
571 + GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15),
572 + GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
573 + "infra_pcie_gfmux_tl_o_p0_sel", 20),
574 + GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
575 + "infra_pcie_gfmux_tl_o_p1_sel", 21),
576 + GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
577 + "infra_pcie_gfmux_tl_o_p2_sel", 22),
578 + GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
579 + "infra_pcie_gfmux_tl_o_p3_sel", 23),
580 + GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24),
581 + GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25),
582 + GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26),
583 + GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27),
584 + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28),
585 + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29),
586 + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30),
587 + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
590 +static const struct mtk_clk_desc infra_desc = {
591 + .clks = infra_clks,
592 + .num_clks = ARRAY_SIZE(infra_clks),
593 + .mux_clks = infra_muxes,
594 + .num_mux_clks = ARRAY_SIZE(infra_muxes),
595 + .clk_lock = &mt7988_clk_lock,
598 +static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
599 + { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
602 +MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
604 +static struct platform_driver clk_mt7988_infracfg_drv = {
606 + .name = "clk-mt7988-infracfg",
607 + .of_match_table = of_match_clk_mt7988_infracfg,
609 + .probe = mtk_clk_simple_probe,
610 + .remove = mtk_clk_simple_remove,
612 +module_platform_driver(clk_mt7988_infracfg_drv);
613 +MODULE_LICENSE("GPL");
615 +++ b/drivers/clk/mediatek/clk-mt7988-topckgen.c
617 +// SPDX-License-Identifier: GPL-2.0
619 + * Copyright (c) 2023 MediaTek Inc.
620 + * Author: Sam Shih <sam.shih@mediatek.com>
621 + * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
624 +#include <linux/clk-provider.h>
625 +#include <linux/of.h>
626 +#include <linux/of_address.h>
627 +#include <linux/of_device.h>
628 +#include <linux/platform_device.h>
629 +#include "clk-mtk.h"
630 +#include "clk-gate.h"
631 +#include "clk-mux.h"
632 +#include <dt-bindings/clock/mediatek,mt7988-clk.h>
634 +static DEFINE_SPINLOCK(mt7988_clk_lock);
636 +static const struct mtk_fixed_clk top_fixed_clks[] = {
637 + FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
640 +static const struct mtk_fixed_factor top_divs[] = {
641 + FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
642 + FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
643 + FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
644 + FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
645 + FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
646 + FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
647 + FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
648 + FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
649 + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
650 + FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
651 + FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
652 + FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
653 + FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
654 + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
655 + FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
656 + FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
657 + FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
658 + FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
659 + FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
660 + FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
661 + FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
662 + FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
663 + FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
664 + FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
665 + FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
666 + FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
667 + FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
668 + FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
669 + FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
672 +static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" };
673 +static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" };
674 +static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" };
675 +static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" };
676 +static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
677 +static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", "mmpll",
678 + "net1pll_d4", "net1pll_d5", "mpll" };
679 +static const char *const eip197_parents[] = { "top_xtal", "netsyspll", "net2pll",
680 + "mmpll", "net1pll_d4", "net1pll_d5" };
681 +static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
682 +static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" };
683 +static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" };
684 +static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", "mmpll_d2",
685 + "mpll_d2", "mmpll_d4", "net1pll_d8_d2" };
686 +static const char *const spi_parents[] = { "top_xtal", "mpll_d2", "mmpll_d4",
687 + "net1pll_d8_d2", "net2pll_d6", "net1pll_d5_d4",
688 + "mpll_d4", "net1pll_d8_d4" };
689 +static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6",
690 + "mpll_d4", "mmpll_d8", "net1pll_d8_d4", "mpll_d8" };
691 +static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4",
692 + "mpll_d4", "mmpll_d8", "net1pll_d8_d4",
693 + "mmpll_d6_d2", "mpll_d8" };
694 +static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4",
695 + "mpll_d4", "mpll_d8_d2", "top_rtc_32k" };
696 +static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4",
698 +static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" };
699 +static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8",
700 + "mpll_d8_d2", "top_rtc_32k" };
701 +static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
702 +static const char *const aud_parents[] = { "top_xtal", "apll2" };
703 +static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
704 +static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" };
705 +static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
706 +static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" };
707 +static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
708 +static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
709 +static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" };
710 +static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
711 +static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" };
712 +static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" };
713 +static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
714 +static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" };
715 +static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" };
716 +static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" };
717 +static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" };
718 +static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" };
719 +static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" };
721 +static const struct mtk_mux top_muxes[] = {
723 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
724 + 0, 2, 7, 0x1c0, 0),
725 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
726 + 0x004, 0x008, 8, 2, 15, 0x1C0, 1),
727 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
728 + 0x004, 0x008, 16, 2, 23, 0x1C0, 2),
729 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
730 + 0x004, 0x008, 24, 2, 31, 0x1C0, 3),
732 + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
733 + 0x018, 0, 1, 7, 0x1C0, 4),
734 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010,
735 + 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
736 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents,
737 + 0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6),
738 + MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018,
739 + 24, 3, 31, 0x1c0, 7),
741 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020,
742 + 0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
743 + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2,
745 + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
746 + 0x024, 0x028, 16, 2, 23, 0x1C0, 10),
747 + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020,
748 + 0x024, 0x028, 24, 3, 31, 0x1C0, 11),
750 + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7,
752 + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038,
753 + 8, 3, 15, 0x1c0, 13),
754 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16,
756 + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038,
757 + 24, 3, 31, 0x1c0, 15),
759 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,
761 + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15,
763 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
764 + pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
765 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040,
766 + 0x044, 0x048, 24, 3, 31, 0x1C0, 19),
768 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050,
769 + 0x054, 0x058, 0, 3, 7, 0x1C0, 20),
770 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050,
771 + 0x054, 0x058, 8, 3, 15, 0x1C0, 21),
772 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050,
773 + 0x054, 0x058, 16, 3, 23, 0x1C0, 22),
774 + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054,
775 + 0x058, 24, 1, 31, 0x1C0, 23),
777 + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060,
778 + 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
779 + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064,
780 + 0x068, 8, 1, 15, 0x1C0, 25),
781 + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060,
782 + 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
783 + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060,
784 + 0x064, 0x068, 24, 1, 31, 0x1C0, 27),
786 + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents,
787 + 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
788 + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15,
790 + MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16,
792 + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24,
795 + MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088,
796 + 0, 1, 7, 0x1c4, 1),
797 + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088,
798 + 8, 1, 15, 0x1c4, 2),
799 + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084,
800 + 0x088, 16, 1, 23, 0x1c4, 3),
801 + MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
802 + usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
804 + MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
805 + usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
806 + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8,
808 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
809 + 0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
810 + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24,
813 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
814 + 0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
815 + MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
816 + 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10),
817 + MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
818 + 0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11),
820 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0,
821 + 0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
822 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4,
823 + 0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL),
824 + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents,
825 + 0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14),
826 + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents,
827 + 0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15),
828 + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0,
829 + 0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16),
831 + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0,
832 + 0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17),
833 + MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4,
834 + 0x0c8, 8, 2, 15, 0x1C4, 18),
835 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4,
836 + 0x0c8, 16, 1, 23, 0x1C4, 19),
837 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4,
838 + 0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL),
840 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
841 + 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
842 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
843 + 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
844 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4,
845 + 0x0d8, 16, 1, 23, 0x1C4, 23),
846 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4,
847 + 0x0d8, 24, 1, 31, 0x1C4, 24),
849 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4,
850 + 0x0e8, 0, 1, 7, 0x1C4, 25),
851 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4,
852 + 0x0e8, 8, 1, 15, 0x1C4, 26),
853 + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents,
854 + 0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27),
855 + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents,
856 + 0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28),
858 + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents,
859 + 0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29),
860 + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents,
861 + 0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30),
862 + MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1,
864 + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1,
867 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108,
868 + 0, 1, 7, 0x1c8, 2),
869 + MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100,
870 + 0x104, 0x108, 8, 1, 15, 0x1C8, 3),
871 + MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
872 + mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4),
873 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
874 + pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
876 + MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118,
877 + 0, 2, 7, 0x1c8, 6),
878 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
879 + netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
880 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
881 + pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
882 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110,
883 + 0x114, 0x118, 24, 2, 31, 0x1C8, 9),
885 + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124,
886 + 0x128, 0, 1, 7, 0x1c8, 10),
887 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128,
888 + 8, 2, 15, 0x1c8, 11),
891 +static const struct mtk_composite top_aud_divs[] = {
892 + DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8),
895 +static const struct mtk_clk_desc topck_desc = {
896 + .fixed_clks = top_fixed_clks,
897 + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
898 + .factor_clks = top_divs,
899 + .num_factor_clks = ARRAY_SIZE(top_divs),
900 + .mux_clks = top_muxes,
901 + .num_mux_clks = ARRAY_SIZE(top_muxes),
902 + .composite_clks = top_aud_divs,
903 + .num_composite_clks = ARRAY_SIZE(top_aud_divs),
904 + .clk_lock = &mt7988_clk_lock,
907 +static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" };
909 +static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" };
911 +static struct mtk_composite mcu_muxes[] = {
912 + /* bus_pll_divider_cfg */
913 + MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1,
915 + /* mp2_pll_divider_cfg */
916 + MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1,
920 +static const struct mtk_clk_desc mcusys_desc = {
921 + .composite_clks = mcu_muxes,
922 + .num_composite_clks = ARRAY_SIZE(mcu_muxes),
925 +static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
926 + { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
927 + { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
930 +MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
932 +static struct platform_driver clk_mt7988_topckgen_drv = {
933 + .probe = mtk_clk_simple_probe,
934 + .remove = mtk_clk_simple_remove,
936 + .name = "clk-mt7988-topckgen",
937 + .of_match_table = of_match_clk_mt7988_topckgen,
940 +module_platform_driver(clk_mt7988_topckgen_drv);
941 +MODULE_LICENSE("GPL");
943 +++ b/drivers/clk/mediatek/clk-mt7988-xfipll.c
945 +// SPDX-License-Identifier: GPL-2.0
947 + * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
950 +#include <linux/clk-provider.h>
951 +#include <linux/of.h>
952 +#include <linux/of_address.h>
953 +#include <linux/of_device.h>
954 +#include <linux/platform_device.h>
955 +#include "clk-mtk.h"
956 +#include "clk-gate.h"
957 +#include <dt-bindings/clock/mediatek,mt7988-clk.h>
959 +/* Register to control USXGMII XFI PLL analog */
960 +#define XFI_PLL_ANA_GLB8 0x108
961 +#define RG_XFI_PLL_ANA_SWWA 0x02283248
963 +static const struct mtk_gate_regs xfipll_cg_regs = {
969 +#define GATE_XFIPLL(_id, _name, _parent, _shift) \
973 + .parent_name = _parent, \
974 + .regs = &xfipll_cg_regs, \
976 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
979 +static const struct mtk_fixed_factor xfipll_divs[] = {
980 + FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32),
983 +static const struct mtk_gate xfipll_clks[] = {
984 + GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31),
987 +static const struct mtk_clk_desc xfipll_desc = {
988 + .clks = xfipll_clks,
989 + .num_clks = ARRAY_SIZE(xfipll_clks),
990 + .factor_clks = xfipll_divs,
991 + .num_factor_clks = ARRAY_SIZE(xfipll_divs),
994 +static int clk_mt7988_xfipll_probe(struct platform_device *pdev)
996 + struct device_node *node = pdev->dev.of_node;
997 + void __iomem *base = of_iomap(node, 0);
1002 + /* Apply software workaround for USXGMII PLL TCL issue */
1003 + writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8);
1006 + return mtk_clk_simple_probe(pdev);
1009 +static const struct of_device_id of_match_clk_mt7988_xfipll[] = {
1010 + { .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc },
1011 + { /* sentinel */ }
1013 +MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll);
1015 +static struct platform_driver clk_mt7988_xfipll_drv = {
1017 + .name = "clk-mt7988-xfipll",
1018 + .of_match_table = of_match_clk_mt7988_xfipll,
1020 + .probe = clk_mt7988_xfipll_probe,
1021 + .remove = mtk_clk_simple_remove,
1023 +module_platform_driver(clk_mt7988_xfipll_drv);
1025 +MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver");
1026 +MODULE_LICENSE("GPL");