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mpc83xx: cleanup rb333.dts
[openwrt/openwrt.git] / target / linux / mpc83xx / patches-3.3 / 200-powerpc-add-rbppc-support.patch
1 --- a/arch/powerpc/boot/Makefile
2 +++ b/arch/powerpc/boot/Makefile
3 @@ -76,7 +76,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
4 cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \
5 cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
6 fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \
7 - cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
8 + cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c rb600.c rb333.c \
9 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
10 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
11 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
12 @@ -242,6 +242,8 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.
13 image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds
14 image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds
15 image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
16 +image-$(CONFIG_RB_PPC) += dtbImage.rb600 \
17 + dtbImage.rb333
18
19 # Board ports in arch/powerpc/platform/85xx/Kconfig
20 image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
21 --- /dev/null
22 +++ b/arch/powerpc/boot/dts/rb600.dts
23 @@ -0,0 +1,283 @@
24 +/*
25 + * RouterBOARD 600 series Device Tree Source
26 + *
27 + * Copyright 2009 Michael Guntsche <mike@it-loops.com>
28 + *
29 + * This program is free software; you can redistribute it and/or modify it
30 + * under the terms of the GNU General Public License as published by the
31 + * Free Software Foundation; either version 2 of the License, or (at your
32 + * option) any later version.
33 + */
34 +
35 +/dts-v1/;
36 +
37 +/ {
38 + model = "RB600";
39 + compatible = "MPC83xx";
40 + #address-cells = <1>;
41 + #size-cells = <1>;
42 +
43 + aliases {
44 + ethernet0 = &enet0;
45 + ethernet1 = &enet1;
46 + pci0 = &pci0;
47 + };
48 +
49 + chosen {
50 + bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
51 + linux,stdout-path = "/soc8343@e0000000/serial@4500";
52 + };
53 +
54 + cpus {
55 + #address-cells = <1>;
56 + #size-cells = <0>;
57 +
58 + PowerPC,8343E@0 {
59 + device_type = "cpu";
60 + reg = <0x0>;
61 + d-cache-line-size = <0x20>;
62 + i-cache-line-size = <0x20>;
63 + d-cache-size = <0x8000>;
64 + i-cache-size = <0x8000>;
65 + timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
66 + clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
67 + };
68 + };
69 +
70 + memory {
71 + device_type = "memory";
72 + reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
73 + };
74 +
75 + cf@f9200000 {
76 + lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
77 + interrupt-at-level = <0x0>;
78 + interrupt-parent = <&ipic>;
79 + interrupts = <0x16 0x8>;
80 + lbc_extra_divider = <0x1>;
81 + reg = <0xf9200000 0x200000>;
82 + device_type = "rb,cf";
83 + };
84 +
85 + cf@f9000000 {
86 + lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
87 + interrupt-at-level = <0x0>;
88 + interrupt-parent = <&ipic>;
89 + interrupts = <0x14 0x8>;
90 + lbc_extra_divider = <0x1>;
91 + reg = <0xf9000000 0x200000>;
92 + device_type = "rb,cf";
93 + };
94 +
95 + flash {
96 + reg = <0xff800000 0x20000>;
97 + };
98 +
99 + nnand {
100 + reg = <0xf0000000 0x1000>;
101 + };
102 +
103 + nand {
104 + ale = <&gpio 0x6>;
105 + cle = <&gpio 0x5>;
106 + nce = <&gpio 0x4>;
107 + rdy = <&gpio 0x3>;
108 + reg = <0xf8000000 0x1000>;
109 + device_type = "rb,nand";
110 + };
111 +
112 + fancon {
113 + interrupt-parent = <&ipic>;
114 + interrupts = <0x17 0x8>;
115 + sense = <&gpio 0x7>;
116 + fan_on = <&gpio 0x9>;
117 + };
118 +
119 + pci0: pci@e0008500 {
120 + device_type = "pci";
121 + compatible = "fsl,mpc8349-pci";
122 + reg = <0xe0008500 0x100 0xe0008300 0x8>;
123 + #address-cells = <3>;
124 + #size-cells = <2>;
125 + #interrupt-cells = <1>;
126 + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
127 + bus-range = <0x0 0x0>;
128 + interrupt-map = <
129 + 0x5800 0x0 0x0 0x1 &ipic 0x15 0x8
130 + 0x6000 0x0 0x0 0x1 &ipic 0x30 0x8
131 + 0x6000 0x0 0x0 0x2 &ipic 0x11 0x8
132 + 0x6800 0x0 0x0 0x1 &ipic 0x11 0x8
133 + 0x6800 0x0 0x0 0x2 &ipic 0x12 0x8
134 + 0x7000 0x0 0x0 0x1 &ipic 0x12 0x8
135 + 0x7000 0x0 0x0 0x2 &ipic 0x13 0x8
136 + 0x7800 0x0 0x0 0x1 &ipic 0x13 0x8
137 + 0x7800 0x0 0x0 0x2 &ipic 0x30 0x8
138 + 0x8000 0x0 0x0 0x1 &ipic 0x30 0x8
139 + 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
140 + 0x8000 0x0 0x0 0x3 &ipic 0x11 0x8
141 + 0x8000 0x0 0x0 0x4 &ipic 0x13 0x8
142 + 0xa000 0x0 0x0 0x1 &ipic 0x30 0x8
143 + 0xa000 0x0 0x0 0x2 &ipic 0x11 0x8
144 + 0xa000 0x0 0x0 0x3 &ipic 0x12 0x8
145 + 0xa000 0x0 0x0 0x4 &ipic 0x13 0x8
146 + 0xa800 0x0 0x0 0x1 &ipic 0x11 0x8
147 + 0xa800 0x0 0x0 0x2 &ipic 0x12 0x8
148 + 0xa800 0x0 0x0 0x3 &ipic 0x13 0x8
149 + 0xa800 0x0 0x0 0x4 &ipic 0x30 0x8>;
150 + interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
151 + interrupt-parent = <&ipic>;
152 + };
153 +
154 + soc8343@e0000000 {
155 + #address-cells = <1>;
156 + #size-cells = <1>;
157 + device_type = "soc";
158 + compatible = "simple-bus";
159 + ranges = <0x0 0xe0000000 0x100000>;
160 + reg = <0xe0000000 0x200>;
161 + bus-frequency = <0x1>;
162 +
163 + led {
164 + user_led = <0x400 0x8>;
165 + };
166 +
167 + beeper {
168 + reg = <0x500 0x100>;
169 + };
170 +
171 + gpio: gpio@0 {
172 + reg = <0xc08 0x4>;
173 + device-id = <0x0>;
174 + compatible = "gpio";
175 + device_type = "gpio";
176 + };
177 +
178 + dma@82a8 {
179 + #address-cells = <1>;
180 + #size-cells = <1>;
181 + compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
182 + reg = <0x82a8 4>;
183 + ranges = <0 0x8100 0x1a8>;
184 + interrupt-parent = <&ipic>;
185 + interrupts = <71 8>;
186 + cell-index = <0>;
187 + dma-channel@0 {
188 + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
189 + reg = <0 0x80>;
190 + cell-index = <0>;
191 + interrupt-parent = <&ipic>;
192 + interrupts = <71 8>;
193 + };
194 + dma-channel@80 {
195 + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
196 + reg = <0x80 0x80>;
197 + cell-index = <1>;
198 + interrupt-parent = <&ipic>;
199 + interrupts = <71 8>;
200 + };
201 + dma-channel@100 {
202 + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
203 + reg = <0x100 0x80>;
204 + cell-index = <2>;
205 + interrupt-parent = <&ipic>;
206 + interrupts = <71 8>;
207 + };
208 + dma-channel@180 {
209 + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
210 + reg = <0x180 0x28>;
211 + cell-index = <3>;
212 + interrupt-parent = <&ipic>;
213 + interrupts = <71 8>;
214 + };
215 + };
216 +
217 + enet0: ethernet@25000 {
218 + #address-cells = <1>;
219 + #size-cells = <1>;
220 + cell-index = <0>;
221 + phy-handle = <&phy0>;
222 + tbi-handle = <&tbi0>;
223 + interrupt-parent = <&ipic>;
224 + interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
225 + local-mac-address = [00 00 00 00 00 00];
226 + reg = <0x25000 0x1000>;
227 + ranges = <0x0 0x25000 0x1000>;
228 + compatible = "gianfar";
229 + model = "TSEC";
230 + device_type = "network";
231 +
232 + mdio@520 {
233 + #address-cells = <1>;
234 + #size-cells = <0>;
235 + compatible = "fsl,gianfar-tbi";
236 + reg = <0x520 0x20>;
237 +
238 + tbi0: tbi-phy@11 {
239 + reg = <0x11>;
240 + device_type = "tbi-phy";
241 + };
242 + };
243 + };
244 +
245 + enet1: ethernet@24000 {
246 + #address-cells = <1>;
247 + #size-cells = <1>;
248 + cell-index = <1>;
249 + phy-handle = <&phy1>;
250 + tbi-handle = <&tbi1>;
251 + interrupt-parent = <&ipic>;
252 + interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
253 + local-mac-address = [00 00 00 00 00 00];
254 + reg = <0x24000 0x1000>;
255 + ranges = <0x0 0x24000 0x1000>;
256 + compatible = "gianfar";
257 + model = "TSEC";
258 + device_type = "network";
259 +
260 + mdio@520 {
261 + #size-cells = <0x0>;
262 + #address-cells = <0x1>;
263 + reg = <0x520 0x20>;
264 + compatible = "fsl,gianfar-mdio";
265 +
266 + phy0: ethernet-phy@0 {
267 + device_type = "ethernet-phy";
268 + reg = <0x0>;
269 + };
270 +
271 + phy1: ethernet-phy@1 {
272 + device_type = "ethernet-phy";
273 + reg = <0x1>;
274 + };
275 +
276 + tbi1: tbi-phy@11 {
277 + reg = <0x11>;
278 + device_type = "tbi-phy";
279 + };
280 + };
281 + };
282 +
283 + ipic: pic@700 {
284 + interrupt-controller;
285 + #address-cells = <0>;
286 + #interrupt-cells = <2>;
287 + reg = <0x700 0x100>;
288 + device_type = "ipic";
289 + };
290 +
291 + serial@4500 {
292 + interrupt-parent = <&ipic>;
293 + interrupts = <0x9 0x8>;
294 + clock-frequency = <0xfe4f840>;
295 + reg = <0x4500 0x100>;
296 + compatible = "ns16550";
297 + device_type = "serial";
298 + };
299 +
300 + wdt@200 {
301 + reg = <0x200 0x100>;
302 + compatible = "mpc83xx_wdt";
303 + device_type = "watchdog";
304 + };
305 + };
306 +};
307 --- /dev/null
308 +++ b/arch/powerpc/boot/rb600.c
309 @@ -0,0 +1,70 @@
310 +/*
311 + * The RouterBOARD platform -- for booting RB600(A) RouterBOARDs.
312 + *
313 + * Author: Michael Guntsche <mike@it-loops.com>
314 + *
315 + * Copyright (c) 2009 Michael Guntsche
316 + *
317 + * This program is free software; you can redistribute it and/or modify it
318 + * under the terms of the GNU General Public License version 2 as published
319 + * by the Free Software Foundation.
320 + */
321 +
322 +#include "ops.h"
323 +#include "types.h"
324 +#include "io.h"
325 +#include "stdio.h"
326 +#include <libfdt.h>
327 +
328 +BSS_STACK(4*1024);
329 +
330 +u64 memsize64;
331 +const void *fw_dtb;
332 +
333 +static void rb600_fixups(void)
334 +{
335 + const u32 *reg, *timebase, *clock;
336 + int node, size;
337 +
338 + dt_fixup_memory(0, memsize64);
339 +
340 + /* Set the MAC addresses. */
341 + node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@24000");
342 + reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
343 + dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg);
344 +
345 + node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@25000");
346 + reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
347 + dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg);
348 +
349 + /* Find the CPU timebase and clock frequencies. */
350 + node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
351 + timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
352 + clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
353 + dt_fixup_cpu_clocks(*clock, *timebase, 0);
354 +
355 +}
356 +
357 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
358 + unsigned long r6, unsigned long r7)
359 +{
360 + const u32 *reg;
361 + int node, size;
362 +
363 + fw_dtb = (const void *)r3;
364 +
365 + /* Find the memory range. */
366 + node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
367 + reg = fdt_getprop(fw_dtb, node, "reg", &size);
368 + memsize64 = reg[1];
369 +
370 + /* Now we have the memory size; initialize the heap. */
371 + simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
372 +
373 + /* Prepare the device tree and find the console. */
374 + fdt_init(_dtb_start);
375 + serial_console_init();
376 +
377 + /* Remaining fixups... */
378 + platform_ops.fixups = rb600_fixups;
379 +}
380 --- a/arch/powerpc/boot/wrapper
381 +++ b/arch/powerpc/boot/wrapper
382 @@ -215,7 +215,7 @@ ps3)
383 link_address=''
384 pie=
385 ;;
386 -ep88xc|ep405|ep8248e)
387 +ep88xc|ep405|ep8248e|rb600|rb333)
388 platformo="$object/fixed-head.o $object/$platform.o"
389 binary=y
390 ;;
391 --- a/arch/powerpc/platforms/83xx/Kconfig
392 +++ b/arch/powerpc/platforms/83xx/Kconfig
393 @@ -38,6 +38,15 @@ config MPC832x_RDB
394 help
395 This option enables support for the MPC8323 RDB board.
396
397 +config RB_PPC
398 + bool "MikroTik RouterBOARD 333/600 series"
399 + select DEFAULT_UIMAGE
400 + select QUICC_ENGINE
401 + select PPC_MPC832x
402 + select PPC_MPC834x
403 + help
404 + This option enables support for MikroTik RouterBOARD 333/600 series boards.
405 +
406 config MPC834x_MDS
407 bool "Freescale MPC834x MDS"
408 select DEFAULT_UIMAGE
409 --- /dev/null
410 +++ b/arch/powerpc/boot/dts/rb333.dts
411 @@ -0,0 +1,426 @@
412 +
413 +/*
414 + * RouterBOARD 333 series Device Tree Source
415 + *
416 + * Copyright 2010 Alexandros C. Couloumbis <alex@ozo.com>
417 + * Copyright 2009 Michael Guntsche <mike@it-loops.com>
418 + *
419 + * This program is free software; you can redistribute it and/or modify it
420 + * under the terms of the GNU General Public License as published by the
421 + * Free Software Foundation; either version 2 of the License, or (at your
422 + * option) any later version.
423 + *
424 + * Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
425 + * Warning (ranges_format): "ranges" property in /qe@e0100000/muram@10000 has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1)
426 + * Warning (avoid_default_addr_size): Relying on default #address-cells value for /qe@e0100000/muram@10000/data-only@0
427 + * Warning (avoid_default_addr_size): Relying on default #size-cells value for /qe@e0100000/muram@10000/data-only@0
428 + * Warning (obsolete_chosen_interrupt_controller): /chosen has obsolete "interrupt-controller" property
429 + *
430 + */
431 +
432 +
433 +/dts-v1/;
434 +
435 +/ {
436 + model = "RB333";
437 + compatible = "MPC83xx";
438 + #size-cells = <1>;
439 + #address-cells = <1>;
440 +
441 + aliases {
442 + ethernet0 = &enet0;
443 + ethernet1 = &enet1;
444 + ethernet2 = &enet2;
445 + pci0 = &pci0;
446 + };
447 +
448 + chosen {
449 + bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
450 + // linux,platform = <0x8062>;
451 + // linux,initrd = <0x488000 0x0>;
452 + linux,stdout-path = "/soc8323@e0000000/serial@4500";
453 + // interrupt-controller = <&ipic>;
454 + };
455 +
456 + cpus {
457 + #cpus = <1>;
458 + #size-cells = <0>;
459 + #address-cells = <1>;
460 +
461 + PowerPC,8323E@0 {
462 + device_type = "cpu";
463 + reg = <0x0>;
464 + i-cache-size = <0x4000>;
465 + d-cache-size = <0x4000>;
466 + i-cache-line-size = <0x20>;
467 + d-cache-line-size = <0x20>;
468 + // clock-frequency = <0x13de3650>;
469 + // timebase-frequency = <0x1fc9f08>;
470 + timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
471 + clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
472 + 32-bit;
473 + };
474 + };
475 +
476 + memory {
477 + device_type = "memory";
478 + reg = <0x0 0x4000000>;
479 + // reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
480 + };
481 +
482 + flash {
483 + reg = <0xfe000000 0x20000>;
484 + };
485 +
486 + nand {
487 + ale = <&gpio2 0x3>;
488 + cle = <&gpio2 0x2>;
489 + nce = <&gpio2 0x1>;
490 + rdy = <&gpio2 0x0>;
491 + reg = <0xf8000000 0x1000>;
492 + device_type = "rb,nand";
493 + };
494 +
495 + nnand {
496 + reg = <0xf0000000 0x1000>;
497 + };
498 +
499 + voltage {
500 + voltage_gpio = <&gpio3 0x11>;
501 + };
502 +
503 + fancon {
504 + interrupt-parent = <&ipic>;
505 + interrupts = <0x14 0x8>;
506 + fan_on = <&gpio0 0x10>;
507 + };
508 +
509 + soc8323@e0000000 {
510 + #address-cells = <1>;
511 + #size-cells = <1>;
512 + device_type = "soc";
513 + compatible = "simple-bus";
514 + ranges = <0x0 0xe0000000 0x00100000>;
515 + reg = <0xe0000000 0x00000200>;
516 + bus-frequency = <1>;
517 +
518 + wdt@200 {
519 + device_type = "watchdog";
520 + compatible = "mpc83xx_wdt";
521 + reg = <0x200 0x100>;
522 + };
523 +
524 + ipic:pic@700 {
525 + interrupt-controller;
526 + #address-cells = <0>;
527 + #interrupt-cells = <2>;
528 + reg = <0x700 0x100>;
529 + device_type = "ipic";
530 + };
531 +
532 + par_io@1400 {
533 + num-ports = <4>;
534 + device_type = "par_io";
535 + reg = <0x1400 0x100>;
536 +
537 + ucc2pio: ucc_pin@02 {
538 + pio-map = <
539 + /* port pin dir open_drain assignment has_irq */
540 + 3 4 3 0 2 0
541 + 3 5 1 0 2 0
542 + 0 18 1 0 1 0
543 + 0 19 1 0 1 0
544 + 0 20 1 0 1 0
545 + 0 21 1 0 1 0
546 + 0 30 1 0 1 0
547 + 3 6 2 0 1 0
548 + 0 29 2 0 1 0
549 + 0 31 2 0 1 0
550 + 0 22 2 0 1 0
551 + 0 23 2 0 1 0
552 + 0 24 2 0 1 0
553 + 0 25 2 0 1 0
554 + 0 28 2 0 1 0
555 + 0 26 2 0 1 0
556 + 3 31 2 0 1 0>;
557 + };
558 +
559 + ucc3pio: ucc_pin@03 {
560 + pio-map = <
561 + /* port pin dir open_drain assignment has_irq */
562 + 1 0 1 0 1 0
563 + 1 1 1 0 1 0
564 + 1 2 1 0 1 0
565 + 1 3 1 0 1 0
566 + 1 12 1 0 1 0
567 + 3 24 2 0 1 0
568 + 1 11 2 0 1 0
569 + 1 13 2 0 1 0
570 + 1 4 2 0 1 0
571 + 1 5 2 0 1 0
572 + 1 6 2 0 1 0
573 + 1 7 2 0 1 0
574 + 1 10 2 0 1 0
575 + 1 8 2 0 1 0
576 + 3 29 2 0 1 0>;
577 + };
578 +
579 + ucc4pio: ucc_pin@04 {
580 + pio-map = <
581 + /* port pin dir open_drain assignment has_irq */
582 + 1 18 1 0 1 0
583 + 1 19 1 0 1 0
584 + 1 20 1 0 1 0
585 + 1 21 1 0 1 0
586 + 1 30 1 0 1 0
587 + 3 20 2 0 1 0
588 + 1 30 2 0 1 0
589 + 1 31 2 0 1 0
590 + 1 22 2 0 1 0
591 + 1 23 2 0 1 0
592 + 1 24 2 0 1 0
593 + 1 25 2 0 1 0
594 + 1 28 2 0 1 0
595 + 1 26 2 0 1 0
596 + 3 21 2 0 1 0>;
597 + };
598 + };
599 +
600 + serial0: serial@4500 {
601 + cell-index = <0>;
602 + device_type = "serial";
603 + compatible = "fsl,ns16550", "ns16550";
604 + reg = <0x4500 0x100>;
605 + clock-frequency = <0x7f27c20>;
606 + interrupts = <9 0x8>;
607 + interrupt-parent = <&ipic>;
608 + };
609 +
610 + dma@82a8 {
611 + #address-cells = <1>;
612 + #size-cells = <1>;
613 + compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
614 + reg = <0x82a8 4>;
615 + ranges = <0 0x8100 0x1a8>;
616 + interrupt-parent = <&ipic>;
617 + interrupts = <71 8>;
618 + cell-index = <0>;
619 + dma-channel@0 {
620 + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
621 + reg = <0 0x80>;
622 + cell-index = <0>;
623 + interrupt-parent = <&ipic>;
624 + interrupts = <71 8>;
625 + };
626 + dma-channel@80 {
627 + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
628 + reg = <0x80 0x80>;
629 + cell-index = <1>;
630 + interrupt-parent = <&ipic>;
631 + interrupts = <71 8>;
632 + };
633 + dma-channel@100 {
634 + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
635 + reg = <0x100 0x80>;
636 + cell-index = <2>;
637 + interrupt-parent = <&ipic>;
638 + interrupts = <71 8>;
639 + };
640 + dma-channel@180 {
641 + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
642 + reg = <0x180 0x28>;
643 + cell-index = <3>;
644 + interrupt-parent = <&ipic>;
645 + interrupts = <71 8>;
646 + };
647 + };
648 +
649 + beeper {
650 + gpio = <&gpio3 0x12>;
651 + reg = <0x500 0x100>;
652 + interrupt-parent = <&ipic>;
653 + interrupts = <0x48 0x8>;
654 + };
655 +
656 + gpio3: gpio@3 {
657 + reg = <0x144c 0x4>;
658 + device-id = <0x3>;
659 + compatible = "qe_gpio";
660 + device_type = "gpio";
661 + };
662 +
663 + gpio2: gpio@2 {
664 + reg = <0x1434 0x4>;
665 + device-id = <0x2>;
666 + compatible = "qe_gpio";
667 + device_type = "gpio";
668 + };
669 +
670 + gpio0: gpio@0 {
671 + reg = <0x1404 0x4>;
672 + device-id = <0x0>;
673 + compatible = "qe_gpio";
674 + device_type = "gpio";
675 + };
676 + };
677 +
678 + pci0: pci@e0008500 {
679 + device_type = "pci";
680 + // compatible = "83xx";
681 + compatible = "fsl,mpc8349-pci";
682 + reg = <0xe0008500 0x100 0xe0008300 0x8>;
683 + #address-cells = <3>;
684 + #size-cells = <2>;
685 + #interrupt-cells = <1>;
686 + // clock-frequency = <0>;
687 + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
688 + bus-range = <0x0 0x0>;
689 + interrupt-map = <
690 + /* IDSEL 0x10 AD16 miniPCI slot 0 */
691 + 0x8000 0x0 0x0 0x1 &ipic 0x11 0x8
692 + 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
693 +
694 + /* IDSEL 0x11 AD17 miniPCI slot 1 */
695 + 0x8800 0x0 0x0 0x1 &ipic 0x12 0x8
696 + 0x8800 0x0 0x0 0x2 &ipic 0x13 0x8
697 +
698 + /* IDSEL 0x12 AD18 miniPCI slot 2 */
699 + 0x9000 0x0 0x0 0x1 &ipic 0x13 0x8
700 + 0x9000 0x0 0x0 0x2 &ipic 0x11 0x8>;
701 +
702 + interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
703 + interrupt-parent = <&ipic>;
704 + // interrupts = <66 0x8>;
705 + };
706 +
707 + qe@e0100000 {
708 + reg = <0xe0100000 0x480>;
709 + ranges = <0x0 0xe0100000 0x100000>;
710 + model = "QE";
711 + device_type = "qe";
712 + compatible = "fsl,qe";
713 + #size-cells = <1>;
714 + #address-cells = <1>;
715 + brg-frequency = <0>;
716 + bus-frequency = <0>;
717 + // bus-frequency = <198000000>;
718 + fsl,qe-num-riscs = <1>;
719 + fsl,qe-num-snums = <28>;
720 +
721 + qeic: qeic@80 {
722 + interrupt-controller;
723 + compatible = "fsl,qe-ic";
724 + big-endian;
725 + built-in;
726 + reg = <0x80 0x80>;
727 + #interrupt-cells = <1>;
728 + #address-cells = <0>;
729 + device_type = "qeic";
730 + interrupts = <0x20 0x8 0x21 0x8>;
731 + interrupt-parent = <&ipic>;
732 + };
733 +
734 + mdio@2120 {
735 + compatible = "ucc_geth_phy";
736 + device_type = "mdio";
737 + reg = <0x3120 0x18>;
738 + #size-cells = <0>;
739 + #address-cells = <1>;
740 +
741 + phy3: ethernet-phy@03 {
742 + // interface = <0x3>;
743 + device_type = "ethernet-phy";
744 + reg = <0x3>;
745 + };
746 +
747 + phy2: ethernet-phy@02 {
748 + // interface = <0x3>;
749 + device_type = "ethernet-phy";
750 + reg = <0x2>;
751 + };
752 +
753 + phy1: ethernet-phy@01 {
754 + // interface = <0x3>;
755 + device_type = "ethernet-phy";
756 + reg = <0x1>;
757 + };
758 + };
759 +
760 + enet0: ucc@2200 {
761 + tx-clock = <0x1a>;
762 + rx-clock = <0x1f>;
763 + local-mac-address = [00 00 00 00 00 00];
764 + interrupt-parent = <&qeic>;
765 + interrupts = <0x22>;
766 + reg = <0x2200 0x200>;
767 + device-id = <0x3>;
768 + model = "UCC";
769 + compatible = "ucc_geth";
770 + device_type = "network";
771 + phy-handle = <&phy2>;
772 + pio-handle = <&ucc3pio>;
773 + };
774 +
775 + enet1: ucc@3200 {
776 + tx-clock = <0x22>;
777 + rx-clock = <0x20>;
778 + local-mac-address = [00 00 00 00 00 00];
779 + interrupt-parent = <&qeic>;
780 + interrupts = <0x23>;
781 + reg = <0x3200 0x200>;
782 + device-id = <0x4>;
783 + model = "UCC";
784 + compatible = "ucc_geth";
785 + device_type = "network";
786 + phy-handle = <&phy3>;
787 + pio-handle = <&ucc4pio>;
788 + };
789 +
790 + enet2: ucc@3000 {
791 + tx-clock = <0x18>;
792 + rx-clock = <0x17>;
793 + local-mac-address = [00 00 00 00 00 00];
794 + interrupt-parent = <&qeic>;
795 + interrupts = <0x21>;
796 + reg = <0x3000 0x200>;
797 + device-id = <0x2>;
798 + model = "UCC";
799 + compatible = "ucc_geth";
800 + device_type = "network";
801 + phy-handle = <&phy1>;
802 + pio-handle = <&ucc2pio>;
803 + };
804 +
805 + spi@500 {
806 + mode = "cpu";
807 + interrupt-parent = <&qeic>;
808 + interrupts = <0x1>;
809 + reg = <0x500 0x40>;
810 + compatible = "fsl,spi";
811 + device_type = "spi";
812 + };
813 +
814 + spi@4c0 {
815 + mode = "cpu";
816 + interrupt-parent = <&qeic>;
817 + interrupts = <0x2>;
818 + reg = <0x4c0 0x40>;
819 + compatible = "fsl,spi";
820 + device_type = "spi";
821 + };
822 +
823 + muram@10000 {
824 + #address-cells = <1>;
825 + #size-cells = <1>;
826 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
827 + ranges = <0x0 0x10000 0x4000>;
828 + device_type = "muram";
829 +
830 + data-only@0 {
831 + compatible = "fsl,qe-muram-data",
832 + "fsl,cpm-muram-data";
833 + reg = <0x0 0x4000>;
834 + };
835 + };
836 + };
837 +};
838 --- /dev/null
839 +++ b/arch/powerpc/boot/rb333.c
840 @@ -0,0 +1,86 @@
841 +/*
842 + * The RouterBOARD platform -- for booting RB333 RouterBOARDs.
843 + *
844 + * Author: Alexandros C. Couloumbis <alex@ozo.com>
845 + * Author: Michael Guntsche <mike@it-loops.com>
846 + *
847 + * Copyright (c) 2010 Alexandros C. Couloumbis
848 + * Copyright (c) 2009 Michael Guntsche
849 + *
850 + * This program is free software; you can redistribute it and/or modify it
851 + * under the terms of the GNU General Public License version 2 as published
852 + * by the Free Software Foundation.
853 + */
854 +
855 +#include "ops.h"
856 +#include "types.h"
857 +#include "io.h"
858 +#include "stdio.h"
859 +#include <libfdt.h>
860 +
861 +BSS_STACK(4*1024);
862 +
863 +u64 memsize64;
864 +const void *fw_dtb;
865 +
866 +static void rb333_fixups(void)
867 +{
868 + const u32 *reg, *timebase, *clock;
869 + int node, size;
870 + void *chosen;
871 + const char* bootargs;
872 +
873 + dt_fixup_memory(0, memsize64);
874 +
875 + /* Find the CPU timebase and clock frequencies. */
876 + node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
877 + timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
878 + clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
879 + dt_fixup_cpu_clocks(*clock, *timebase, 0);
880 +
881 + /* Set the MAC addresses. */
882 + node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@2200");
883 + reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
884 + dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg);
885 +
886 + node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@3200");
887 + reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
888 + dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg);
889 +
890 + node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@3000");
891 + reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
892 + dt_fixup_mac_address_by_alias("ethernet2", (const u8 *)reg);
893 +
894 + /* Fixup chosen
895 + * The bootloader reads the kernelparm segment and adds the content to
896 + * bootargs. This is needed to specify root and other boot flags.
897 + */
898 + chosen = finddevice("/chosen");
899 + node = fdt_path_offset(fw_dtb, "/chosen");
900 + bootargs = fdt_getprop(fw_dtb, node, "bootargs", &size);
901 + setprop_str(chosen, "bootargs", bootargs);
902 +}
903 +
904 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
905 + unsigned long r6, unsigned long r7)
906 +{
907 + const u32 *reg;
908 + int node, size;
909 +
910 + fw_dtb = (const void *)r3;
911 +
912 + /* Find the memory range. */
913 + node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
914 + reg = fdt_getprop(fw_dtb, node, "reg", &size);
915 + memsize64 = reg[1];
916 +
917 + /* Now we have the memory size; initialize the heap. */
918 + simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
919 +
920 + /* Prepare the device tree and find the console. */
921 + fdt_init(_dtb_start);
922 + serial_console_init();
923 +
924 + /* Remaining fixups... */
925 + platform_ops.fixups = rb333_fixups;
926 +}
927 --- /dev/null
928 +++ b/arch/powerpc/platforms/83xx/rbppc.c
929 @@ -0,0 +1,388 @@
930 +/*
931 + * Copyright (C) 2010 Alexandros C. Couloumbis <alex@ozo.com>
932 + * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
933 + * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
934 + * Copyright (C) Mikrotik 2007
935 + *
936 + * This program is free software; you can redistribute it and/or modify it
937 + * under the terms of the GNU General Public License as published by the
938 + * Free Software Foundation; either version 2 of the License, or (at your
939 + * option) any later version.
940 + */
941 +
942 +#include <linux/delay.h>
943 +#include <linux/root_dev.h>
944 +#include <linux/initrd.h>
945 +#include <linux/interrupt.h>
946 +#include <linux/of_platform.h>
947 +#include <linux/of_device.h>
948 +#include <linux/of_platform.h>
949 +#include <linux/pci.h>
950 +#include <asm/time.h>
951 +#include <asm/ipic.h>
952 +#include <asm/udbg.h>
953 +#include <asm/qe.h>
954 +#include <asm/qe_ic.h>
955 +#include <sysdev/fsl_soc.h>
956 +#include <sysdev/fsl_pci.h>
957 +#include "mpc83xx.h"
958 +
959 +#define SYSCTL 0x100
960 +#define SICRL 0x014
961 +
962 +#define GTCFR2 0x04
963 +#define GTMDR4 0x22
964 +#define GTRFR4 0x26
965 +#define GTCNR4 0x2e
966 +#define GTVER4 0x36
967 +#define GTPSR4 0x3e
968 +
969 +#define GTCFR_BCM 0x40
970 +#define GTCFR_STP4 0x20
971 +#define GTCFR_RST4 0x10
972 +#define GTCFR_STP3 0x02
973 +#define GTCFR_RST3 0x01
974 +
975 +#define GTMDR_ORI 0x10
976 +#define GTMDR_FRR 0x08
977 +#define GTMDR_ICLK16 0x04
978 +
979 +extern int par_io_data_set(u8 port, u8 pin, u8 val);
980 +extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
981 + int assignment, int has_irq);
982 +
983 +static unsigned timer_freq;
984 +static void *gtm;
985 +
986 +static int beeper_irq;
987 +static unsigned beeper_gpio_pin[2];
988 +
989 +int rb333model = 0;
990 +
991 +irqreturn_t rbppc_timer_irq(int irq, void *ptr)
992 +{
993 + static int toggle = 0;
994 +
995 + par_io_data_set(beeper_gpio_pin[0], beeper_gpio_pin[1], toggle);
996 + toggle = !toggle;
997 +
998 + /* ack interrupt */
999 + out_be16(gtm + GTVER4, 3);
1000 +
1001 + return IRQ_HANDLED;
1002 +}
1003 +
1004 +void rbppc_beep(unsigned freq)
1005 +{
1006 + unsigned gtmdr;
1007 +
1008 + if (freq > 5000) freq = 5000;
1009 +
1010 + if (!gtm)
1011 + return;
1012 + if (!freq) {
1013 + out_8(gtm + GTCFR2, GTCFR_STP4 | GTCFR_STP3);
1014 + return;
1015 + }
1016 +
1017 + out_8(gtm + GTCFR2, GTCFR_RST4 | GTCFR_STP3);
1018 + out_be16(gtm + GTPSR4, 255);
1019 + gtmdr = GTMDR_FRR | GTMDR_ICLK16;
1020 + if (beeper_irq != NO_IRQ) gtmdr |= GTMDR_ORI;
1021 + out_be16(gtm + GTMDR4, gtmdr);
1022 + out_be16(gtm + GTVER4, 3);
1023 +
1024 + out_be16(gtm + GTRFR4, timer_freq / 16 / 256 / freq / 2);
1025 + out_be16(gtm + GTCNR4, 0);
1026 +}
1027 +EXPORT_SYMBOL(rbppc_beep);
1028 +
1029 +static void __init rbppc_setup_arch(void)
1030 +{
1031 + struct device_node *np;
1032 +
1033 + np = of_find_node_by_type(NULL, "cpu");
1034 + if (np) {
1035 + const unsigned *fp = of_get_property(np, "clock-frequency", NULL);
1036 + loops_per_jiffy = fp ? *fp / HZ : 0;
1037 +
1038 + of_node_put(np);
1039 + }
1040 +
1041 + np = of_find_node_by_name(NULL, "serial");
1042 + if (np) {
1043 + timer_freq =
1044 + *(unsigned *) of_get_property(np, "clock-frequency", NULL);
1045 + of_node_put(np);
1046 + }
1047 +
1048 +#ifdef CONFIG_PCI
1049 + np = of_find_node_by_type(NULL, "pci");
1050 + if (np) {
1051 + mpc83xx_add_bridge(np);
1052 + }
1053 +#endif
1054 +
1055 +if (rb333model) {
1056 +
1057 +#ifdef CONFIG_QUICC_ENGINE
1058 + qe_reset();
1059 +
1060 + if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
1061 + par_io_init(np);
1062 + of_node_put(np);
1063 +
1064 + for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
1065 + par_io_of_config(np);
1066 + }
1067 +#endif
1068 +
1069 +} /* RB333 */
1070 +
1071 +}
1072 +
1073 +void __init rbppc_init_IRQ(void)
1074 +{
1075 + struct device_node *np;
1076 +
1077 + np = of_find_node_by_type(NULL, "ipic");
1078 + if (np) {
1079 + ipic_init(np, 0);
1080 + ipic_set_default_priority();
1081 + of_node_put(np);
1082 + }
1083 +
1084 +if (rb333model) {
1085 +
1086 +#ifdef CONFIG_QUICC_ENGINE
1087 + np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
1088 + if (!np) {
1089 + np = of_find_node_by_type(NULL, "qeic");
1090 + if (!np)
1091 + return;
1092 + }
1093 + qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
1094 + of_node_put(np);
1095 +#endif /* CONFIG_QUICC_ENGINE */
1096 +
1097 +} /* RB333 */
1098 +
1099 +}
1100 +
1101 +static int __init rbppc_probe(void)
1102 +{
1103 + char *model;
1104 +
1105 + model = of_get_flat_dt_prop(of_get_flat_dt_root(), "model", NULL);
1106 +
1107 + if (!model)
1108 + return 0;
1109 +
1110 + if (strcmp(model, "RB333") == 0) {
1111 + rb333model = 1;
1112 + return 1;
1113 + }
1114 +
1115 + if (strcmp(model, "RB600") == 0)
1116 + return 1;
1117 +
1118 + return 0;
1119 +}
1120 +
1121 +static void __init rbppc_beeper_init(struct device_node *beeper)
1122 +{
1123 + struct resource res;
1124 + struct device_node *gpio;
1125 + const unsigned *pin;
1126 + const unsigned *gpio_id;
1127 +
1128 + if (of_address_to_resource(beeper, 0, &res)) {
1129 + printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No region specified\n", beeper->full_name);
1130 + return;
1131 + }
1132 +
1133 + pin = of_get_property(beeper, "gpio", NULL);
1134 + if (pin) {
1135 + gpio = of_find_node_by_phandle(pin[0]);
1136 +
1137 + if (!gpio) {
1138 + printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: GPIO handle %x not found\n", beeper->full_name, pin[0]);
1139 + return;
1140 + }
1141 +
1142 + gpio_id = of_get_property(gpio, "device-id", NULL);
1143 + if (!gpio_id) {
1144 + printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No device-id specified in GPIO\n", beeper->full_name);
1145 + return;
1146 + }
1147 +
1148 + beeper_gpio_pin[0] = *gpio_id;
1149 + beeper_gpio_pin[1] = pin[1];
1150 +
1151 + par_io_config_pin(*gpio_id, pin[1], 1, 0, 0, 0);
1152 + } else {
1153 + void *sysctl;
1154 +
1155 + sysctl = ioremap_nocache(get_immrbase() + SYSCTL, 0x100);
1156 + out_be32(sysctl + SICRL,
1157 + in_be32(sysctl + SICRL) | (1 << (31 - 19)));
1158 + iounmap(sysctl);
1159 + }
1160 +
1161 + gtm = ioremap_nocache(res.start, res.end - res.start + 1);
1162 +
1163 + beeper_irq = irq_of_parse_and_map(beeper, 0);
1164 + if (beeper_irq != NO_IRQ) {
1165 + int e = request_irq(beeper_irq, rbppc_timer_irq, 0, "beeper", NULL);
1166 + if (e) {
1167 + printk(KERN_ERR "rbppc_beeper_init(%s): Request of beeper irq failed!\n", beeper->full_name);
1168 + }
1169 + }
1170 +}
1171 +
1172 +#define SBIT(x) (0x80000000 >> (x))
1173 +#define DBIT(x, y) ((y) << (32 - (((x % 16) + 1) * 2)))
1174 +
1175 +#define GPIO_DIR_RB333(x) ((x) + (0x1408 >> 2))
1176 +#define GPIO_DATA_RB333(x) ((x) + (0x1404 >> 2))
1177 +
1178 +#define SICRL_RB600(x) ((x) + (0x114 >> 2))
1179 +#define GPIO_DIR_RB600(x) ((x) + (0xc00 >> 2))
1180 +#define GPIO_DATA_RB600(x) ((x) + (0xc08 >> 2))
1181 +
1182 +static void rbppc_restart(char *cmd)
1183 +{
1184 + __be32 __iomem *reg;
1185 + unsigned rb_model;
1186 + struct device_node *root;
1187 + unsigned int size;
1188 +
1189 + root = of_find_node_by_path("/");
1190 + if (root) {
1191 + const char *prop = (char *) of_get_property(root, "model", &size);
1192 + rb_model = prop[sizeof("RB") - 1] - '0';
1193 + of_node_put(root);
1194 + switch (rb_model) {
1195 + case 3:
1196 + reg = ioremap(get_immrbase(), 0x2000);
1197 + local_irq_disable();
1198 + out_be32(GPIO_DIR_RB333(reg),
1199 + (in_be32(GPIO_DIR_RB333(reg)) & ~DBIT(4, 3)) | DBIT(4, 1));
1200 + out_be32(GPIO_DATA_RB333(reg), in_be32(GPIO_DATA_RB333(reg)) & ~SBIT(4));
1201 + break;
1202 + case 6:
1203 + reg = ioremap(get_immrbase(), 0x1000);
1204 + local_irq_disable();
1205 + out_be32(SICRL_RB600(reg), in_be32(SICRL_RB600(reg)) & ~0x00800000);
1206 + out_be32(GPIO_DIR_RB600(reg), in_be32(GPIO_DIR_RB600(reg)) | SBIT(2));
1207 + out_be32(GPIO_DATA_RB600(reg), in_be32(GPIO_DATA_RB600(reg)) & ~SBIT(2));
1208 + break;
1209 + default:
1210 + mpc83xx_restart(cmd);
1211 + break;
1212 + }
1213 + }
1214 + else mpc83xx_restart(cmd);
1215 +
1216 + for (;;) ;
1217 +}
1218 +
1219 +static void rbppc_halt(void)
1220 +{
1221 + while (1);
1222 +}
1223 +
1224 +static struct of_device_id rbppc_ids[] = {
1225 + { .type = "soc", },
1226 + { .compatible = "soc", },
1227 + { .compatible = "simple-bus", },
1228 + { .type = "qe", },
1229 + { .compatible = "fsl,qe", },
1230 + { .compatible = "gianfar", },
1231 + { },
1232 +};
1233 +
1234 +static int __init rbppc_declare_of_platform_devices(void)
1235 +{
1236 + struct device_node *np;
1237 + unsigned idx;
1238 +
1239 + of_platform_bus_probe(NULL, rbppc_ids, NULL);
1240 +
1241 + np = of_find_node_by_type(NULL, "mdio");
1242 + if (np) {
1243 + unsigned len;
1244 + unsigned *res;
1245 + const unsigned *eres;
1246 + struct device_node *ep;
1247 +
1248 + ep = of_find_compatible_node(NULL, "network", "ucc_geth");
1249 + if (ep) {
1250 + eres = of_get_property(ep, "reg", &len);
1251 + res = (unsigned *) of_get_property(np, "reg", &len);
1252 + if (res && eres) {
1253 + res[0] = eres[0] + 0x120;
1254 + }
1255 + }
1256 + }
1257 +
1258 + np = of_find_node_by_name(NULL, "nand");
1259 + if (np) {
1260 + of_platform_device_create(np, "nand", NULL);
1261 + }
1262 +
1263 + idx = 0;
1264 + for_each_node_by_type(np, "rb,cf") {
1265 + char dev_name[12];
1266 + snprintf(dev_name, sizeof(dev_name), "cf.%u", idx);
1267 + of_platform_device_create(np, dev_name, NULL);
1268 + ++idx;
1269 + }
1270 +
1271 + np = of_find_node_by_name(NULL, "beeper");
1272 + if (np) {
1273 + rbppc_beeper_init(np);
1274 + }
1275 +
1276 + return 0;
1277 +}
1278 +machine_device_initcall(rb600, rbppc_declare_of_platform_devices);
1279 +
1280 +define_machine(rb600) {
1281 + .name = "MikroTik RouterBOARD 333/600 series",
1282 + .probe = rbppc_probe,
1283 + .setup_arch = rbppc_setup_arch,
1284 + .init_IRQ = rbppc_init_IRQ,
1285 + .get_irq = ipic_get_irq,
1286 + .restart = rbppc_restart,
1287 + .halt = rbppc_halt,
1288 + .time_init = mpc83xx_time_init,
1289 + .calibrate_decr = generic_calibrate_decr,
1290 +};
1291 +
1292 +static void fixup_pcibridge(struct pci_dev *dev)
1293 +{
1294 + if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1295 + /* let the kernel itself set right memory windows */
1296 + pci_write_config_word(dev, PCI_MEMORY_BASE, 0);
1297 + pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
1298 + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0);
1299 + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
1300 + pci_write_config_byte(dev, PCI_IO_BASE, 0);
1301 + pci_write_config_byte(dev, PCI_IO_LIMIT, 4 << 4);
1302 +
1303 + pci_write_config_byte(
1304 + dev, PCI_COMMAND,
1305 + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
1306 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
1307 + }
1308 +}
1309 +
1310 +
1311 +static void fixup_rb604(struct pci_dev *dev)
1312 +{
1313 + pci_write_config_byte(dev, 0xC0, 0x01);
1314 +}
1315 +
1316 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_pcibridge)
1317 +DECLARE_PCI_FIXUP_HEADER(0x3388, 0x0021, fixup_rb604)
OpenWrt Source Repository