1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (C) 2019 Marvell International Ltd.
5 * Device tree for the CN9132-DB board.
9 #include "puzzle-thermal.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
15 model = "iEi Puzzle-M902";
16 compatible = "iei,puzzle-m902",
17 "marvell,armada-ap807-quad", "marvell,armada-ap807";
20 stdout-path = "serial0:115200n8";
32 ethernet0 = &cp0_eth0;
33 ethernet1 = &cp0_eth1;
34 ethernet2 = &cp0_eth2;
35 ethernet3 = &cp1_eth0;
36 ethernet4 = &cp1_eth1;
37 ethernet5 = &cp1_eth2;
38 ethernet6 = &cp2_eth0;
39 ethernet7 = &cp2_eth1;
40 ethernet8 = &cp2_eth2;
43 led-boot = &led_power;
44 led-failsafe = &led_info;
45 led-running = &led_power;
46 led-upgrade = &led_info;
50 device_type = "memory";
51 reg = <0x0 0x0 0x0 0x80000000>;
55 compatible = "gpio-keys";
59 linux,code = <KEY_RESTART>;
60 gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
64 cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
65 compatible = "regulator-fixed";
66 regulator-name = "cp2-xhci0-vbus";
67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>;
70 gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
73 cp2_usb3_0_phy0: cp2_usb3_phy0 {
74 compatible = "usb-nop-xceiv";
75 vcc-supply = <&cp2_reg_usb3_vbus0>;
78 cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
79 compatible = "regulator-fixed";
80 regulator-name = "cp2-xhci1-vbus";
81 regulator-min-microvolt = <5000000>;
82 regulator-max-microvolt = <5000000>;
84 gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
87 cp2_usb3_0_phy1: cp2_usb3_phy1 {
88 compatible = "usb-nop-xceiv";
89 vcc-supply = <&cp2_reg_usb3_vbus1>;
92 cp2_sfp_eth0: sfp-eth0 {
93 compatible = "sff,sfp";
94 i2c-bus = <&cp2_sfpp0_i2c>;
95 los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
96 mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
97 tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
98 tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
111 compatible = "iei,wt61p803-puzzle";
112 #address-cells = <1>;
114 current-speed = <115200>;
119 compatible = "iei,wt61p803-puzzle-leds";
120 #address-cells = <1>;
126 label = "white:network";
132 label = "green:cloud";
138 label = "orange:info";
144 label = "yellow:power";
146 default-state = "on";
151 compatible = "iei,wt61p803-puzzle-hwmon";
152 #address-cells = <1>;
155 chassis_fan_group0: fan-group@0 {
156 #cooling-cells = <2>;
158 cooling-levels = <80 102 170 230 255>;
165 PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
169 PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
173 /* on-board eMMC - U9 */
175 pinctrl-names = "default";
188 cp0_nbaset_phy0: ethernet-phy@0 {
189 compatible = "ethernet-phy-ieee802.3-c45";
192 cp0_nbaset_phy1: ethernet-phy@1 {
193 compatible = "ethernet-phy-ieee802.3-c45";
196 cp0_nbaset_phy2: ethernet-phy@2 {
197 compatible = "ethernet-phy-ieee802.3-c45";
206 /* SLM-1521-V2, CON9 */
209 phy-mode = "10gbase-kr";
210 phys = <&cp0_comphy2 0>;
211 phy = <&cp0_nbaset_phy0>;
216 phy-mode = "2500base-x";
217 phys = <&cp0_comphy4 1>;
218 phy = <&cp0_nbaset_phy1>;
223 phy-mode = "2500base-x";
224 phys = <&cp0_comphy1 2>;
225 phy = <&cp0_nbaset_phy2>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&cp0_i2c0_pins>;
240 clock-frequency = <100000>;
242 compatible = "epson,rx8130";
249 clock-frequency = <100000>;
252 /* SLM-1521-V2, CON6 */
257 phys = <&cp0_comphy0 1>;
265 phys = <&cp0_comphy5 2>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&cp0_spi0_pins>;
272 reg = <0x700680 0x50>, /* control */
273 <0x2000000 0x1000000>; /* CS0 */
276 #address-cells = <0x1>;
278 compatible = "jedec,spi-nor";
280 spi-max-frequency = <40000000>;
282 compatible = "fixed-partitions";
283 #address-cells = <1>;
287 reg = <0x0 0x1f0000>;
290 label = "U-Boot ENV Factory";
291 reg = <0x1f0000 0x10000>;
295 reg = <0x200000 0x1f0000>;
298 label = "U-Boot ENV";
299 reg = <0x3f0000 0x10000>;
306 cp0_pinctrl: pinctrl {
307 compatible = "marvell,cp115-standalone-pinctrl";
308 cp0_i2c0_pins: cp0-i2c-pins-0 {
309 marvell,pins = "mpp37", "mpp38";
310 marvell,function = "i2c0";
312 cp0_i2c1_pins: cp0-i2c-pins-1 {
313 marvell,pins = "mpp35", "mpp36";
314 marvell,function = "i2c1";
316 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
317 marvell,pins = "mpp0", "mpp1", "mpp2",
318 "mpp3", "mpp4", "mpp5",
319 "mpp6", "mpp7", "mpp8",
320 "mpp9", "mpp10", "mpp11";
321 marvell,function = "ge0";
323 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
324 marvell,pins = "mpp44", "mpp45", "mpp46",
325 "mpp47", "mpp48", "mpp49",
326 "mpp50", "mpp51", "mpp52",
327 "mpp53", "mpp54", "mpp55";
328 marvell,function = "ge1";
330 cp0_spi0_pins: cp0-spi-pins-0 {
331 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
332 marvell,function = "spi1";
339 phys = <&cp0_comphy3 1>;
344 * Instantiate the first connected CP115
347 #define CP11X_NAME cp1
348 #define CP11X_BASE f4000000
349 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
350 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
351 #define CP11X_PCIE0_BASE f4600000
352 #define CP11X_PCIE1_BASE f4620000
353 #define CP11X_PCIE2_BASE f4640000
355 #include "armada-cp115.dtsi"
359 #undef CP11X_PCIEx_MEM_BASE
360 #undef CP11X_PCIEx_MEM_SIZE
361 #undef CP11X_PCIE0_BASE
362 #undef CP11X_PCIE1_BASE
363 #undef CP11X_PCIE2_BASE
371 cp1_nbaset_phy0: ethernet-phy@3 {
372 compatible = "ethernet-phy-ieee802.3-c45";
375 cp1_nbaset_phy1: ethernet-phy@4 {
376 compatible = "ethernet-phy-ieee802.3-c45";
379 cp1_nbaset_phy2: ethernet-phy@5 {
380 compatible = "ethernet-phy-ieee802.3-c45";
392 phy-mode = "10gbase-kr";
393 phys = <&cp1_comphy2 0>;
394 phy = <&cp1_nbaset_phy0>;
399 phy-mode = "2500base-x";
400 phys = <&cp1_comphy4 1>;
401 phy = <&cp1_nbaset_phy1>;
406 phy-mode = "2500base-x";
407 phys = <&cp1_comphy1 2>;
408 phy = <&cp1_nbaset_phy2>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&cp1_i2c0_pins>;
423 clock-frequency = <100000>;
427 cp1_pinctrl: pinctrl {
428 compatible = "marvell,cp115-standalone-pinctrl";
429 cp1_i2c0_pins: cp1-i2c-pins-0 {
430 marvell,pins = "mpp37", "mpp38";
431 marvell,function = "i2c0";
433 cp1_spi0_pins: cp1-spi-pins-0 {
434 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
435 marvell,function = "spi1";
437 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
438 marvell,pins = "mpp3";
439 marvell,function = "gpio";
445 PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
449 * Instantiate the second connected CP115
452 #define CP11X_NAME cp2
453 #define CP11X_BASE f6000000
454 #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
455 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
456 #define CP11X_PCIE0_BASE f6600000
457 #define CP11X_PCIE1_BASE f6620000
458 #define CP11X_PCIE2_BASE f6640000
460 #include "armada-cp115.dtsi"
464 #undef CP11X_PCIEx_MEM_BASE
465 #undef CP11X_PCIEx_MEM_SIZE
466 #undef CP11X_PCIE0_BASE
467 #undef CP11X_PCIE1_BASE
468 #undef CP11X_PCIE2_BASE
480 cp2_nbaset_phy0: ethernet-phy@6 {
481 compatible = "ethernet-phy-ieee802.3-c45";
484 cp2_nbaset_phy1: ethernet-phy@7 {
485 compatible = "ethernet-phy-ieee802.3-c45";
488 cp2_nbaset_phy2: ethernet-phy@8 {
489 compatible = "ethernet-phy-ieee802.3-c45";
494 /* SLM-1521-V2, CON9 */
497 phy-mode = "10gbase-kr";
498 phys = <&cp2_comphy2 0>;
499 phy = <&cp2_nbaset_phy0>;
504 phy-mode = "2500base-x";
505 phys = <&cp2_comphy4 1>;
506 phy = <&cp2_nbaset_phy1>;
511 phy-mode = "2500base-x";
512 phys = <&cp2_comphy1 2>;
513 phy = <&cp2_nbaset_phy2>;
525 clock-frequency = <100000>;
526 /* SLM-1521-V2 - U3 */
528 compatible = "nxp,pca9544";
529 #address-cells = <1>;
532 cp2_sfpp0_i2c: i2c@0 {
533 #address-cells = <1>;
539 #address-cells = <1>;
543 cp2_module_expander1: pca9555@21 {
544 compatible = "nxp,pca9555";
545 pinctrl-names = "default";
555 cp2_pinctrl: pinctrl {
556 compatible = "marvell,cp115-standalone-pinctrl";
557 cp2_i2c0_pins: cp2-i2c-pins-0 {
558 marvell,pins = "mpp37", "mpp38";
559 marvell,function = "i2c0";
565 PUZZLE_FAN_THERMAL(cp2, &chassis_fan_group0);