1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (C) 2019 Marvell International Ltd.
5 * Device tree for the CN9132-DB board.
9 #include "puzzle-thermal.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
16 model = "iEi Puzzle-M902";
17 compatible = "iei,puzzle-m902",
18 "marvell,armada-ap807-quad", "marvell,armada-ap807";
21 stdout-path = "serial0:115200n8";
33 ethernet0 = &cp0_eth0;
34 ethernet1 = &cp0_eth1;
35 ethernet2 = &cp0_eth2;
36 ethernet3 = &cp1_eth0;
37 ethernet4 = &cp1_eth1;
38 ethernet5 = &cp1_eth2;
39 ethernet6 = &cp2_eth0;
40 ethernet7 = &cp2_eth1;
41 ethernet8 = &cp2_eth2;
44 led-boot = &led_power;
45 led-failsafe = &led_info;
46 led-running = &led_power;
47 led-upgrade = &led_info;
51 device_type = "memory";
52 reg = <0x0 0x0 0x0 0x80000000>;
56 compatible = "gpio-keys";
60 linux,code = <KEY_RESTART>;
61 gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
65 cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
66 compatible = "regulator-fixed";
67 regulator-name = "cp2-xhci0-vbus";
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
71 gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
74 cp2_usb3_0_phy0: cp2_usb3_phy0 {
75 compatible = "usb-nop-xceiv";
76 vcc-supply = <&cp2_reg_usb3_vbus0>;
79 cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
80 compatible = "regulator-fixed";
81 regulator-name = "cp2-xhci1-vbus";
82 regulator-min-microvolt = <5000000>;
83 regulator-max-microvolt = <5000000>;
85 gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
88 cp2_usb3_0_phy1: cp2_usb3_phy1 {
89 compatible = "usb-nop-xceiv";
90 vcc-supply = <&cp2_reg_usb3_vbus1>;
93 cp2_sfp_eth0: sfp-eth0 {
94 compatible = "sff,sfp";
95 i2c-bus = <&cp2_sfpp0_i2c>;
96 los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
97 mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
98 tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
99 tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
112 compatible = "iei,wt61p803-puzzle";
113 #address-cells = <1>;
115 current-speed = <115200>;
120 compatible = "iei,wt61p803-puzzle-leds";
121 #address-cells = <1>;
127 label = "white:network";
133 label = "green:cloud";
139 label = "orange:info";
145 function = LED_FUNCTION_POWER;
146 color = <LED_COLOR_ID_YELLOW>;
148 default-state = "on";
153 compatible = "iei,wt61p803-puzzle-hwmon";
154 #address-cells = <1>;
157 chassis_fan_group0: fan-group@0 {
158 #cooling-cells = <2>;
160 cooling-levels = <0 159 195 211 223 241 255>;
167 PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
171 PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
175 /* on-board eMMC - U9 */
177 pinctrl-names = "default";
190 cp0_nbaset_phy0: ethernet-phy@0 {
191 compatible = "ethernet-phy-ieee802.3-c45";
194 cp0_nbaset_phy1: ethernet-phy@1 {
195 compatible = "ethernet-phy-ieee802.3-c45";
198 cp0_nbaset_phy2: ethernet-phy@2 {
199 compatible = "ethernet-phy-ieee802.3-c45";
208 /* SLM-1521-V2, CON9 */
211 phy-mode = "10gbase-kr";
212 phys = <&cp0_comphy2 0>;
213 phy = <&cp0_nbaset_phy0>;
218 phy-mode = "2500base-x";
219 phys = <&cp0_comphy4 1>;
220 phy = <&cp0_nbaset_phy1>;
225 phy-mode = "2500base-x";
226 phys = <&cp0_comphy1 2>;
227 phy = <&cp0_nbaset_phy2>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&cp0_i2c0_pins>;
242 clock-frequency = <100000>;
244 compatible = "epson,rx8130";
251 clock-frequency = <100000>;
254 /* SLM-1521-V2, CON6 */
259 phys = <&cp0_comphy0 1>;
267 phys = <&cp0_comphy5 2>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&cp0_spi0_pins>;
274 reg = <0x700680 0x50>, /* control */
275 <0x2000000 0x1000000>; /* CS0 */
278 #address-cells = <0x1>;
280 compatible = "jedec,spi-nor";
282 spi-max-frequency = <40000000>;
284 compatible = "fixed-partitions";
285 #address-cells = <1>;
289 reg = <0x0 0x1f0000>;
292 label = "U-Boot ENV Factory";
293 reg = <0x1f0000 0x10000>;
297 reg = <0x200000 0x1f0000>;
300 label = "U-Boot ENV";
301 reg = <0x3f0000 0x10000>;
312 cp0_pinctrl: pinctrl {
313 compatible = "marvell,cp115-standalone-pinctrl";
314 cp0_i2c0_pins: cp0-i2c-pins-0 {
315 marvell,pins = "mpp37", "mpp38";
316 marvell,function = "i2c0";
318 cp0_i2c1_pins: cp0-i2c-pins-1 {
319 marvell,pins = "mpp35", "mpp36";
320 marvell,function = "i2c1";
322 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
323 marvell,pins = "mpp0", "mpp1", "mpp2",
324 "mpp3", "mpp4", "mpp5",
325 "mpp6", "mpp7", "mpp8",
326 "mpp9", "mpp10", "mpp11";
327 marvell,function = "ge0";
329 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
330 marvell,pins = "mpp44", "mpp45", "mpp46",
331 "mpp47", "mpp48", "mpp49",
332 "mpp50", "mpp51", "mpp52",
333 "mpp53", "mpp54", "mpp55";
334 marvell,function = "ge1";
336 cp0_spi0_pins: cp0-spi-pins-0 {
337 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
338 marvell,function = "spi1";
345 phys = <&cp0_comphy3 1>;
350 * Instantiate the first connected CP115
353 #define CP11X_NAME cp1
354 #define CP11X_BASE f4000000
355 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
356 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
357 #define CP11X_PCIE0_BASE f4600000
358 #define CP11X_PCIE1_BASE f4620000
359 #define CP11X_PCIE2_BASE f4640000
361 #include "armada-cp115.dtsi"
365 #undef CP11X_PCIEx_MEM_BASE
366 #undef CP11X_PCIEx_MEM_SIZE
367 #undef CP11X_PCIE0_BASE
368 #undef CP11X_PCIE1_BASE
369 #undef CP11X_PCIE2_BASE
377 cp1_nbaset_phy0: ethernet-phy@3 {
378 compatible = "ethernet-phy-ieee802.3-c45";
381 cp1_nbaset_phy1: ethernet-phy@4 {
382 compatible = "ethernet-phy-ieee802.3-c45";
385 cp1_nbaset_phy2: ethernet-phy@5 {
386 compatible = "ethernet-phy-ieee802.3-c45";
398 phy-mode = "10gbase-kr";
399 phys = <&cp1_comphy2 0>;
400 phy = <&cp1_nbaset_phy0>;
405 phy-mode = "2500base-x";
406 phys = <&cp1_comphy4 1>;
407 phy = <&cp1_nbaset_phy1>;
412 phy-mode = "2500base-x";
413 phys = <&cp1_comphy1 2>;
414 phy = <&cp1_nbaset_phy2>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&cp1_i2c0_pins>;
429 clock-frequency = <100000>;
437 cp1_pinctrl: pinctrl {
438 compatible = "marvell,cp115-standalone-pinctrl";
439 cp1_i2c0_pins: cp1-i2c-pins-0 {
440 marvell,pins = "mpp37", "mpp38";
441 marvell,function = "i2c0";
443 cp1_spi0_pins: cp1-spi-pins-0 {
444 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
445 marvell,function = "spi1";
447 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
448 marvell,pins = "mpp3";
449 marvell,function = "gpio";
455 PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
459 * Instantiate the second connected CP115
462 #define CP11X_NAME cp2
463 #define CP11X_BASE f6000000
464 #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
465 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
466 #define CP11X_PCIE0_BASE f6600000
467 #define CP11X_PCIE1_BASE f6620000
468 #define CP11X_PCIE2_BASE f6640000
470 #include "armada-cp115.dtsi"
474 #undef CP11X_PCIEx_MEM_BASE
475 #undef CP11X_PCIEx_MEM_SIZE
476 #undef CP11X_PCIE0_BASE
477 #undef CP11X_PCIE1_BASE
478 #undef CP11X_PCIE2_BASE
490 cp2_nbaset_phy0: ethernet-phy@6 {
491 compatible = "ethernet-phy-ieee802.3-c45";
494 cp2_nbaset_phy1: ethernet-phy@7 {
495 compatible = "ethernet-phy-ieee802.3-c45";
498 cp2_nbaset_phy2: ethernet-phy@8 {
499 compatible = "ethernet-phy-ieee802.3-c45";
504 /* SLM-1521-V2, CON9 */
507 phy-mode = "10gbase-kr";
508 phys = <&cp2_comphy2 0>;
509 phy = <&cp2_nbaset_phy0>;
514 phy-mode = "2500base-x";
515 phys = <&cp2_comphy4 1>;
516 phy = <&cp2_nbaset_phy1>;
521 phy-mode = "2500base-x";
522 phys = <&cp2_comphy1 2>;
523 phy = <&cp2_nbaset_phy2>;
535 clock-frequency = <100000>;
536 /* SLM-1521-V2 - U3 */
538 compatible = "nxp,pca9544";
539 #address-cells = <1>;
542 cp2_sfpp0_i2c: i2c@0 {
543 #address-cells = <1>;
549 #address-cells = <1>;
553 cp2_module_expander1: pca9555@21 {
554 compatible = "nxp,pca9555";
555 pinctrl-names = "default";
569 cp2_pinctrl: pinctrl {
570 compatible = "marvell,cp115-standalone-pinctrl";
571 cp2_i2c0_pins: cp2-i2c-pins-0 {
572 marvell,pins = "mpp37", "mpp38";
573 marvell,function = "i2c0";
579 PUZZLE_FAN_THERMAL(cp2, &chassis_fan_group0);