1 From be448338edda73460dc3e8c005b17edddf1c1b4f Mon Sep 17 00:00:00 2001
2 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 Date: Thu, 6 Jun 2013 18:27:16 +0200
4 Subject: [PATCH 078/203] PCI: mvebu: add support for MSI
6 This commit adds support for Message Signaled Interrupts in the
7 Marvell PCIe host controller. The work is very simple: it simply gets
8 a reference to the msi_chip associated to the PCIe controller thanks
9 to the msi-parent DT property, and stores this reference in the
10 pci_bus structure. This is enough to let the Linux PCI core use the
11 functions of msi_chip to setup and teardown MSIs.
13 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
14 Reviewed-by: Thierry Reding <thierry.reding@gmail.com>
15 Acked-by: Bjorn Helgaas <bhelgaas@google.com>
17 .../devicetree/bindings/pci/mvebu-pci.txt | 3 +++
18 drivers/pci/host/pci-mvebu.c | 26 ++++++++++++++++++++++
19 2 files changed, 29 insertions(+)
21 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
22 +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
23 @@ -14,6 +14,8 @@ Mandatory properties:
24 interfaces, and ranges describing the MBus windows needed to access
25 the memory and I/O regions of each PCIe interface.
27 +- msi-parent: Link to the hardware entity that serves as the Message
28 + Signaled Interrupt controller for this PCI controller.
29 The ranges describing the MMIO registers have the following layout:
31 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 @@ -85,6 +87,7 @@ pcie-controller {
35 bus-range = <0x00 0xff>;
36 + msi-parent = <&mpic>;
39 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
40 --- a/drivers/pci/host/pci-mvebu.c
41 +++ b/drivers/pci/host/pci-mvebu.c
43 #include <linux/clk.h>
44 #include <linux/module.h>
45 #include <linux/mbus.h>
46 +#include <linux/msi.h>
47 #include <linux/slab.h>
48 #include <linux/platform_device.h>
49 #include <linux/of_address.h>
50 @@ -103,6 +104,7 @@ struct mvebu_pcie_port;
52 struct platform_device *pdev;
53 struct mvebu_pcie_port *ports;
54 + struct msi_chip *msi;
56 struct resource realio;
58 @@ -673,6 +675,12 @@ static struct pci_bus *mvebu_pcie_scan_b
62 +void mvebu_pcie_add_bus(struct pci_bus *bus)
64 + struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
65 + bus->msi = pcie->msi;
68 resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
69 const struct resource *res,
70 resource_size_t start,
71 @@ -709,6 +717,7 @@ static void __init mvebu_pcie_enable(str
72 hw.map_irq = mvebu_pcie_map_irq;
73 hw.ops = &mvebu_pcie_ops;
74 hw.align_resource = mvebu_pcie_align_resource;
75 + hw.add_bus = mvebu_pcie_add_bus;
79 @@ -733,6 +742,21 @@ mvebu_pcie_map_registers(struct platform
80 return devm_request_and_ioremap(&pdev->dev, ®s);
83 +static void __init mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
85 + struct device_node *msi_node;
87 + msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
92 + pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
95 + pcie->msi->dev = &pcie->pdev->dev;
98 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
99 #define DT_TYPE_IO 0x1
100 #define DT_TYPE_MEM32 0x2
101 @@ -911,6 +935,8 @@ static int __init mvebu_pcie_probe(struc
105 + mvebu_pcie_msi_enable(pcie);
107 mvebu_pcie_enable(pcie);