1 From b5289e9cb18e6c254e13826e6bcfbfe95b819d77 Mon Sep 17 00:00:00 2001
2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
3 Date: Thu, 14 Nov 2013 18:25:26 -0300
4 Subject: [PATCH 140/203] mtd: nand: pxa3xx: Use a completion to signal device
7 The expected behavior of the waitfunc() NAND chip call is to wait
8 for the device to be READY (this is a standard chip line).
9 However, the current implementation does almost nothing, which opens
10 the possibility of issuing a command to a non-ready device.
12 Fix this by adding a new completion to wait for the ready event to arrive.
14 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
15 Tested-by: Daniel Mack <zonque@gmail.com>
16 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
18 drivers/mtd/nand/pxa3xx_nand.c | 38 ++++++++++++++++++++++++--------------
19 1 file changed, 24 insertions(+), 14 deletions(-)
21 --- a/drivers/mtd/nand/pxa3xx_nand.c
22 +++ b/drivers/mtd/nand/pxa3xx_nand.c
25 #include <linux/platform_data/mtd-nand-pxa3xx.h>
27 +#define NAND_DEV_READY_TIMEOUT 50
28 #define CHIP_DELAY_TIMEOUT (2 * HZ/10)
29 #define NAND_STOP_DELAY (2 * HZ/50)
30 #define PAGE_CHUNK_SIZE (2048)
31 @@ -168,7 +169,7 @@ struct pxa3xx_nand_info {
33 void __iomem *mmio_base;
34 unsigned long mmio_phys;
35 - struct completion cmd_complete;
36 + struct completion cmd_complete, dev_ready;
38 unsigned int buf_start;
39 unsigned int buf_count;
40 @@ -198,7 +199,7 @@ struct pxa3xx_nand_info {
41 int use_ecc; /* use HW ECC ? */
42 int use_dma; /* use DMA ? */
43 int use_spare; /* use spare ? */
47 unsigned int fifo_size; /* max. data size in the FIFO */
48 unsigned int data_size; /* data to be read from FIFO */
49 @@ -480,7 +481,7 @@ static void start_data_dma(struct pxa3xx
50 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
52 struct pxa3xx_nand_info *info = devid;
53 - unsigned int status, is_completed = 0;
54 + unsigned int status, is_completed = 0, is_ready = 0;
55 unsigned int ready, cmd_done;
58 @@ -516,8 +517,8 @@ static irqreturn_t pxa3xx_nand_irq(int i
63 info->state = STATE_READY;
67 if (status & NDSR_WRCMDREQ) {
68 @@ -546,6 +547,8 @@ static irqreturn_t pxa3xx_nand_irq(int i
69 nand_writel(info, NDSR, status);
71 complete(&info->cmd_complete);
73 + complete(&info->dev_ready);
77 @@ -576,7 +579,6 @@ static int prepare_command_pool(struct p
82 info->retcode = ERR_NONE;
84 info->ndcb0 = NDCB0_CSEL;
85 @@ -749,6 +751,8 @@ static void pxa3xx_nand_cmdfunc(struct m
86 exec_cmd = prepare_command_pool(info, command, column, page_addr);
88 init_completion(&info->cmd_complete);
89 + init_completion(&info->dev_ready);
90 + info->need_wait = 1;
91 pxa3xx_nand_start(info);
93 ret = wait_for_completion_timeout(&info->cmd_complete,
94 @@ -863,21 +867,27 @@ static int pxa3xx_nand_waitfunc(struct m
96 struct pxa3xx_nand_host *host = mtd->priv;
97 struct pxa3xx_nand_info *info = host->info_data;
100 + if (info->need_wait) {
101 + ret = wait_for_completion_timeout(&info->dev_ready,
102 + CHIP_DELAY_TIMEOUT);
103 + info->need_wait = 0;
105 + dev_err(&info->pdev->dev, "Ready time out!!!\n");
106 + return NAND_STATUS_FAIL;
110 /* pxa3xx_nand_send_command has waited for command complete */
111 if (this->state == FL_WRITING || this->state == FL_ERASING) {
112 if (info->retcode == ERR_NONE)
116 - * any error make it return 0x01 which will tell
117 - * the caller the erase and write fail
122 + return NAND_STATUS_FAIL;
126 + return NAND_STATUS_READY;
129 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
130 @@ -1030,7 +1040,7 @@ static int pxa3xx_nand_sensing(struct px
133 chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
134 - if (info->is_ready)
135 + if (!info->need_wait)