target/linux/mvebu/patches-3.10/0147-mtd-nand-pxa3xx-Split-prepare_command_pool-in-two-st.patch

   1 From 78c8c8dc7e27c4502504cb4daa07bc9762f54de9 Mon Sep 17 00:00:00 2001
   2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
   3 Date: Thu, 14 Nov 2013 18:25:33 -0300
   4 Subject: [PATCH 147/203] mtd: nand: pxa3xx: Split prepare_command_pool() in
   5  two stages
   6
   7 This commit splits the prepare_command_pool() function into two
   8 stages: prepare_start_command() / prepare_set_command().
   9
  10 This is a preparation patch without any functionality changes,
  11 and is meant to allow support for multiple page reading/writing
  12 operations.
  13
  14 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
  15 Tested-by: Daniel Mack <zonque@gmail.com>
  16 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
  17 ---
  18  drivers/mtd/nand/pxa3xx_nand.c | 44 ++++++++++++++++++++++++------------------
  19  1 file changed, 25 insertions(+), 19 deletions(-)
  20
  21 --- a/drivers/mtd/nand/pxa3xx_nand.c
  22 +++ b/drivers/mtd/nand/pxa3xx_nand.c
  23 @@ -607,18 +607,8 @@ static void set_command_address(struct p
  24         }
  25  }
  26
  27 -static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
  28 -               uint16_t column, int page_addr)
  29 +static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
  30  {
  31 -       int addr_cycle, exec_cmd;
  32 -       struct pxa3xx_nand_host *host;
  33 -       struct mtd_info *mtd;
  34 -
  35 -       host = info->host[info->cs];
  36 -       mtd = host->mtd;
  37 -       addr_cycle = 0;
  38 -       exec_cmd = 1;
  39 -
  40         /* reset data and oob column point to handle data */
  41         info->buf_start         = 0;
  42         info->buf_count         = 0;
  43 @@ -627,10 +617,6 @@ static int prepare_command_pool(struct p
  44         info->use_spare         = 1;
  45         info->retcode           = ERR_NONE;
  46         info->ndcb3             = 0;
  47 -       if (info->cs != 0)
  48 -               info->ndcb0 = NDCB0_CSEL;
  49 -       else
  50 -               info->ndcb0 = 0;
  51
  52         switch (command) {
  53         case NAND_CMD_READ0:
  54 @@ -642,14 +628,32 @@ static int prepare_command_pool(struct p
  55         case NAND_CMD_PARAM:
  56                 info->use_spare = 0;
  57                 break;
  58 -       case NAND_CMD_SEQIN:
  59 -               exec_cmd = 0;
  60 -               break;
  61         default:
  62                 info->ndcb1 = 0;
  63                 info->ndcb2 = 0;
  64                 break;
  65         }
  66 +}
  67 +
  68 +static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
  69 +               uint16_t column, int page_addr)
  70 +{
  71 +       int addr_cycle, exec_cmd;
  72 +       struct pxa3xx_nand_host *host;
  73 +       struct mtd_info *mtd;
  74 +
  75 +       host = info->host[info->cs];
  76 +       mtd = host->mtd;
  77 +       addr_cycle = 0;
  78 +       exec_cmd = 1;
  79 +
  80 +       if (info->cs != 0)
  81 +               info->ndcb0 = NDCB0_CSEL;
  82 +       else
  83 +               info->ndcb0 = 0;
  84 +
  85 +       if (command == NAND_CMD_SEQIN)
  86 +               exec_cmd = 0;
  87
  88         addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
  89                                     + host->col_addr_cycles);
  90 @@ -784,8 +788,10 @@ static void pxa3xx_nand_cmdfunc(struct m
  91                 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  92         }
  93
  94 +       prepare_start_command(info, command);
  95 +
  96         info->state = STATE_PREPARED;
  97 -       exec_cmd = prepare_command_pool(info, command, column, page_addr);
  98 +       exec_cmd = prepare_set_command(info, command, column, page_addr);
  99         if (exec_cmd) {
 100                 init_completion(&info->cmd_complete);
 101                 init_completion(&info->dev_ready);