target/linux/mvebu/patches-3.18/021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch

   1 From e5ee12817e9eac891c6b2a340f64d94d9abd355f Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Thu, 8 Jan 2015 18:38:09 +0100
   4 Subject: [PATCH 4/4] ARM: mvebu: Add Armada 385 Access Point Development Board
   5  support
   6
   7 The A385-AP is a board produced by Marvell that holds 3 mPCIe slot, a 16MB
   8 SPI-NOR, 3 Gigabit Ethernet ports, USB3 and NAND flash storage.
   9
  10 [gregory.clement@free-electrons.com: switch the license to the dual
  11 X11/GPL with the agreement of the author]
  12
  13 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  14 Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
  15 Signed-off-by: Andrew Lunn <andrew@lunn.ch>
  16 ---
  17  arch/arm/boot/dts/Makefile             |   1 +
  18  arch/arm/boot/dts/armada-385-db-ap.dts | 178 +++++++++++++++++++++++++++++++++
  19  2 files changed, 179 insertions(+)
  20  create mode 100644 arch/arm/boot/dts/armada-385-db-ap.dts
  21
  22 --- a/arch/arm/boot/dts/Makefile
  23 +++ b/arch/arm/boot/dts/Makefile
  24 @@ -500,6 +500,7 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \
  25         armada-375-db.dtb
  26  dtb-$(CONFIG_MACH_ARMADA_38X) += \
  27         armada-385-db.dtb \
  28 +       armada-385-db-ap.dtb \
  29         armada-385-rd.dtb
  30  dtb-$(CONFIG_MACH_ARMADA_XP) += \
  31         armada-xp-axpwifiap.dtb \
  32 --- /dev/null
  33 +++ b/arch/arm/boot/dts/armada-385-db-ap.dts
  34 @@ -0,0 +1,178 @@
  35 +/*
  36 + * Device Tree file for Marvell Armada 385 Access Point Development board
  37 + * (DB-88F6820-AP)
  38 + *
  39 + *  Copyright (C) 2014 Marvell
  40 + *
  41 + * Nadav Haklai <nadavh@marvell.com>
  42 + *
  43 + * This file is dual-licensed: you can use it either under the terms
  44 + * of the GPL or the X11 license, at your option. Note that this dual
  45 + * licensing only applies to this file, and not this project as a
  46 + * whole.
  47 + *
  48 + *  a) This file is licensed under the terms of the GNU General Public
  49 + *     License version 2.  This program is licensed "as is" without
  50 + *     any warranty of any kind, whether express or implied.
  51 + *
  52 + * Or, alternatively,
  53 + *
  54 + *  b) Permission is hereby granted, free of charge, to any person
  55 + *     obtaining a copy of this software and associated documentation
  56 + *     files (the "Software"), to deal in the Software without
  57 + *     restriction, including without limitation the rights to use,
  58 + *     copy, modify, merge, publish, distribute, sublicense, and/or
  59 + *     sell copies of the Software, and to permit persons to whom the
  60 + *     Software is furnished to do so, subject to the following
  61 + *     conditions:
  62 + *
  63 + *     The above copyright notice and this permission notice shall be
  64 + *     included in all copies or substantial portions of the Software.
  65 + *
  66 + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  67 + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  68 + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  69 + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  70 + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  71 + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  72 + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  73 + *     OTHER DEALINGS IN THE SOFTWARE.
  74 + */
  75 +
  76 +/dts-v1/;
  77 +#include "armada-385.dtsi"
  78 +
  79 +#include <dt-bindings/gpio/gpio.h>
  80 +
  81 +/ {
  82 +       model = "Marvell Armada 385 Access Point Development Board";
  83 +       compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
  84 +
  85 +       chosen {
  86 +               bootargs = "console=ttyS0,115200";
  87 +               stdout-path = &uart1;
  88 +       };
  89 +
  90 +       memory {
  91 +               device_type = "memory";
  92 +               reg = <0x00000000 0x80000000>; /* 2GB */
  93 +       };
  94 +
  95 +       soc {
  96 +               ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  97 +                         MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  98 +
  99 +               internal-regs {
 100 +                       spi1: spi@10680 {
 101 +                               pinctrl-names = "default";
 102 +                               pinctrl-0 = <&spi1_pins>;
 103 +                               status = "okay";
 104 +
 105 +                               spi-flash@0 {
 106 +                                       #address-cells = <1>;
 107 +                                       #size-cells = <1>;
 108 +                                       compatible = "st,m25p128";
 109 +                                       reg = <0>; /* Chip select 0 */
 110 +                                       spi-max-frequency = <54000000>;
 111 +                               };
 112 +                       };
 113 +
 114 +                       i2c0: i2c@11000 {
 115 +                               pinctrl-names = "default";
 116 +                               pinctrl-0 = <&i2c0_pins>;
 117 +                               status = "okay";
 118 +
 119 +                               /*
 120 +                                * This bus is wired to two EEPROM
 121 +                                * sockets, one of which holding the
 122 +                                * board ID used by the bootloader.
 123 +                                * Erasing this EEPROM's content will
 124 +                                * brick the board.
 125 +                                * Use this bus with caution.
 126 +                                */
 127 +                       };
 128 +
 129 +                       mdio@72004 {
 130 +                               pinctrl-names = "default";
 131 +                               pinctrl-0 = <&mdio_pins>;
 132 +
 133 +                               phy0: ethernet-phy@1 {
 134 +                                       reg = <1>;
 135 +                               };
 136 +
 137 +                               phy1: ethernet-phy@4 {
 138 +                                       reg = <4>;
 139 +                               };
 140 +
 141 +                               phy2: ethernet-phy@6 {
 142 +                                       reg = <6>;
 143 +                               };
 144 +                       };
 145 +
 146 +                       /* UART0 is exposed through the JP8 connector */
 147 +                       uart0: serial@12000 {
 148 +                               pinctrl-names = "default";
 149 +                               pinctrl-0 = <&uart0_pins>;
 150 +                               status = "okay";
 151 +                       };
 152 +
 153 +                       /*
 154 +                        * UART1 is exposed through a FTDI chip
 155 +                        * wired to the mini-USB connector
 156 +                        */
 157 +                       uart1: serial@12100 {
 158 +                               pinctrl-names = "default";
 159 +                               pinctrl-0 = <&uart1_pins>;
 160 +                               status = "okay";
 161 +                       };
 162 +
 163 +                       ethernet@30000 {
 164 +                               status = "okay";
 165 +                               phy = <&phy2>;
 166 +                               phy-mode = "sgmii";
 167 +                       };
 168 +
 169 +                       ethernet@34000 {
 170 +                               status = "okay";
 171 +                               phy = <&phy1>;
 172 +                               phy-mode = "sgmii";
 173 +                       };
 174 +
 175 +                       ethernet@70000 {
 176 +                               pinctrl-names = "default";
 177 +
 178 +                               /*
 179 +                                * The Reference Clock 0 is used to
 180 +                                * provide a clock to the PHY
 181 +                                */
 182 +                               pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
 183 +                               status = "okay";
 184 +                               phy = <&phy0>;
 185 +                               phy-mode = "rgmii-id";
 186 +                       };
 187 +               };
 188 +
 189 +               pcie-controller {
 190 +                       status = "okay";
 191 +
 192 +                       /*
 193 +                        * The three PCIe units are accessible through
 194 +                        * standard mini-PCIe slots on the board.
 195 +                        */
 196 +                       pcie@1,0 {
 197 +                               /* Port 0, Lane 0 */
 198 +                               status = "okay";
 199 +                       };
 200 +
 201 +                       pcie@2,0 {
 202 +                               /* Port 1, Lane 0 */
 203 +                               status = "okay";
 204 +                       };
 205 +
 206 +                       pcie@3,0 {
 207 +                               /* Port 2, Lane 0 */
 208 +                               status = "okay";
 209 +                       };
 210 +               };
 211 +       };
 212 +};