1 The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2
2 PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3
3 PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe
4 units (two 4x or quad 1x and two 4x/1x). We therefore add the
5 necessary Device Tree informations to make those PCIe interfaces
8 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 arch/arm/boot/dts/armada-xp-mv78230.dtsi | 62 +++++++++++++++++
11 arch/arm/boot/dts/armada-xp-mv78260.dtsi | 72 +++++++++++++++++++
12 arch/arm/boot/dts/armada-xp-mv78460.dtsi | 112 ++++++++++++++++++++++++++++++
13 3 files changed, 246 insertions(+)
15 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
16 +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
18 #interrupts-cells = <2>;
19 interrupts = <87>, <88>, <89>;
23 + * MV78230 has 2 PCIe units Gen2.0: One unit can be
24 + * configured as x4 or quad x1 lanes. One unit is
28 + compatible = "marvell,armada-370-xp-pcie";
29 + status = "disabled";
30 + #address-cells = <1>;
32 + ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
33 + 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
34 + 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
35 + 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
36 + 0xC000 0xd004C000 0x2000 /* port0x1_port3 */>;
38 + pcie0.0@0xd0040000 {
41 + clocks = <&gateclk 5>;
42 + marvell,pcie-port = <0>;
43 + marvell,pcie-lane = <0>;
44 + status = "disabled";
47 + pcie0.1@0xd0044000 {
48 + reg = <0x4000 0x2000>;
50 + clocks = <&gateclk 5>;
51 + marvell,pcie-port = <0>;
52 + marvell,pcie-lane = <1>;
53 + status = "disabled";
56 + pcie0.2@0xd0048000 {
57 + reg = <0x8000 0x2000>;
59 + clocks = <&gateclk 5>;
60 + marvell,pcie-port = <0>;
61 + marvell,pcie-lane = <2>;
62 + status = "disabled";
65 + pcie0.3@0xd004C000 {
66 + reg = <0xC000 0x2000>;
68 + clocks = <&gateclk 5>;
69 + marvell,pcie-port = <0>;
70 + marvell,pcie-lane = <3>;
71 + status = "disabled";
75 + reg = <0x2000 0x2000>;
77 + clocks = <&gateclk 7>;
78 + marvell,pcie-port = <2>;
79 + marvell,pcie-lane = <0>;
80 + status = "disabled";
85 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
86 +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
88 clocks = <&gateclk 1>;
93 + * MV78260 has 3 PCIe units Gen2.0: Two units can be
94 + * configured as x4 or quad x1 lanes. One unit is
98 + compatible = "marvell,armada-370-xp-pcie";
100 + #address-cells = <1>;
102 + ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
103 + 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
104 + 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
105 + 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
106 + 0xC000 0xd004C000 0x2000 /* port0x1_port3 */
107 + 0x12000 0xd0082000 0x2000 /* port3x1_port0 */>;
109 + pcie0.0@0xd0040000 {
110 + reg = <0x0 0x2000>;
112 + clocks = <&gateclk 5>;
113 + marvell,pcie-port = <0>;
114 + marvell,pcie-lane = <0>;
115 + status = "disabled";
118 + pcie0.1@0xd0044000 {
119 + reg = <0x4000 0x2000>;
121 + clocks = <&gateclk 5>;
122 + marvell,pcie-port = <0>;
123 + marvell,pcie-lane = <1>;
124 + status = "disabled";
127 + pcie0.2@0xd0048000 {
128 + reg = <0x8000 0x2000>;
130 + clocks = <&gateclk 5>;
131 + marvell,pcie-port = <0>;
132 + marvell,pcie-lane = <2>;
133 + status = "disabled";
136 + pcie0.3@0xd004C000 {
137 + reg = <0xC000 0x2000>;
139 + clocks = <&gateclk 5>;
140 + marvell,pcie-port = <0>;
141 + marvell,pcie-lane = <3>;
142 + status = "disabled";
146 + reg = <0x2000 0x2000>;
148 + clocks = <&gateclk 7>;
149 + marvell,pcie-port = <2>;
150 + marvell,pcie-lane = <0>;
151 + status = "disabled";
155 + reg = <0x12000 0x2000>;
156 + interrupts = <103>;
157 + clocks = <&gateclk 8>;
158 + marvell,pcie-port = <3>;
159 + marvell,pcie-lane = <0>;
160 + status = "disabled";
165 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
166 +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
167 @@ -111,5 +111,117 @@
168 clocks = <&gateclk 1>;
173 + * MV78460 has 4 PCIe units Gen2.0: Two units can be
174 + * configured as x4 or quad x1 lanes. Two units are
178 + compatible = "marvell,armada-370-xp-pcie";
179 + status = "disabled";
180 + #address-cells = <1>;
182 + ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
183 + 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
184 + 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
185 + 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
186 + 0xC000 0xd004C000 0x2000 /* port0x1_port3 */
187 + 0x10000 0xd0080000 0x2000 /* port1x1_port0 */
188 + 0x12000 0xd0082000 0x2000 /* port3x1_port0 */
189 + 0x14000 0xd0084000 0x2000 /* port1x1_port1 */
190 + 0x18000 0xd0088000 0x2000 /* port1x1_port2 */
191 + 0x1C000 0xd008C000 0x2000 /* port1x1_port3 */>;
193 + pcie0.0@0xd0040000 {
194 + reg = <0x0 0x2000>;
196 + clocks = <&gateclk 5>;
197 + marvell,pcie-port = <0>;
198 + marvell,pcie-lane = <0>;
199 + status = "disabled";
202 + pcie0.1@0xd0044000 {
203 + reg = <0x4000 0x2000>;
205 + clocks = <&gateclk 5>;
206 + marvell,pcie-port = <0>;
207 + marvell,pcie-lane = <1>;
208 + status = "disabled";
211 + pcie0.2@0xd0048000 {
212 + reg = <0x8000 0x2000>;
214 + clocks = <&gateclk 5>;
215 + marvell,pcie-port = <0>;
216 + marvell,pcie-lane = <2>;
217 + status = "disabled";
220 + pcie0.3@0xd004C000 {
221 + reg = <0xC000 0x2000>;
223 + clocks = <&gateclk 5>;
224 + marvell,pcie-port = <0>;
225 + marvell,pcie-lane = <3>;
226 + status = "disabled";
229 + pcie1.0@0xd0040000 {
230 + reg = <0x10000 0x2000>;
232 + clocks = <&gateclk 6>;
233 + marvell,pcie-port = <1>;
234 + marvell,pcie-lane = <0>;
235 + status = "disabled";
238 + pcie1.1@0xd0044000 {
239 + reg = <0x14000 0x2000>;
241 + clocks = <&gateclk 6>;
242 + marvell,pcie-port = <1>;
243 + marvell,pcie-lane = <1>;
244 + status = "disabled";
247 + pcie1.2@0xd0048000 {
248 + reg = <0x18000 0x2000>;
250 + clocks = <&gateclk 6>;
251 + marvell,pcie-port = <1>;
252 + marvell,pcie-lane = <2>;
253 + status = "disabled";
256 + pcie1.3@0xd004C000 {
257 + reg = <0x1C000 0x2000>;
259 + clocks = <&gateclk 6>;
260 + marvell,pcie-port = <1>;
261 + marvell,pcie-lane = <3>;
262 + status = "disabled";
266 + reg = <0x2000 0x2000>;
268 + clocks = <&gateclk 7>;
269 + marvell,pcie-port = <2>;
270 + marvell,pcie-lane = <0>;
271 + status = "disabled";
275 + reg = <0x12000 0x2000>;
276 + interrupts = <103>;
277 + clocks = <&gateclk 8>;
278 + marvell,pcie-port = <3>;
279 + marvell,pcie-lane = <0>;
280 + status = "disabled";