1 From f70b629e488cc3f2a325ac35476f4f7ae502c5d0 Mon Sep 17 00:00:00 2001
2 From: Tomasz Maciej Nowak <tmn505@gmail.com>
3 Date: Thu, 14 Jun 2018 14:24:40 +0200
4 Subject: [PATCH 1/2] PCI: aardvark: allow to specify link capability
6 Use DT of_pci_get_max_link_speed() facility to allow specifying link
7 capability. If none or unspecified value is given it falls back to gen2,
8 which is default for Armada 3700 SoC.
10 Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
12 drivers/pci/host/pci-aardvark.c | 11 +++++++++--
13 1 file changed, 9 insertions(+), 2 deletions(-)
15 --- a/drivers/pci/host/pci-aardvark.c
16 +++ b/drivers/pci/host/pci-aardvark.c
17 @@ -273,6 +273,8 @@ static void advk_pcie_set_ob_win(struct
19 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
21 + struct device *dev = &pcie->pdev->dev;
22 + struct device_node *node = dev->of_node;
26 @@ -312,10 +314,15 @@ static void advk_pcie_setup_hw(struct ad
27 PCIE_CORE_CTRL2_TD_ENABLE;
28 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
32 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
33 reg &= ~PCIE_GEN_SEL_MSK;
35 + if (of_pci_get_max_link_speed(node) == 1)
37 + else if (of_pci_get_max_link_speed(node) == 3)
41 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);