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oxnas: add support for 2nd S-ATA port to sata_oxnas driver
[openwrt/staging/jogo.git] / target / linux / oxnas / files / drivers / ata / sata_oxnas.c
1 /*
2 * sata_oxnas
3 * A driver to interface the 934 based sata core present in the ox820
4 * with libata and scsi
5 * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com>
6 * based on ox820 sata code by:
7 * Copyright (c) 2007 Oxford Semiconductor Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/ata.h>
21 #include <linux/libata.h>
22 #include <linux/of_platform.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/clk.h>
30 #include <linux/reset.h>
31
32 #include <mach/utils.h>
33
34 /* sgdma request structure */
35 struct sgdma_request {
36 volatile u32 qualifier;
37 volatile u32 control;
38 dma_addr_t src_pa;
39 dma_addr_t dst_pa;
40 } __packed __aligned(4);
41
42
43 /* Controller information */
44 enum {
45 SATA_OXNAS_MAX_PRD = 254,
46 SATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD *
47 sizeof(struct ata_bmdma_prd) +
48 sizeof(struct sgdma_request),
49 SATA_OXNAS_MAX_PORTS = 2,
50 /** The different Oxsemi SATA core version numbers */
51 SATA_OXNAS_CORE_VERSION = 0x1f3,
52 SATA_OXNAS_IRQ_FLAG = IRQF_SHARED,
53 SATA_OXNAS_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
54 ATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/),
55 SATA_OXNAS_QUEUE_DEPTH = 32,
56
57 SATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF,
58 };
59
60
61 /*
62 * SATA Port Registers
63 */
64 enum {
65 /** sata host port register offsets */
66 ORB1 = 0x00,
67 ORB2 = 0x04,
68 ORB3 = 0x08,
69 ORB4 = 0x0C,
70 ORB5 = 0x10,
71 MASTER_STATUS = 0x10,
72 FIS_CTRL = 0x18,
73 FIS_DATA = 0x1C,
74 INT_STATUS = 0x30,
75 INT_CLEAR = 0x30,
76 INT_ENABLE = 0x34,
77 INT_DISABLE = 0x38,
78 VERSION = 0x3C,
79 SATA_CONTROL = 0x5C,
80 SATA_COMMAND = 0x60,
81 HID_FEATURES = 0x64,
82 PORT_CONTROL = 0x68,
83 DRIVE_CONTROL = 0x6C,
84 /** These registers allow access to the link layer registers
85 that reside in a different clock domain to the processor bus */
86 LINK_DATA = 0x70,
87 LINK_RD_ADDR = 0x74,
88 LINK_WR_ADDR = 0x78,
89 LINK_CONTROL = 0x7C,
90 /* window control */
91 WIN1LO = 0x80,
92 WIN1HI = 0x84,
93 WIN2LO = 0x88,
94 WIN2HI = 0x8C,
95 WIN0_CONTROL = 0x90,
96 };
97
98 /** sata port register bits */
99 enum{
100 /**
101 * commands to issue in the master status to tell it to move shadow ,
102 * registers to the actual device ,
103 */
104 SATA_OPCODE_MASK = 0x00000007,
105 CMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4,
106 CMD_WRITE_TO_ORB_REGS = 0x2,
107 CMD_SYNC_ESCAPE = 0x7,
108 CMD_CORE_BUSY = (1 << 7),
109 CMD_DRIVE_SELECT_SHIFT = 12,
110 CMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT),
111
112 /** interrupt bits */
113 INT_END_OF_CMD = 1 << 0,
114 INT_LINK_SERROR = 1 << 1,
115 INT_ERROR = 1 << 2,
116 INT_LINK_IRQ = 1 << 3,
117 INT_REG_ACCESS_ERR = 1 << 7,
118 INT_BIST_FIS = 1 << 11,
119 INT_MASKABLE = INT_END_OF_CMD |
120 INT_LINK_SERROR |
121 INT_ERROR |
122 INT_LINK_IRQ |
123 INT_REG_ACCESS_ERR |
124 INT_BIST_FIS,
125 INT_WANT = INT_END_OF_CMD |
126 INT_LINK_SERROR |
127 INT_REG_ACCESS_ERR |
128 INT_ERROR,
129 INT_ERRORS = INT_LINK_SERROR |
130 INT_REG_ACCESS_ERR |
131 INT_ERROR,
132
133 /** raw interrupt bits, unmaskable, but do not generate interrupts */
134 RAW_END_OF_CMD = INT_END_OF_CMD << 16,
135 RAW_LINK_SERROR = INT_LINK_SERROR << 16,
136 RAW_ERROR = INT_ERROR << 16,
137 RAW_LINK_IRQ = INT_LINK_IRQ << 16,
138 RAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16,
139 RAW_BIST_FIS = INT_BIST_FIS << 16,
140 RAW_WANT = INT_WANT << 16,
141 RAW_ERRORS = INT_ERRORS << 16,
142
143 /**
144 * variables to write to the device control register to set the current
145 * device, ie. master or slave.
146 */
147 DR_CON_48 = 2,
148 DR_CON_28 = 0,
149
150 SATA_CTL_ERR_MASK = 0x00000016,
151
152 };
153
154 /* ATA SGDMA register offsets */
155 enum {
156 SGDMA_CONTROL = 0x0,
157 SGDMA_STATUS = 0x4,
158 SGDMA_REQUESTPTR = 0x8,
159 SGDMA_RESETS = 0xC,
160 SGDMA_CORESIZE = 0x10,
161 };
162
163 /* DMA controller register offsets */
164 enum {
165 DMA_CONTROL = 0x0,
166 DMA_CORESIZE = 0x20,
167
168 DMA_CONTROL_RESET = (1 << 12),
169 };
170
171 enum {
172 /* see DMA core docs for the values. Out means from memory (bus A) out
173 * to disk (bus B) */
174 SGDMA_REQCTL0OUT = 0x0497c03d,
175 /* burst mode disabled when no micro code used */
176 SGDMA_REQCTL0IN = 0x0493a3c1,
177 SGDMA_REQCTL1OUT = 0x0497c07d,
178 SGDMA_REQCTL1IN = 0x0497a3c5,
179 SGDMA_CONTROL_NOGO = 0x3e,
180 SGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1,
181 SGDMA_ERRORMASK = 0x3f,
182 SGDMA_BUSY = 0x80,
183
184 SGDMA_RESETS_CTRL = 1 << 0,
185 SGDMA_RESETS_ARBT = 1 << 1,
186 SGDMA_RESETS_AHB = 1 << 2,
187 SGDMA_RESETS_ALL = SGDMA_RESETS_CTRL |
188 SGDMA_RESETS_ARBT |
189 SGDMA_RESETS_AHB,
190
191 /* Final EOTs */
192 SGDMA_REQQUAL = 0x00220001,
193
194 };
195
196 /** SATA core register offsets */
197 enum {
198 DM_DBG1 = 0x000,
199 RAID_SET = 0x004,
200 DM_DBG2 = 0x008,
201 DATACOUNT_PORT0 = 0x010,
202 DATACOUNT_PORT1 = 0x014,
203 CORE_INT_STATUS = 0x030,
204 CORE_INT_CLEAR = 0x030,
205 CORE_INT_ENABLE = 0x034,
206 CORE_INT_DISABLE = 0x038,
207 CORE_REBUILD_ENABLE = 0x050,
208 CORE_FAILED_PORT_R = 0x054,
209 DEVICE_CONTROL = 0x068,
210 EXCESS = 0x06C,
211 RAID_SIZE_LOW = 0x070,
212 RAID_SIZE_HIGH = 0x074,
213 PORT_ERROR_MASK = 0x078,
214 IDLE_STATUS = 0x07C,
215 RAID_CONTROL = 0x090,
216 DATA_PLANE_CTRL = 0x0AC,
217 CORE_DATAPLANE_STAT = 0x0b8,
218 PROC_PC = 0x100,
219 CONFIG_IN = 0x3d8,
220 PROC_START = 0x3f0,
221 PROC_RESET = 0x3f4,
222 UCODE_STORE = 0x1000,
223 RAID_WP_BOT_LOW = 0x1FF0,
224 RAID_WP_BOT_HIGH = 0x1FF4,
225 RAID_WP_TOP_LOW = 0x1FF8,
226 RAID_WP_TOP_HIGH = 0x1FFC,
227 DATA_MUX_RAM0 = 0x8000,
228 DATA_MUX_RAM1 = 0xA000,
229 PORT_SIZE = 0x10000,
230 };
231
232 enum {
233 /* Sata core debug1 register bits */
234 CORE_PORT0_DATA_DIR_BIT = 20,
235 CORE_PORT1_DATA_DIR_BIT = 21,
236 CORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT,
237 CORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT,
238
239 /** sata core control register bits */
240 SCTL_CLR_ERR = 0x00003016,
241 RAID_CLR_ERR = 0x0000011e,
242
243 /* Interrupts direct from the ports */
244 NORMAL_INTS_WANTED = 0x00000303,
245
246 /* shift these left by port number */
247 COREINT_HOST = 0x00000001,
248 COREINT_END = 0x00000100,
249 CORERAW_HOST = COREINT_HOST << 16,
250 CORERAW_END = COREINT_END << 16,
251
252 /* Interrupts from the RAID controller only */
253 RAID_INTS_WANTED = 0x00008300,
254
255 /* The bits in the IDLE_STATUS that, when set indicate an idle core */
256 IDLE_CORES = (1 << 18) | (1 << 19),
257
258 /* Data plane control error-mask mask and bit, these bit in the data
259 * plane control mask out errors from the ports that prevent the SGDMA
260 * care from sending an interrupt */
261 DPC_ERROR_MASK = 0x00000300,
262 DPC_ERROR_MASK_BIT = 0x00000100,
263 /* enable jbod micro-code */
264 DPC_JBOD_UCODE = 1 << 0,
265 DPC_FIS_SWCH = 1 << 1,
266
267 /** Device Control register bits */
268 DEVICE_CONTROL_DMABT = 1 << 4,
269 DEVICE_CONTROL_ABORT = 1 << 2,
270 DEVICE_CONTROL_PAD = 1 << 3,
271 DEVICE_CONTROL_PADPAT = 1 << 16,
272 DEVICE_CONTROL_PRTRST = 1 << 8,
273 DEVICE_CONTROL_RAMRST = 1 << 12,
274 DEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28,
275
276 /** oxsemi HW raid modes */
277 OXNASSATA_NOTRAID = 0,
278 OXNASSATA_RAID0 = 1,
279 OXNASSATA_RAID1 = 2,
280 /** OX820 specific HW-RAID register values */
281 RAID_TWODISKS = 3,
282 UNKNOWN_MODE = ~0,
283
284 CONFIG_IN_RESUME = 2,
285 };
286
287 /* SATA PHY Registers */
288 enum {
289 PHY_STAT = 0x00,
290 PHY_DATA = 0x04,
291 };
292
293 enum {
294 STAT_READ_VALID = (1 << 21),
295 STAT_CR_ACK = (1 << 20),
296 STAT_CR_READ = (1 << 19),
297 STAT_CR_WRITE = (1 << 18),
298 STAT_CAP_DATA = (1 << 17),
299 STAT_CAP_ADDR = (1 << 16),
300
301 STAT_ACK_ANY = STAT_CR_ACK |
302 STAT_CR_READ |
303 STAT_CR_WRITE |
304 STAT_CAP_DATA |
305 STAT_CAP_ADDR,
306
307 CR_READ_ENABLE = (1 << 16),
308 CR_WRITE_ENABLE = (1 << 17),
309 CR_CAP_DATA = (1 << 18),
310 };
311
312 enum {
313 /* Link layer registers */
314 SERROR_IRQ_MASK = 5,
315 };
316
317 enum {
318 OXNAS_SATA_SOFTRESET = 1,
319 OXNAS_SATA_REINIT = 2,
320 };
321
322 enum {
323 OXNAS_SATA_UCODE_RAID0,
324 OXNAS_SATA_UCODE_RAID1,
325 OXNAS_SATA_UCODE_JBOD,
326 OXNAS_SATA_UCODE_NONE,
327 };
328
329 enum {
330 SATA_UNLOCKED,
331 SATA_WRITER,
332 SATA_READER,
333 SATA_REBUILD,
334 SATA_HWRAID,
335 SATA_SCSI_STACK
336 };
337
338 struct sata_oxnas_host_priv {
339 void __iomem *port_base;
340 void __iomem *dmactl_base;
341 void __iomem *sgdma_base;
342 void __iomem *core_base;
343 void __iomem *phy_base;
344 dma_addr_t dma_base;
345 void __iomem *dma_base_va;
346 size_t dma_size;
347 int irq;
348 int n_ports;
349 int current_ucode;
350 u32 port_frozen;
351 u32 port_in_eh;
352 struct clk *clk;
353 struct reset_control *rst_sata;
354 struct reset_control *rst_link;
355 struct reset_control *rst_phy;
356 };
357
358 typedef irqreturn_t (*ox820sata_isr_callback_t)(int, unsigned long, int);
359
360 static DEFINE_SPINLOCK(oxsphy_lock);
361 static DEFINE_SPINLOCK(oxsacs_lock);
362 struct sata_oxnas_port_priv {
363 void __iomem *port_base;
364 void __iomem *dmactl_base;
365 void __iomem *sgdma_base;
366 void __iomem *core_base;
367 struct sgdma_request *sgdma_request;
368 dma_addr_t sgdma_request_pa;
369 };
370
371 static u8 sata_oxnas_check_status(struct ata_port *ap);
372 static int sata_oxnas_cleanup(struct ata_host *ah);
373 static void sata_oxnas_tf_load(struct ata_port *ap,
374 const struct ata_taskfile *tf);
375 static void sata_oxnas_irq_on(struct ata_port *ap);
376 static void sata_oxnas_post_reset_init(struct ata_port *ap);
377
378 static int sata_oxnas_acquire_hw(int port_no, int may_sleep,
379 int timeout_jiffies);
380 static void sata_oxnas_release_hw(unsigned int port_no);
381
382 static int core_locked = 0;
383 static int reentrant_port_no = -1;
384 static int hw_lock_count = 0;
385 static int direct_lock_count = 0;
386 static void *locker_uid = 0;
387 static int current_locker_type = SATA_UNLOCKED;
388 static const void *HW_LOCKER_UID = (void*)0xdeadbeef;
389 static DECLARE_WAIT_QUEUE_HEAD(fast_wait_queue);
390 static DECLARE_WAIT_QUEUE_HEAD(scsi_wait_queue);
391 static ox820sata_isr_callback_t ox820sata_isr_callback = NULL;
392 static unsigned long ox820sata_isr_arg = 0;
393 static int scsi_nonblocking_attempts = 0;
394
395 /***************************************************************************
396 * ASIC access
397 ***************************************************************************/
398 static void wait_cr_ack(void __iomem *phy_base)
399 {
400 while ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f)
401 ; /* wait for an ack bit to be set */
402 }
403
404 static u16 read_cr(void __iomem *phy_base, u16 address)
405 {
406 iowrite32((u32)address, phy_base + PHY_STAT);
407 wait_cr_ack(phy_base);
408 iowrite32(CR_READ_ENABLE, phy_base + PHY_DATA);
409 wait_cr_ack(phy_base);
410 return (u16)ioread32(phy_base + PHY_STAT);
411 }
412
413 static void write_cr(void __iomem *phy_base, u16 data, u16 address)
414 {
415 iowrite32((u32)address, phy_base + PHY_STAT);
416 wait_cr_ack(phy_base);
417 iowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA);
418 wait_cr_ack(phy_base);
419 iowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA);
420 wait_cr_ack(phy_base);
421 }
422
423 #define PH_GAIN 2
424 #define FR_GAIN 3
425 #define PH_GAIN_OFFSET 6
426 #define FR_GAIN_OFFSET 8
427 #define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
428 #define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
429 #define USE_INT_SETTING (1<<5)
430
431 void workaround5458(struct ata_host *ah)
432 {
433 struct sata_oxnas_host_priv *hd = ah->private_data;
434 void __iomem *phy_base = hd->phy_base;
435 u16 rx_control;
436 unsigned i;
437
438 for (i = 0; i < 2; i++) {
439 rx_control = read_cr(phy_base, 0x201d + (i << 8));
440 rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
441 rx_control |= PH_GAIN << PH_GAIN_OFFSET;
442 rx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING;
443 write_cr(phy_base, rx_control, 0x201d+(i<<8));
444 }
445 }
446
447 /**
448 * allows access to the link layer registers
449 * @param link_reg the link layer register to access (oxsemi indexing ie
450 * 00 = static config, 04 = phy ctrl)
451 */
452 void sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val)
453 {
454 struct sata_oxnas_port_priv *port_priv = ap->private_data;
455 void __iomem *port_base = port_priv->port_base;
456 u32 patience;
457 unsigned long flags;
458
459 DPRINTK("P%d [0x%02x]->0x%08x\n", ap->port_no, link_reg, val);
460
461 spin_lock_irqsave(&oxsphy_lock, flags);
462 iowrite32(val, port_base + LINK_DATA);
463
464 /* accessed twice as a work around for a bug in the SATA abp bridge
465 * hardware (bug 6828) */
466 iowrite32(link_reg , port_base + LINK_WR_ADDR);
467 ioread32(port_base + LINK_WR_ADDR);
468
469 for (patience = 0x100000; patience > 0; --patience) {
470 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
471 break;
472 }
473 spin_unlock_irqrestore(&oxsphy_lock, flags);
474 }
475
476 static int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg,
477 u32 val)
478 {
479 sata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val);
480 return 0;
481 }
482
483 static int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg,
484 u32 val)
485 {
486 return sata_oxnas_scr_write_port(link->ap, sc_reg, val);
487 }
488
489 u32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg)
490 {
491 struct sata_oxnas_port_priv *pd = ap->private_data;
492 void __iomem *port_base = pd->port_base;
493 u32 result;
494 u32 patience;
495 unsigned long flags;
496
497 spin_lock_irqsave(&oxsphy_lock, flags);
498 /* accessed twice as a work around for a bug in the SATA abp bridge
499 * hardware (bug 6828) */
500 iowrite32(link_reg, port_base + LINK_RD_ADDR);
501 ioread32(port_base + LINK_RD_ADDR);
502
503 for (patience = 0x100000; patience > 0; --patience) {
504 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
505 break;
506 }
507 if (patience == 0)
508 DPRINTK("link read timed out for port %d\n", ap->port_no);
509
510 result = ioread32(port_base + LINK_DATA);
511 spin_unlock_irqrestore(&oxsphy_lock, flags);
512
513 return result;
514 }
515
516 static int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg,
517 u32 *val)
518 {
519 *val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4));
520 return 0;
521 }
522
523 static int sata_oxnas_scr_read(struct ata_link *link,
524 unsigned int sc_reg, u32 *val)
525 {
526 return sata_oxnas_scr_read_port(link->ap, sc_reg, val);
527 }
528
529 /**
530 * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
531 * registered, to be sure hardware is quiet. It clears and masks interrupt bits
532 * in the SATA core.
533 *
534 * @param ap hardware with the registers in
535 */
536 static void sata_oxnas_irq_clear(struct ata_port *ap)
537 {
538 struct sata_oxnas_port_priv *port_priv = ap->private_data;
539
540 /* clear pending interrupts */
541 iowrite32(~0, port_priv->port_base + INT_CLEAR);
542 iowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR);
543 }
544
545 /**
546 * qc_issue is used to make a command active, once the hardware and S/G tables
547 * have been prepared. IDE BMDMA drivers use the helper function
548 * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
549 * drivers roll their own ->qc_issue implementation, using this as the
550 * "issue new ATA command to hardware" hook.
551 * @param qc the queued command to issue
552 */
553 static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc)
554 {
555 struct sata_oxnas_port_priv *pd = qc->ap->private_data;
556 struct sata_oxnas_host_priv *hd = qc->ap->host->private_data;
557
558 void __iomem *port_base = pd->port_base;
559 void __iomem *core_base = pd->core_base;
560 int port_no = qc->ap->port_no;
561 int no_microcode = ( hd->current_ucode == UNKNOWN_MODE );
562 u32 reg;
563
564 /* check the core is idle */
565 if (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) {
566 int count = 0;
567
568 DPRINTK("core busy for a command on port %d\n",
569 qc->ap->port_no);
570 do {
571 mdelay(1);
572 if (++count > 100) {
573 DPRINTK("core busy for a command on port %d\n",
574 qc->ap->port_no);
575 /* CrazyDumpDebug(); */
576 sata_oxnas_cleanup(qc->ap->host);
577 }
578 } while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY);
579 }
580
581 /* enable passing of error signals to DMA sub-core by clearing the
582 * appropriate bit */
583 reg = ioread32(core_base + DATA_PLANE_CTRL);
584 if(no_microcode)
585 reg |= (DPC_ERROR_MASK_BIT | (DPC_ERROR_MASK_BIT << 1));
586 reg &= ~(DPC_ERROR_MASK_BIT << port_no);
587 iowrite32(reg, core_base + DATA_PLANE_CTRL);
588
589 /* Disable all interrupts for ports and RAID controller */
590 iowrite32(~0, port_base + INT_DISABLE);
591
592 /* Disable all interrupts for core */
593 iowrite32(~0, core_base + CORE_INT_DISABLE);
594 wmb();
595
596 /* Load the command settings into the orb registers */
597 sata_oxnas_tf_load(qc->ap, &qc->tf);
598
599 /* both pio and dma commands use dma */
600 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
601 /* Start the DMA */
602 iowrite32(SGDMA_CONTROL_GO, pd->sgdma_base + SGDMA_CONTROL);
603 wmb();
604 }
605
606 /* enable End of command interrupt */
607 iowrite32(INT_WANT, port_base + INT_ENABLE);
608 iowrite32(COREINT_END, core_base + CORE_INT_ENABLE);
609 wmb();
610
611 /* Start the command */
612 reg = ioread32(port_base + SATA_COMMAND);
613 reg &= ~SATA_OPCODE_MASK;
614 reg |= CMD_WRITE_TO_ORB_REGS;
615 iowrite32(reg , port_base + SATA_COMMAND);
616 wmb();
617
618 return 0;
619 }
620
621 /**
622 * Will schedule the libATA error handler on the premise that there has
623 * been a hotplug event on the port specified
624 */
625 void sata_oxnas_checkforhotplug(struct ata_port *ap)
626 {
627 DPRINTK("ENTER\n");
628
629 ata_ehi_hotplugged(&ap->link.eh_info);
630 ata_port_freeze(ap);
631 }
632
633
634 /**************************************************************************/
635 /* Locking */
636 /**************************************************************************/
637 /**
638 * The underlying function that controls access to the sata core
639 *
640 * @return non-zero indicates that you have acquired exclusive access to the
641 * sata core.
642 */
643 static int __acquire_sata_core(
644 int port_no,
645 ox820sata_isr_callback_t callback,
646 unsigned long arg,
647 int may_sleep,
648 int timeout_jiffies,
649 int hw_access,
650 void *uid,
651 int locker_type)
652 {
653 unsigned long end = jiffies + timeout_jiffies;
654 int acquired = 0;
655 unsigned long flags;
656 int timed_out = 0;
657 DEFINE_WAIT(wait);
658
659 spin_lock_irqsave(&oxsacs_lock, flags);
660
661 DPRINTK("Entered uid %p, port %d, h/w count %d, d count %d, callback %p, "
662 "hw_access %d, core_locked %d, reentrant_port_no %d, ox820sata_isr_callback %p\n",
663 uid, port_no, hw_lock_count, direct_lock_count, callback, hw_access,
664 core_locked, reentrant_port_no, ox820sata_isr_callback);
665
666 while (!timed_out) {
667 if (core_locked || (!hw_access && scsi_nonblocking_attempts)) {
668 /* Can only allow access if from SCSI/SATA stack and if
669 reentrant access is allowed and this access is to the same
670 port for which the lock is current held */
671 if (hw_access && (port_no == reentrant_port_no)) {
672 BUG_ON(!hw_lock_count);
673 ++hw_lock_count;
674
675 DPRINTK("Allow SCSI/SATA re-entrant access to uid %p port %d\n", uid, port_no);
676 acquired = 1;
677 break;
678 } else if (!hw_access) {
679 if ((locker_type == SATA_READER) && (current_locker_type == SATA_READER)) {
680 WARN(1,
681 "Already locked by reader, uid %p, locker_uid %p, port %d, "
682 "h/w count %d, d count %d, hw_access %d\n", uid, locker_uid,
683 port_no, hw_lock_count, direct_lock_count, hw_access);
684 goto check_uid;
685 }
686
687 if ((locker_type != SATA_READER) && (locker_type != SATA_WRITER)) {
688 goto wait_for_lock;
689 }
690
691 check_uid:
692 WARN(uid == locker_uid, "Attempt to lock by locker type %d "
693 "uid %p, already locked by locker type %d with "
694 "locker_uid %p, port %d, h/w count %d, d count %d, "
695 "hw_access %d\n", locker_type, uid, current_locker_type,
696 locker_uid, port_no, hw_lock_count, direct_lock_count, hw_access);
697 }
698 } else {
699 WARN(hw_lock_count || direct_lock_count, "Core unlocked but counts "
700 "non-zero: uid %p, locker_uid %p, port %d, h/w count %d, "
701 "d count %d, hw_access %d\n", uid, locker_uid, port_no,
702 hw_lock_count, direct_lock_count, hw_access);
703
704 BUG_ON(current_locker_type != SATA_UNLOCKED);
705
706 WARN(locker_uid, "Attempt to lock uid %p when locker_uid %p is "
707 "non-zero, port %d, h/w count %d, d count %d, hw_access %d\n",
708 uid, locker_uid, port_no, hw_lock_count, direct_lock_count,
709 hw_access);
710
711 if (!hw_access) {
712 /* Direct access attempting to acquire non-contented lock */
713 BUG_ON(!callback); // Must have callback for direct access
714 BUG_ON(reentrant_port_no != -1); // Sanity check lock state
715
716 ox820sata_isr_callback = callback;
717 ox820sata_isr_arg = arg;
718 ++direct_lock_count;
719
720 current_locker_type = locker_type;
721 } else {
722 /* SCSI/SATA attempting to acquire non-contented lock */
723 BUG_ON(callback); // No callbacks for SCSI/SATA access
724 BUG_ON(arg); // No callback args for SCSI/SATA access
725
726 BUG_ON(ox820sata_isr_callback); // Sanity check lock state
727 BUG_ON(ox820sata_isr_arg); // Sanity check lock state
728
729 ++hw_lock_count;
730 reentrant_port_no = port_no;
731
732 current_locker_type = SATA_SCSI_STACK;
733 }
734
735 core_locked = 1;
736 acquired = 1;
737 locker_uid = uid;
738 break;
739 }
740
741 wait_for_lock:
742 if (!may_sleep) {
743 DPRINTK("Denying for uid %p locker_type %d, hw_access %d, port %d, "
744 "current_locker_type %d as cannot sleep\n", uid, locker_type,
745 hw_access, port_no, current_locker_type);
746
747 if (hw_access) {
748 ++scsi_nonblocking_attempts;
749 }
750 break;
751 }
752
753 // Core is locked and we're allowed to sleep, so wait to be awoken when
754 // the core is unlocked
755 for (;;) {
756 prepare_to_wait(hw_access ? &scsi_wait_queue : &fast_wait_queue,
757 &wait, TASK_UNINTERRUPTIBLE);
758 if (!core_locked && !(!hw_access && scsi_nonblocking_attempts)) {
759 // We're going to use variables that will have been changed by
760 // the waker prior to clearing core_locked so we need to ensure
761 // we see changes to all those variables
762 smp_rmb();
763 break;
764 }
765 if (time_after(jiffies, end)) {
766 printk("__acquire_sata_core() uid %p failing for port %d timed out, "
767 "locker_uid %p, h/w count %d, d count %d, callback %p, hw_access %d, "
768 "core_locked %d, reentrant_port_no %d, ox820sata_isr_callback %p, "
769 "ox820sata_isr_arg %p\n", uid, port_no, locker_uid,
770 hw_lock_count, direct_lock_count, callback, hw_access,
771 core_locked, reentrant_port_no, ox820sata_isr_callback,
772 (void*)ox820sata_isr_arg);
773 timed_out = 1;
774 break;
775 }
776 spin_unlock_irqrestore(&oxsacs_lock, flags);
777 if (!schedule_timeout(4*HZ)) {
778 printk(KERN_INFO "__acquire_sata_core() uid %p, locker_uid %p, "
779 "timed-out of schedule(), checking overall timeout\n",
780 uid, locker_uid);
781 }
782 spin_lock_irqsave(&oxsacs_lock, flags);
783 }
784 finish_wait(hw_access ? &scsi_wait_queue : &fast_wait_queue, &wait);
785 }
786
787 if (hw_access && acquired) {
788 if (scsi_nonblocking_attempts) {
789 scsi_nonblocking_attempts = 0;
790 }
791
792 // Wake any other SCSI/SATA waiters so they can get reentrant access to
793 // the same port if appropriate. This is because if the SATA core is
794 // locked by fast access, or SCSI/SATA access to other port, then can
795 // have >1 SCSI/SATA waiters on the wait list so want to give reentrant
796 // accessors a chance to get access ASAP
797 if (!list_empty(&scsi_wait_queue.task_list)) {
798 wake_up(&scsi_wait_queue);
799 }
800 }
801
802 DPRINTK("Leaving uid %p with acquired = %d, port %d, callback %p\n", uid, acquired, port_no, callback);
803
804 spin_unlock_irqrestore(&oxsacs_lock, flags);
805
806 return acquired;
807 }
808
809 int sata_core_has_fast_waiters(void)
810 {
811 int has_waiters;
812 unsigned long flags;
813
814 spin_lock_irqsave(&oxsacs_lock, flags);
815 has_waiters = !list_empty(&fast_wait_queue.task_list);
816 spin_unlock_irqrestore(&oxsacs_lock, flags);
817
818 return has_waiters;
819 }
820 EXPORT_SYMBOL(sata_core_has_fast_waiters);
821
822 int sata_core_has_scsi_waiters(void)
823 {
824 int has_waiters;
825 unsigned long flags;
826
827 spin_lock_irqsave(&oxsacs_lock, flags);
828 has_waiters = scsi_nonblocking_attempts || !list_empty(&scsi_wait_queue.task_list);
829 spin_unlock_irqrestore(&oxsacs_lock, flags);
830
831 return has_waiters;
832 }
833 EXPORT_SYMBOL(sata_core_has_scsi_waiters);
834
835 /*
836 * ata_port operation to gain ownership of the SATA hardware prior to issuing
837 * a command against a SATA host. Allows any number of users of the port against
838 * which the lock was first acquired, thus enforcing that only one SATA core
839 * port may be operated on at once.
840 */
841 static int sata_oxnas_acquire_hw(
842 int port_no,
843 int may_sleep,
844 int timeout_jiffies)
845 {
846 return __acquire_sata_core(port_no, NULL, 0, may_sleep, timeout_jiffies, 1, (void*)HW_LOCKER_UID, SATA_SCSI_STACK);
847 }
848
849 /*
850 * operation to release ownership of the SATA hardware
851 */
852 static void sata_oxnas_release_hw(unsigned int port_no)
853 {
854 unsigned long flags;
855 int released = 0;
856
857 spin_lock_irqsave(&oxsacs_lock, flags);
858
859 DPRINTK("Entered port_no = %d, h/w count %d, d count %d, core locked = %d, "
860 "reentrant_port_no = %d, ox820sata_isr_callback %p\n", port_no,
861 hw_lock_count, direct_lock_count, core_locked, reentrant_port_no, ox820sata_isr_callback);
862
863 if (!core_locked) {
864 /* Nobody holds the SATA lock */
865 printk(KERN_WARNING "Nobody holds SATA lock, port_no %d\n", port_no);
866 released = 1;
867 } else if (!hw_lock_count) {
868 /* SCSI/SATA has released without holding the lock */
869 printk(KERN_WARNING "SCSI/SATA does not hold SATA lock, port_no %d\n", port_no);
870 } else {
871 /* Trap incorrect usage */
872 BUG_ON(reentrant_port_no == -1);
873 BUG_ON(port_no != reentrant_port_no);
874 BUG_ON(direct_lock_count);
875 BUG_ON(current_locker_type != SATA_SCSI_STACK);
876
877 WARN(!locker_uid || (locker_uid != HW_LOCKER_UID), "Invalid locker "
878 "uid %p, h/w count %d, d count %d, reentrant_port_no %d, "
879 "core_locked %d, ox820sata_isr_callback %p\n", locker_uid,
880 hw_lock_count, direct_lock_count, reentrant_port_no, core_locked,
881 ox820sata_isr_callback);
882
883 if (--hw_lock_count) {
884 DPRINTK("Still nested port_no %d\n", port_no);
885 } else {
886 DPRINTK("Release port_no %d\n", port_no);
887 reentrant_port_no = -1;
888 ox820sata_isr_callback = NULL;
889 current_locker_type = SATA_UNLOCKED;
890 locker_uid = 0;
891 core_locked = 0;
892 released = 1;
893 wake_up(!list_empty(&scsi_wait_queue.task_list) ? &scsi_wait_queue : &fast_wait_queue);
894 }
895 }
896
897 DPRINTK("Leaving, port_no %d, count %d\n", port_no, hw_lock_count);
898
899 spin_unlock_irqrestore(&oxsacs_lock, flags);
900
901 /* CONFIG_SATA_OX820_DIRECT_HWRAID */
902 /* if (released)
903 ox820hwraid_restart_queue();
904 } */
905 }
906
907 static inline int sata_oxnas_is_host_frozen(struct ata_host *ah)
908 {
909 struct sata_oxnas_host_priv *hd = ah->private_data;
910
911 smp_rmb();
912 return hd->port_in_eh || hd->port_frozen;
913 }
914
915
916 static inline u32 sata_oxnas_hostportbusy(struct ata_port *ap)
917 {
918 struct sata_oxnas_host_priv *hd = ap->host->private_data;
919
920 return (ioread32(hd->port_base + SATA_COMMAND) & CMD_CORE_BUSY) ||
921 (hd->n_ports > 1 &&
922 (ioread32(hd->port_base + PORT_SIZE + SATA_COMMAND) & CMD_CORE_BUSY));
923 }
924
925 static inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap)
926 {
927 struct sata_oxnas_port_priv *pd = ap->private_data;
928
929 return ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY;
930 }
931
932
933 /**
934 * Turns on the cores clock and resets it
935 */
936 static void sata_oxnas_reset_core(struct ata_host *ah)
937 {
938 struct sata_oxnas_host_priv *host_priv = ah->private_data;
939 int n;
940
941 DPRINTK("ENTER\n");
942 clk_prepare_enable(host_priv->clk);
943
944 reset_control_assert(host_priv->rst_sata);
945 reset_control_assert(host_priv->rst_link);
946 reset_control_assert(host_priv->rst_phy);
947
948 udelay(50);
949
950 /* un-reset the PHY, then Link and Controller */
951 reset_control_deassert(host_priv->rst_phy);
952 udelay(50);
953
954 reset_control_deassert(host_priv->rst_sata);
955 reset_control_deassert(host_priv->rst_link);
956 udelay(50);
957
958 workaround5458(ah);
959 /* tune for sata compatability */
960 sata_oxnas_link_write(ah->ports[0], 0x60, 0x2988);
961
962 for (n=0; n < host_priv->n_ports; n++) {
963 /* each port in turn */
964 sata_oxnas_link_write(ah->ports[n], 0x70, 0x55629);
965 }
966 udelay(50);
967 }
968
969
970 /**
971 * Called after an identify device command has worked out what kind of device
972 * is on the port
973 *
974 * @param port The port to configure
975 * @param pdev The hardware associated with controlling the port
976 */
977 static void sata_oxnas_dev_config(struct ata_device *pdev)
978 {
979 struct sata_oxnas_port_priv *pd = pdev->link->ap->private_data;
980 void __iomem *port_base = pd->port_base;
981 u32 reg;
982
983 DPRINTK("ENTER\n");
984 /* Set the bits to put the port into 28 or 48-bit node */
985 reg = ioread32(port_base + DRIVE_CONTROL);
986 reg &= ~3;
987 reg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28;
988 iowrite32(reg, port_base + DRIVE_CONTROL);
989
990 /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
991 if (pdev->flags & ATA_DFLAG_LBA48) {
992 reg = ioread32(port_base + PORT_CONTROL);
993 reg |= 2;
994 iowrite32(reg, port_base + PORT_CONTROL);
995 }
996 }
997 /**
998 * called to write a taskfile into the ORB registers
999 * @param ap hardware with the registers in
1000 * @param tf taskfile to write to the registers
1001 */
1002 static void sata_oxnas_tf_load(struct ata_port *ap,
1003 const struct ata_taskfile *tf)
1004 {
1005 u32 count = 0;
1006 u32 Orb1 = 0;
1007 u32 Orb2 = 0;
1008 u32 Orb3 = 0;
1009 u32 Orb4 = 0;
1010 u32 Command_Reg;
1011
1012 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1013 void __iomem *port_base = port_priv->port_base;
1014 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
1015
1016 /* wait a maximum of 10ms for the core to be idle */
1017 do {
1018 Command_Reg = ioread32(port_base + SATA_COMMAND);
1019 if (!(Command_Reg & CMD_CORE_BUSY))
1020 break;
1021 count++;
1022 udelay(50);
1023 } while (count < 200);
1024
1025 /* check if the ctl register has interrupts disabled or enabled and
1026 * modify the interrupt enable registers on the ata core as required */
1027 if (tf->ctl & ATA_NIEN) {
1028 /* interrupts disabled */
1029 u32 mask = (COREINT_END << ap->port_no);
1030
1031 iowrite32(mask, port_priv->core_base + CORE_INT_DISABLE);
1032 sata_oxnas_irq_clear(ap);
1033 } else {
1034 sata_oxnas_irq_on(ap);
1035 }
1036
1037 Orb2 |= (tf->command) << 24;
1038
1039 /* write 48 or 28 bit tf parameters */
1040 if (is_addr) {
1041 /* set LBA bit as it's an address */
1042 Orb1 |= (tf->device & ATA_LBA) << 24;
1043
1044 if (tf->flags & ATA_TFLAG_LBA48) {
1045 Orb1 |= ATA_LBA << 24;
1046 Orb2 |= (tf->hob_nsect) << 8;
1047 Orb3 |= (tf->hob_lbal) << 24;
1048 Orb4 |= (tf->hob_lbam) << 0;
1049 Orb4 |= (tf->hob_lbah) << 8;
1050 Orb4 |= (tf->hob_feature) << 16;
1051 } else {
1052 Orb3 |= (tf->device & 0xf) << 24;
1053 }
1054
1055 /* write 28-bit lba */
1056 Orb2 |= (tf->nsect) << 0;
1057 Orb2 |= (tf->feature) << 16;
1058 Orb3 |= (tf->lbal) << 0;
1059 Orb3 |= (tf->lbam) << 8;
1060 Orb3 |= (tf->lbah) << 16;
1061 Orb4 |= (tf->ctl) << 24;
1062 }
1063
1064 if (tf->flags & ATA_TFLAG_DEVICE)
1065 Orb1 |= (tf->device) << 24;
1066
1067 ap->last_ctl = tf->ctl;
1068
1069 /* write values to registers */
1070 iowrite32(Orb1, port_base + ORB1);
1071 iowrite32(Orb2, port_base + ORB2);
1072 iowrite32(Orb3, port_base + ORB3);
1073 iowrite32(Orb4, port_base + ORB4);
1074 }
1075
1076
1077 void sata_oxnas_set_mode(struct ata_host *ah, u32 mode, u32 force)
1078 {
1079 struct sata_oxnas_host_priv *host_priv = ah->private_data;
1080 void __iomem *core_base = host_priv->core_base;
1081
1082 unsigned int *src;
1083 void __iomem *dst;
1084 unsigned int progmicrocode = 0;
1085 unsigned int changeparameters = 0;
1086
1087 u32 previous_mode;
1088
1089 /* these micro-code programs _should_ include the version word */
1090
1091 /* JBOD */
1092 static const unsigned int jbod[] = {
1093 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
1094 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
1095 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
1096 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
1097 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
1098 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
1099 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
1100 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
1101 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
1102 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
1103 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
1104 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1105 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
1106 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1107 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
1108 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
1109 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
1110 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
1111 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
1112 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
1113 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
1114 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
1115 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
1116 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
1117 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
1118 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
1119 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
1120 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
1121 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
1122 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
1123 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
1124 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
1125 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
1126 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
1127 0x00718908, 0x0208A206, 0x00EE0005, ~0
1128 };
1129
1130 /* Bi-Modal RAID-0/1 */
1131 static const unsigned int raid[] = {
1132 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
1133 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
1134 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
1135 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
1136 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
1137 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
1138 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
1139 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
1140 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
1141 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
1142 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
1143 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
1144 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
1145 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
1146 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
1147 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
1148 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
1149 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
1150 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
1151 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
1152 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
1153 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
1154 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
1155 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
1156 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
1157 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
1158 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
1159 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
1160 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
1161 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
1162 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
1163 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
1164 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
1165 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
1166 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
1167 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
1168 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
1169 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
1170 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
1171 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
1172 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
1173 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
1174 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
1175 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
1176 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
1177 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
1178 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
1179 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
1180 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
1181 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
1182 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
1183 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
1184 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
1185 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
1186 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
1187 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
1188 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
1189 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
1190 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
1191 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
1192 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
1193 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
1194 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
1195 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
1196 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
1197 0x02400000, ~0
1198 };
1199
1200 DPRINTK("ENTER: mode:%d, force:%d\n", mode, force);
1201
1202 if (force)
1203 previous_mode = UNKNOWN_MODE;
1204 else
1205 previous_mode = host_priv->current_ucode;
1206
1207 if (mode == previous_mode)
1208 return;
1209
1210 host_priv->current_ucode = mode;
1211
1212 /* decide what needs to be done using the STD in my logbook */
1213 switch (previous_mode) {
1214 case OXNASSATA_RAID1:
1215 switch (mode) {
1216 case OXNASSATA_RAID0:
1217 changeparameters = 1;
1218 break;
1219 case OXNASSATA_NOTRAID:
1220 changeparameters = 1;
1221 progmicrocode = 1;
1222 break;
1223 }
1224 break;
1225 case OXNASSATA_RAID0:
1226 switch (mode) {
1227 case OXNASSATA_RAID1:
1228 changeparameters = 1;
1229 break;
1230 case OXNASSATA_NOTRAID:
1231 changeparameters = 1;
1232 progmicrocode = 1;
1233 break;
1234 }
1235 break;
1236 case OXNASSATA_NOTRAID:
1237 switch (mode) {
1238 case OXNASSATA_RAID0:
1239 case OXNASSATA_RAID1:
1240 changeparameters = 1;
1241 progmicrocode = 1;
1242 break;
1243 }
1244 break;
1245 case UNKNOWN_MODE:
1246 changeparameters = 1;
1247 progmicrocode = 1;
1248 break;
1249 }
1250
1251 /* no need to reprogram everything if already in the right mode */
1252 if (progmicrocode) {
1253 /* reset micro-code processor */
1254 iowrite32(1, core_base + PROC_RESET);
1255 wmb();
1256
1257 /* select micro-code */
1258 switch (mode) {
1259 case OXNASSATA_RAID1:
1260 case OXNASSATA_RAID0:
1261 VPRINTK("Loading RAID micro-code\n");
1262 src = (unsigned int *)&raid[1];
1263 break;
1264 case OXNASSATA_NOTRAID:
1265 VPRINTK("Loading JBOD micro-code\n");
1266 src = (unsigned int *)&jbod[1];
1267 break;
1268 default:
1269 BUG();
1270 break;
1271 }
1272
1273 /* load micro code */
1274 dst = core_base + UCODE_STORE;
1275 while (*src != ~0) {
1276 iowrite32(*src, dst);
1277 src++;
1278 dst += sizeof(*src);
1279 }
1280 wmb();
1281 }
1282
1283 if (changeparameters) {
1284 u32 reg;
1285 /* set other mode dependent flags */
1286 switch (mode) {
1287 case OXNASSATA_RAID1:
1288 /* clear JBOD mode */
1289 reg = ioread32(core_base + DATA_PLANE_CTRL);
1290 reg |= DPC_JBOD_UCODE;
1291 reg &= ~DPC_FIS_SWCH;
1292 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1293 wmb();
1294
1295 /* set the hardware up for RAID-1 */
1296 iowrite32(0, core_base + RAID_WP_BOT_LOW);
1297 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
1298 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
1299 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
1300 iowrite32(0, core_base + RAID_SIZE_LOW);
1301 iowrite32(0, core_base + RAID_SIZE_HIGH);
1302 wmb();
1303 break;
1304 case OXNASSATA_RAID0:
1305 /* clear JBOD mode */
1306 reg = ioread32(core_base + DATA_PLANE_CTRL);
1307 reg |= DPC_JBOD_UCODE;
1308 reg &= ~DPC_FIS_SWCH;
1309 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1310 wmb();
1311
1312 /* set the hardware up for RAID-1 */
1313 iowrite32(0, core_base + RAID_WP_BOT_LOW);
1314 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
1315 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
1316 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
1317 iowrite32(0xffffffff, core_base + RAID_SIZE_LOW);
1318 iowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH);
1319 wmb();
1320 break;
1321 case OXNASSATA_NOTRAID:
1322 /* enable jbod mode */
1323 reg = ioread32(core_base + DATA_PLANE_CTRL);
1324 reg &= ~DPC_JBOD_UCODE;
1325 reg &= ~DPC_FIS_SWCH;
1326 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1327 wmb();
1328
1329 /* start micro-code processor*/
1330 iowrite32(1, core_base + PROC_START);
1331 break;
1332 default:
1333 reg = ioread32(core_base + DATA_PLANE_CTRL);
1334 reg |= DPC_JBOD_UCODE;
1335 reg &= ~DPC_FIS_SWCH;
1336 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1337 wmb();
1338 break;
1339 }
1340 }
1341 }
1342
1343 /**
1344 * sends a sync-escape if there is a link present
1345 */
1346 static inline void sata_oxnas_send_sync_escape(struct ata_port *ap)
1347 {
1348 struct sata_oxnas_port_priv *pd = ap->private_data;
1349 u32 reg;
1350
1351 /* read the SSTATUS register and only send a sync escape if there is a
1352 * link active */
1353 if ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) {
1354 reg = ioread32(pd->port_base + SATA_COMMAND);
1355 reg &= ~SATA_OPCODE_MASK;
1356 reg |= CMD_SYNC_ESCAPE;
1357 iowrite32(reg, pd->port_base + SATA_COMMAND);
1358 }
1359 }
1360
1361 /* clears errors */
1362 static inline void sata_oxnas_clear_CS_error(struct ata_port *ap)
1363 {
1364 struct sata_oxnas_port_priv *pd = ap->private_data;
1365 u32 *base = pd->port_base;
1366 u32 reg;
1367
1368 reg = ioread32(base + SATA_CONTROL);
1369 reg &= SATA_CTL_ERR_MASK;
1370 iowrite32(reg, base + SATA_CONTROL);
1371 }
1372
1373 static inline void sata_oxnas_reset_sgdma(struct ata_port *ap)
1374 {
1375 struct sata_oxnas_port_priv *pd = ap->private_data;
1376 iowrite32(SGDMA_RESETS_CTRL, pd->sgdma_base + SGDMA_RESETS);
1377 }
1378
1379 static inline void sata_oxnas_reset_dma(struct ata_port *ap, int assert)
1380 {
1381 struct sata_oxnas_port_priv *pd = ap->private_data;
1382 u32 reg;
1383
1384 reg = ioread32(pd->dmactl_base + DMA_CONTROL);
1385 if (assert)
1386 reg |= DMA_CONTROL_RESET;
1387 else
1388 reg &= ~DMA_CONTROL_RESET;
1389
1390 iowrite32(reg, pd->dmactl_base + DMA_CONTROL);
1391 };
1392
1393 /**
1394 * Clears the error caused by the core's registers being accessed when the
1395 * core is busy.
1396 */
1397 static inline void sata_oxnas_clear_reg_access_error(struct ata_port *ap)
1398 {
1399 struct sata_oxnas_port_priv *pd = ap->private_data;
1400 u32 *base = pd->port_base;
1401 u32 reg;
1402
1403 reg = ioread32(base + INT_STATUS);
1404
1405 DPRINTK("ENTER\n");
1406 if (reg & INT_REG_ACCESS_ERR) {
1407 printk(KERN_INFO "clearing register access error on port %d\n", ap->port_no);
1408 iowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS);
1409 }
1410 reg = ioread32(base + INT_STATUS);
1411 if (reg & INT_REG_ACCESS_ERR)
1412 printk(KERN_INFO "register access error didn't clear\n");
1413 }
1414
1415 static inline void sata_oxnas_clear_sctl_error(struct ata_port *ap)
1416 {
1417 struct sata_oxnas_port_priv *pd = ap->private_data;
1418 u32 *base = pd->port_base;
1419 u32 reg;
1420
1421 reg = ioread32(base + SATA_CONTROL);
1422 reg |= SCTL_CLR_ERR;
1423 iowrite32(reg, base + SATA_CONTROL);
1424 }
1425
1426 static inline void sata_oxnas_clear_raid_error(struct ata_host *ah)
1427 {
1428 return;
1429 };
1430
1431 /**
1432 * Clean up all the state machines in the sata core.
1433 * @return post cleanup action required
1434 */
1435 static int sata_oxnas_cleanup(struct ata_host *ah)
1436 {
1437 struct sata_oxnas_host_priv *hd = ah->private_data;
1438 int actions_required = 0;
1439 int n;
1440 printk(KERN_INFO "sata_oxnas: reseting SATA core\n");
1441 /* core not recovering, reset it */
1442 mdelay(5);
1443 sata_oxnas_reset_core(ah);
1444 mdelay(5);
1445 actions_required |= OXNAS_SATA_REINIT;
1446 /* Perform any SATA core re-initialisation after reset post reset init
1447 * needs to be called for both ports as there's one reset for both
1448 * ports */
1449 for (n=0; n < hd->n_ports; n++)
1450 sata_oxnas_post_reset_init(ah->ports[n]);
1451
1452
1453 return actions_required;
1454 }
1455
1456 /**
1457 * ata_qc_new - Request an available ATA command, for queueing
1458 * @ap: Port associated with device @dev
1459 * @return non zero will refuse a new command, zero will may grant on subject
1460 * to conditions elsewhere.
1461 *
1462 */
1463 static int sata_oxnas_qc_new(struct ata_port *ap)
1464 {
1465 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1466 DPRINTK("port %d\n", ap->port_no);
1467 smp_rmb();
1468 if (hd->port_frozen || hd->port_in_eh)
1469 return 1;
1470 else
1471 return !sata_oxnas_acquire_hw(ap->port_no, 0, 0);
1472 }
1473
1474 /**
1475 * releases the lock on the port the command used
1476 */
1477 static void sata_oxnas_qc_free(struct ata_queued_cmd *qc)
1478 {
1479 DPRINTK("\n");
1480 sata_oxnas_release_hw(qc->ap->port_no);
1481 }
1482
1483 static void sata_oxnas_freeze(struct ata_port* ap)
1484 {
1485 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1486 DPRINTK("\n");
1487 hd->port_frozen |= BIT(ap->port_no);
1488 smp_wmb();
1489 }
1490
1491 static void sata_oxnas_thaw(struct ata_port* ap)
1492 {
1493 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1494 DPRINTK("\n");
1495 hd->port_frozen &= ~BIT(ap->port_no);
1496 smp_wmb();
1497 }
1498
1499 void sata_oxnas_freeze_host(struct ata_port *ap)
1500 {
1501 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1502
1503 DPRINTK("ENTER\n");
1504 hd->port_in_eh |= BIT(ap->port_no);
1505 smp_wmb();
1506 }
1507
1508 void sata_oxnas_thaw_host(struct ata_port *ap)
1509 {
1510 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1511
1512 DPRINTK("ENTER\n");
1513 hd->port_in_eh &= ~BIT(ap->port_no);
1514 smp_wmb();
1515 }
1516
1517 static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc)
1518 {
1519 DPRINTK("ENTER\n");
1520 /* If the core is busy here, make it idle */
1521 if (qc->flags & ATA_QCFLAG_FAILED)
1522 sata_oxnas_cleanup(qc->ap->host);
1523 }
1524
1525
1526 /**
1527 * turn on the interrupts
1528 *
1529 * @param ap Hardware with the registers in
1530 */
1531 static void sata_oxnas_irq_on(struct ata_port *ap)
1532 {
1533 struct sata_oxnas_port_priv *pd = ap->private_data;
1534 u32 mask = (COREINT_END << ap->port_no);
1535
1536 /* Clear pending interrupts */
1537 iowrite32(~0, pd->port_base + INT_CLEAR);
1538 iowrite32(mask, pd->core_base + CORE_INT_STATUS);
1539 wmb();
1540
1541 /* enable End of command interrupt */
1542 iowrite32(INT_WANT, pd->port_base + INT_ENABLE);
1543 iowrite32(mask, pd->core_base + CORE_INT_ENABLE);
1544 }
1545
1546
1547 /** @return true if the port has a cable connected */
1548 int sata_oxnas_check_link(struct ata_port *ap)
1549 {
1550 int reg;
1551
1552 sata_oxnas_scr_read_port(ap, SCR_STATUS, &reg);
1553 /* Check for the cable present indicated by SCR status bit-0 set */
1554 return reg & 0x1;
1555 }
1556
1557 /**
1558 * ata_std_postreset - standard postreset callback
1559 * @link: the target ata_link
1560 * @classes: classes of attached devices
1561 *
1562 * This function is invoked after a successful reset. Note that
1563 * the device might have been reset more than once using
1564 * different reset methods before postreset is invoked.
1565 *
1566 * LOCKING:
1567 * Kernel thread context (may sleep)
1568 */
1569 static void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes)
1570 {
1571 struct ata_port *ap = link->ap;
1572 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1573
1574 unsigned int dev;
1575
1576 DPRINTK("ENTER\n");
1577 ata_std_postreset(link, classes);
1578
1579 /* turn on phy error detection by removing the masks */
1580 sata_oxnas_link_write(ap->host->ports[0], 0x0c, 0x30003);
1581 if (hd->n_ports > 1)
1582 sata_oxnas_link_write(ap->host->ports[1], 0x0c, 0x30003);
1583
1584 /* bail out if no device is present */
1585 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
1586 DPRINTK("EXIT, no device\n");
1587 return;
1588 }
1589
1590 /* go through all the devices and configure them */
1591 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1592 if (ap->link.device[dev].class == ATA_DEV_ATA)
1593 sata_oxnas_dev_config(&(ap->link.device[dev]));
1594 }
1595
1596 DPRINTK("EXIT\n");
1597 }
1598
1599 /**
1600 * Called to read the hardware registers / DMA buffers, to
1601 * obtain the current set of taskfile register values.
1602 * @param ap hardware with the registers in
1603 * @param tf taskfile to read the registers into
1604 */
1605 static void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1606 {
1607 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1608 void __iomem *port_base = port_priv->port_base;
1609 /* read the orb registers */
1610 u32 Orb1 = ioread32(port_base + ORB1);
1611 u32 Orb2 = ioread32(port_base + ORB2);
1612 u32 Orb3 = ioread32(port_base + ORB3);
1613 u32 Orb4 = ioread32(port_base + ORB4);
1614
1615 /* read common 28/48 bit tf parameters */
1616 tf->device = (Orb1 >> 24);
1617 tf->nsect = (Orb2 >> 0);
1618 tf->feature = (Orb2 >> 16);
1619 tf->command = sata_oxnas_check_status(ap);
1620
1621 /* read 48 or 28 bit tf parameters */
1622 if (tf->flags & ATA_TFLAG_LBA48) {
1623 tf->hob_nsect = (Orb2 >> 8);
1624 tf->lbal = (Orb3 >> 0);
1625 tf->lbam = (Orb3 >> 8);
1626 tf->lbah = (Orb3 >> 16);
1627 tf->hob_lbal = (Orb3 >> 24);
1628 tf->hob_lbam = (Orb4 >> 0);
1629 tf->hob_lbah = (Orb4 >> 8);
1630 /* feature ext and control are write only */
1631 } else {
1632 /* read 28-bit lba */
1633 tf->lbal = (Orb3 >> 0);
1634 tf->lbam = (Orb3 >> 8);
1635 tf->lbah = (Orb3 >> 16);
1636 }
1637 }
1638
1639 /**
1640 * Read a result task-file from the sata core registers.
1641 */
1642 static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc)
1643 {
1644 /* Read the most recently received FIS from the SATA core ORB registers
1645 and convert to an ATA taskfile */
1646 sata_oxnas_tf_read(qc->ap, &qc->result_tf);
1647 return true;
1648 }
1649
1650 /**
1651 * Reads the Status ATA shadow register from hardware.
1652 *
1653 * @return The status register
1654 */
1655 static u8 sata_oxnas_check_status(struct ata_port *ap)
1656 {
1657 u32 Reg;
1658 u8 status;
1659 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1660 void __iomem *port_base = port_priv->port_base;
1661
1662 /* read byte 3 of Orb2 register */
1663 status = ioread32(port_base + ORB2) >> 24;
1664
1665 /* check for the drive going missing indicated by SCR status bits
1666 * 0-3 = 0 */
1667 sata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg);
1668
1669 if (!(Reg & 0x1)) {
1670 status |= ATA_DF;
1671 status |= ATA_ERR;
1672 }
1673
1674 return status;
1675 }
1676
1677 static inline void sata_oxnas_reset_ucode(struct ata_host *ah, int force, int no_microcode)
1678 {
1679 struct sata_oxnas_host_priv *hd = ah->private_data;
1680
1681 DPRINTK("ENTER\n");
1682 if (no_microcode) {
1683 u32 reg;
1684 sata_oxnas_set_mode(ah, UNKNOWN_MODE, force);
1685 reg = ioread32(hd->core_base + DEVICE_CONTROL);
1686 reg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE;
1687 iowrite32(reg, hd->core_base + DEVICE_CONTROL);
1688 } else {
1689 /* JBOD uCode */
1690 sata_oxnas_set_mode(ah, OXNASSATA_NOTRAID, force);
1691 /* Turn the work around off as it may have been left on by any
1692 * HW-RAID code that we've been working with */
1693 iowrite32(0x0, hd->core_base + PORT_ERROR_MASK);
1694 }
1695 }
1696
1697 /**
1698 * Prepare as much as possible for a command without involving anything that is
1699 * shared between ports.
1700 */
1701 static void sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
1702 {
1703 struct sata_oxnas_port_priv *pd;
1704 int port_no = qc->ap->port_no;
1705
1706 /* if the port's not connected, complete now with an error */
1707 if (!sata_oxnas_check_link(qc->ap)) {
1708 printk(KERN_ERR "port %d not connected completing with error\n",
1709 port_no);
1710 qc->err_mask |= AC_ERR_ATA_BUS;
1711 ata_qc_complete(qc);
1712 }
1713
1714 sata_oxnas_reset_ucode(qc->ap->host, 0, 0);
1715
1716 /* both pio and dma commands use dma */
1717 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
1718
1719 /* program the scatterlist into the prd table */
1720 ata_bmdma_qc_prep(qc);
1721
1722 /* point the sgdma controller at the dma request structure */
1723 pd = qc->ap->private_data;
1724
1725 iowrite32(pd->sgdma_request_pa,
1726 pd->sgdma_base + SGDMA_REQUESTPTR);
1727
1728 /* setup the request table */
1729 if (port_no == 0) {
1730 pd->sgdma_request->control =
1731 (qc->dma_dir == DMA_FROM_DEVICE) ?
1732 SGDMA_REQCTL0IN : SGDMA_REQCTL0OUT;
1733 } else {
1734 pd->sgdma_request->control =
1735 (qc->dma_dir == DMA_FROM_DEVICE) ?
1736 SGDMA_REQCTL1IN : SGDMA_REQCTL1OUT;
1737 }
1738 pd->sgdma_request->qualifier = SGDMA_REQQUAL;
1739 pd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma;
1740 pd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma;
1741 smp_wmb();
1742
1743 /* tell it to wait */
1744 iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);
1745 }
1746 }
1747
1748 static int sata_oxnas_port_start(struct ata_port *ap)
1749 {
1750 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1751 struct device *dev = ap->host->dev;
1752 struct sata_oxnas_port_priv *pp;
1753 void *mem;
1754 dma_addr_t mem_dma;
1755
1756 DPRINTK("ENTER\n");
1757
1758 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
1759 if (!pp)
1760 return -ENOMEM;
1761
1762 pp->port_base = host_priv->port_base +
1763 (ap->port_no ? PORT_SIZE : 0);
1764 pp->dmactl_base = host_priv->dmactl_base +
1765 (ap->port_no ? DMA_CORESIZE : 0);
1766 pp->sgdma_base = host_priv->sgdma_base +
1767 (ap->port_no ? SGDMA_CORESIZE : 0);
1768 pp->core_base = host_priv->core_base;
1769
1770 /* preallocated */
1771 if (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * host_priv->n_ports) {
1772 DPRINTK("using preallocated DMA\n");
1773 mem_dma = host_priv->dma_base +
1774 (ap->port_no ? SATA_OXNAS_DMA_SIZE : 0);
1775 mem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE);
1776 } else {
1777 mem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma,
1778 GFP_KERNEL);
1779 }
1780 if (!mem)
1781 goto err_ret;
1782
1783 pp->sgdma_request_pa = mem_dma;
1784 pp->sgdma_request = mem;
1785
1786 ap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request);
1787 ap->bmdma_prd = mem + sizeof(struct sgdma_request);
1788
1789 ap->private_data = pp;
1790
1791 sata_oxnas_post_reset_init(ap);
1792
1793 return 0;
1794
1795 err_ret:
1796 kfree(pp);
1797 return -ENOMEM;
1798
1799 }
1800
1801 static void sata_oxnas_port_stop(struct ata_port *ap)
1802 {
1803 struct device *dev = ap->host->dev;
1804 struct sata_oxnas_port_priv *pp = ap->private_data;
1805 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1806
1807 DPRINTK("ENTER\n");
1808 ap->private_data = NULL;
1809 if (host_priv->dma_size) {
1810 iounmap(pp->sgdma_request);
1811 } else {
1812 dma_free_coherent(dev, SATA_OXNAS_DMA_SIZE,
1813 pp->sgdma_request, pp->sgdma_request_pa);
1814 }
1815
1816 kfree(pp);
1817 }
1818
1819
1820 static void sata_oxnas_post_reset_init(struct ata_port *ap)
1821 {
1822 uint dev;
1823
1824 /* force to load u-code only once after reset */
1825 sata_oxnas_reset_ucode(ap->host, !ap->port_no, 0);
1826
1827 /* turn on phy error detection by removing the masks */
1828 sata_oxnas_link_write(ap, 0x0C, 0x30003);
1829
1830 /* enable hotplug event detection */
1831 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1832 sata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff);
1833 sata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16));
1834
1835 /* enable interrupts for ports */
1836 sata_oxnas_irq_on(ap);
1837
1838 /* go through all the devices and configure them */
1839 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1840 if (ap->link.device[dev].class == ATA_DEV_ATA) {
1841 sata_std_hardreset(&ap->link, NULL, jiffies + HZ);
1842 sata_oxnas_dev_config(&(ap->link.device[dev]));
1843 }
1844 }
1845
1846 /* clean up any remaining errors */
1847 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1848 VPRINTK("done\n");
1849 }
1850
1851 /**
1852 * host_stop() is called when the rmmod or hot unplug process begins. The
1853 * hook must stop all hardware interrupts, DMA engines, etc.
1854 *
1855 * @param ap hardware with the registers in
1856 */
1857 static void sata_oxnas_host_stop(struct ata_host *host_set)
1858 {
1859 DPRINTK("\n");
1860 }
1861
1862
1863 #define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
1864 static void sata_oxnas_error_handler(struct ata_port *ap)
1865 {
1866 DPRINTK("Enter port_no %d\n", ap->port_no);
1867 sata_oxnas_freeze_host(ap);
1868
1869 /* If the core is busy here, make it idle */
1870 sata_oxnas_cleanup(ap->host);
1871
1872 ata_std_error_handler(ap);
1873
1874 sata_oxnas_thaw_host(ap);
1875 }
1876
1877 static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,
1878 unsigned long deadline)
1879 {
1880 struct ata_port *ap = link->ap;
1881 struct sata_oxnas_port_priv *pd = ap->private_data;
1882 void __iomem *port_base = pd->port_base;
1883 int rc;
1884
1885 struct ata_taskfile tf;
1886 u32 Command_Reg;
1887
1888 DPRINTK("ENTER\n");
1889
1890 port_base = pd->port_base;
1891
1892 if (ata_link_offline(link)) {
1893 DPRINTK("PHY reports no device\n");
1894 *class = ATA_DEV_NONE;
1895 goto out;
1896 }
1897
1898 /* write value to register */
1899 iowrite32(0, port_base + ORB1);
1900 iowrite32(0, port_base + ORB2);
1901 iowrite32(0, port_base + ORB3);
1902 iowrite32((ap->ctl) << 24, port_base + ORB4);
1903
1904 /* command the core to send a control FIS */
1905 Command_Reg = ioread32(port_base + SATA_COMMAND);
1906 Command_Reg &= ~SATA_OPCODE_MASK;
1907 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1908 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1909 udelay(20); /* FIXME: flush */
1910
1911 /* write value to register */
1912 iowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4);
1913
1914 /* command the core to send a control FIS */
1915 Command_Reg &= ~SATA_OPCODE_MASK;
1916 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1917 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1918 udelay(20); /* FIXME: flush */
1919
1920 /* write value to register */
1921 iowrite32((ap->ctl) << 24, port_base + ORB4);
1922
1923 /* command the core to send a control FIS */
1924 Command_Reg &= ~SATA_OPCODE_MASK;
1925 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1926 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1927
1928 msleep(150);
1929
1930 rc = ata_sff_wait_ready(link, deadline);
1931
1932 /* if link is occupied, -ENODEV too is an error */
1933 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1934 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
1935 return rc;
1936 }
1937
1938 /* determine by signature whether we have ATA or ATAPI devices */
1939 sata_oxnas_tf_read(ap, &tf);
1940 *class = ata_dev_classify(&tf);
1941
1942 if (*class == ATA_DEV_UNKNOWN)
1943 *class = ATA_DEV_NONE;
1944
1945 out:
1946 DPRINTK("EXIT, class=%u\n", *class);
1947 return 0;
1948 }
1949
1950
1951 int sata_oxnas_init_controller(struct ata_host *host)
1952 {
1953 return 0;
1954 }
1955
1956 /**
1957 * Ref bug-6320
1958 *
1959 * This code is a work around for a DMA hardware bug that will repeat the
1960 * penultimate 8-bytes on some reads. This code will check that the amount
1961 * of data transferred is a multiple of 512 bytes, if not the in it will
1962 * fetch the correct data from a buffer in the SATA core and copy it into
1963 * memory.
1964 *
1965 * @param port SATA port to check and if necessary, correct.
1966 */
1967 static int sata_oxnas_bug_6320_workaround(struct ata_port *ap)
1968 {
1969 struct sata_oxnas_port_priv *pd = ap->private_data;
1970 void __iomem *core_base = pd->core_base;
1971 int is_read;
1972 int quads_transferred;
1973 int remainder;
1974 int sector_quads_remaining;
1975 int bug_present = 0;
1976
1977 /* Only want to apply fix to reads */
1978 is_read = !(ioread32(core_base + DM_DBG1) & (ap->port_no ?
1979 BIT(CORE_PORT1_DATA_DIR_BIT) :
1980 BIT(CORE_PORT0_DATA_DIR_BIT)));
1981
1982 /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
1983 transferred (datacount_port register counts quads transferred) */
1984 quads_transferred =
1985 ioread32(core_base + (ap->port_no ?
1986 DATACOUNT_PORT1 : DATACOUNT_PORT0));
1987
1988 remainder = quads_transferred & 0x7f;
1989 sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
1990
1991 if (is_read && (sector_quads_remaining == 2)) {
1992 bug_present = 1;
1993 } else if (sector_quads_remaining) {
1994 if (is_read) {
1995 printk(KERN_WARNING "SATA read fixup cannot deal with" \
1996 " %d quads remaining\n",
1997 sector_quads_remaining);
1998 } else {
1999 printk(KERN_WARNING "SATA write fixup of %d quads" \
2000 " remaining not supported\n",
2001 sector_quads_remaining);
2002 }
2003 }
2004
2005 return bug_present;
2006 }
2007
2008 /* This port done an interrupt */
2009 static void sata_oxnas_port_irq(struct ata_port *ap, int force_error)
2010 {
2011 struct ata_queued_cmd *qc;
2012 struct sata_oxnas_port_priv *pd = ap->private_data;
2013 void __iomem *port_base = pd->port_base;
2014
2015 u32 int_status;
2016 unsigned long flags = 0;
2017
2018 DPRINTK("ENTER port %d irqstatus %x\n", ap->port_no, ioread32(port_base + INT_STATUS));
2019
2020 if (ap->qc_active & (1 << ATA_TAG_INTERNAL)) {
2021 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
2022 DPRINTK("completing non-ncq cmd\n");
2023
2024 if (qc) {
2025 ata_qc_complete(qc);
2026 }
2027 return;
2028 }
2029
2030 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2031
2032
2033 /* record the port's interrupt */
2034 int_status = ioread32(port_base + INT_STATUS);
2035
2036 /* If there's no command associated with this IRQ, ignore it. We may get
2037 * spurious interrupts when cleaning-up after a failed command, ignore
2038 * these too. */
2039 if (likely(qc)) {
2040 /* get the status before any error cleanup */
2041 qc->err_mask = ac_err_mask(sata_oxnas_check_status(ap));
2042 if (force_error) {
2043 /* Pretend there has been a link error */
2044 qc->err_mask |= AC_ERR_ATA_BUS;
2045 DPRINTK(" ####force error####\n");
2046 }
2047 /* tell libata we're done */
2048 local_irq_save(flags);
2049 sata_oxnas_irq_clear(ap);
2050 local_irq_restore(flags);
2051 ata_qc_complete(qc);
2052 } else {
2053 VPRINTK("Ignoring interrupt, can't find the command tag=" \
2054 "%d %08x\n", ap->link.active_tag, ap->qc_active);
2055 }
2056
2057 /* maybe a hotplug event */
2058 if (unlikely(int_status & INT_LINK_SERROR)) {
2059 u32 serror;
2060
2061 sata_oxnas_scr_read_port(ap, SCR_ERROR, &serror);
2062 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
2063 ata_ehi_hotplugged(&ap->link.eh_info);
2064 ata_port_freeze(ap);
2065 }
2066 }
2067 }
2068
2069 /**
2070 * irq_handler is the interrupt handling routine registered with the system,
2071 * by libata.
2072 */
2073 static irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance)
2074 {
2075 struct ata_host *ah = dev_instance;
2076 struct sata_oxnas_host_priv *hd = ah->private_data;
2077 void __iomem *core_base = hd->core_base;
2078
2079 u32 int_status;
2080 irqreturn_t ret = IRQ_NONE;
2081 u32 port_no;
2082 u32 mask;
2083 int bug_present;
2084
2085 /* loop until there are no more interrupts */
2086 while ((int_status = (ioread32(core_base + CORE_INT_STATUS)) &
2087 (COREINT_END | (COREINT_END << 1)) )) {
2088
2089 /* clear any interrupt */
2090 iowrite32(int_status, core_base + CORE_INT_CLEAR);
2091
2092 /* Only need workaround_bug_6320 for single disk systems as dual
2093 * disk will use uCode which prevents this read underrun problem
2094 * from occuring.
2095 * All single disk systems will use port 0 */
2096 for (port_no = 0; port_no < hd->n_ports; ++port_no) {
2097 /* check the raw end of command interrupt to see if the
2098 * port is done */
2099 mask = (COREINT_END << port_no);
2100 if (int_status & mask) {
2101 /* this port had an interrupt, clear it */
2102 iowrite32(mask, core_base + CORE_INT_CLEAR);
2103 bug_present = ( hd->current_ucode == UNKNOWN_MODE ) ?
2104 sata_oxnas_bug_6320_workaround(
2105 ah->ports[port_no]) : 0;
2106 sata_oxnas_port_irq(ah->ports[port_no],
2107 bug_present);
2108 ret = IRQ_HANDLED;
2109 }
2110 }
2111 }
2112
2113 return ret;
2114 }
2115
2116 /*
2117 * scsi mid-layer and libata interface structures
2118 */
2119 static struct scsi_host_template sata_oxnas_sht = {
2120 ATA_NCQ_SHT("sata_oxnas"),
2121 .can_queue = SATA_OXNAS_QUEUE_DEPTH,
2122 .sg_tablesize = SATA_OXNAS_MAX_PRD,
2123 .dma_boundary = ATA_DMA_BOUNDARY,
2124 .unchecked_isa_dma = 0,
2125 };
2126
2127
2128 static struct ata_port_operations sata_oxnas_ops = {
2129 .inherits = &sata_port_ops,
2130 .qc_prep = sata_oxnas_qc_prep,
2131 .qc_issue = sata_oxnas_qc_issue,
2132 .qc_fill_rtf = sata_oxnas_qc_fill_rtf,
2133 .qc_new = sata_oxnas_qc_new,
2134 .qc_free = sata_oxnas_qc_free,
2135
2136 .scr_read = sata_oxnas_scr_read,
2137 .scr_write = sata_oxnas_scr_write,
2138
2139 .freeze = sata_oxnas_freeze,
2140 .thaw = sata_oxnas_thaw,
2141 .softreset = sata_oxnas_softreset,
2142 /* .hardreset = sata_oxnas_hardreset, */
2143 .postreset = sata_oxnas_postreset,
2144 .error_handler = sata_oxnas_error_handler,
2145 .post_internal_cmd = sata_oxnas_post_internal_cmd,
2146
2147 .port_start = sata_oxnas_port_start,
2148 .port_stop = sata_oxnas_port_stop,
2149
2150 .host_stop = sata_oxnas_host_stop,
2151 /* .pmp_attach = sata_oxnas_pmp_attach, */
2152 /* .pmp_detach = sata_oxnas_pmp_detach, */
2153 .sff_check_status = sata_oxnas_check_status,
2154 .acquire_hw = sata_oxnas_acquire_hw,
2155 };
2156
2157 static const struct ata_port_info sata_oxnas_port_info = {
2158 .flags = SATA_OXNAS_HOST_FLAGS,
2159 .pio_mask = ATA_PIO4,
2160 .udma_mask = ATA_UDMA6,
2161 .port_ops = &sata_oxnas_ops,
2162 };
2163
2164 static int sata_oxnas_probe(struct platform_device *ofdev)
2165 {
2166 int retval = -ENXIO;
2167 int n_ports = 0;
2168 void __iomem *port_base = NULL;
2169 void __iomem *dmactl_base = NULL;
2170 void __iomem *sgdma_base = NULL;
2171 void __iomem *core_base = NULL;
2172 void __iomem *phy_base = NULL;
2173 struct reset_control *rstc;
2174
2175 struct resource res = {};
2176 struct sata_oxnas_host_priv *host_priv = NULL;
2177 int irq = 0;
2178 struct ata_host *host = NULL;
2179 struct clk *clk = NULL;
2180
2181 const struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL };
2182 const struct ata_port_info *dppi[] = { &sata_oxnas_port_info, &sata_oxnas_port_info, NULL };
2183
2184 of_property_read_u32(ofdev->dev.of_node, "nr-ports", &n_ports);
2185 if (n_ports < 1 || n_ports > SATA_OXNAS_MAX_PORTS)
2186 goto error_exit_with_cleanup;
2187
2188 port_base = of_iomap(ofdev->dev.of_node, 0);
2189 if (!port_base)
2190 goto error_exit_with_cleanup;
2191
2192 dmactl_base = of_iomap(ofdev->dev.of_node, 1);
2193 if (!dmactl_base)
2194 goto error_exit_with_cleanup;
2195
2196 sgdma_base = of_iomap(ofdev->dev.of_node, 2);
2197 if (!sgdma_base)
2198 goto error_exit_with_cleanup;
2199
2200 core_base = of_iomap(ofdev->dev.of_node, 3);
2201 if (!core_base)
2202 goto error_exit_with_cleanup;
2203
2204 phy_base = of_iomap(ofdev->dev.of_node, 4);
2205 if (!phy_base)
2206 goto error_exit_with_cleanup;
2207
2208 host_priv = devm_kzalloc(&ofdev->dev,
2209 sizeof(struct sata_oxnas_host_priv),
2210 GFP_KERNEL);
2211 if (!host_priv)
2212 goto error_exit_with_cleanup;
2213
2214 host_priv->port_base = port_base;
2215 host_priv->dmactl_base = dmactl_base;
2216 host_priv->sgdma_base = sgdma_base;
2217 host_priv->core_base = core_base;
2218 host_priv->phy_base = phy_base;
2219 host_priv->n_ports = n_ports;
2220 host_priv->current_ucode = UNKNOWN_MODE;
2221
2222 if (!of_address_to_resource(ofdev->dev.of_node, 5, &res)) {
2223 host_priv->dma_base = res.start;
2224 host_priv->dma_size = resource_size(&res);
2225 }
2226
2227 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
2228 if (!irq) {
2229 dev_err(&ofdev->dev, "invalid irq from platform\n");
2230 goto error_exit_with_cleanup;
2231 }
2232 host_priv->irq = irq;
2233
2234 clk = of_clk_get(ofdev->dev.of_node, 0);
2235 if (IS_ERR(clk)) {
2236 retval = PTR_ERR(clk);
2237 clk = NULL;
2238 goto error_exit_with_cleanup;
2239 }
2240 host_priv->clk = clk;
2241
2242 rstc = devm_reset_control_get(&ofdev->dev, "sata");
2243 if (IS_ERR(rstc)) {
2244 retval = PTR_ERR(rstc);
2245 goto error_exit_with_cleanup;
2246 }
2247 host_priv->rst_sata = rstc;
2248
2249 rstc = devm_reset_control_get(&ofdev->dev, "link");
2250 if (IS_ERR(rstc)) {
2251 retval = PTR_ERR(rstc);
2252 goto error_exit_with_cleanup;
2253 }
2254 host_priv->rst_link = rstc;
2255
2256 rstc = devm_reset_control_get(&ofdev->dev, "phy");
2257 if (IS_ERR(rstc)) {
2258 retval = PTR_ERR(rstc);
2259 goto error_exit_with_cleanup;
2260 }
2261 host_priv->rst_phy = rstc;
2262
2263 /* allocate host structure */
2264 host = ata_host_alloc_pinfo(&ofdev->dev, n_ports>1 ? dppi : ppi,
2265 n_ports);
2266
2267 if (!host) {
2268 retval = -ENOMEM;
2269 goto error_exit_with_cleanup;
2270 }
2271 host->private_data = host_priv;
2272 host->iomap = port_base;
2273
2274 /* initialize host controller */
2275 retval = sata_oxnas_init_controller(host);
2276 if (retval)
2277 goto error_exit_with_cleanup;
2278
2279 /*
2280 * Now, register with libATA core, this will also initiate the
2281 * device discovery process, invoking our port_start() handler &
2282 * error_handler() to execute a dummy softreset EH session
2283 */
2284 ata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG,
2285 &sata_oxnas_sht);
2286
2287 return 0;
2288
2289 error_exit_with_cleanup:
2290 if (irq)
2291 irq_dispose_mapping(host_priv->irq);
2292 if (clk)
2293 clk_put(clk);
2294 if (host)
2295 ata_host_detach(host);
2296 if (port_base)
2297 iounmap(port_base);
2298 if (sgdma_base)
2299 iounmap(sgdma_base);
2300 if (core_base)
2301 iounmap(core_base);
2302 if (phy_base)
2303 iounmap(phy_base);
2304 return retval;
2305 }
2306
2307
2308 static int sata_oxnas_remove(struct platform_device *ofdev)
2309 {
2310 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
2311 struct sata_oxnas_host_priv *host_priv = host->private_data;
2312
2313 ata_host_detach(host);
2314
2315 irq_dispose_mapping(host_priv->irq);
2316 iounmap(host_priv->port_base);
2317 iounmap(host_priv->sgdma_base);
2318 iounmap(host_priv->core_base);
2319
2320 /* reset Controller, Link and PHY */
2321 reset_control_assert(host_priv->rst_sata);
2322 reset_control_assert(host_priv->rst_link);
2323 reset_control_assert(host_priv->rst_phy);
2324
2325 /* Disable the clock to the SATA block */
2326 clk_disable_unprepare(host_priv->clk);
2327 clk_put(host_priv->clk);
2328
2329 return 0;
2330 }
2331
2332 #ifdef CONFIG_PM
2333 static int sata_oxnas_suspend(struct platform_device *op, pm_message_t state)
2334 {
2335 struct ata_host *host = dev_get_drvdata(&op->dev);
2336
2337 return ata_host_suspend(host, state);
2338 }
2339
2340 static int sata_oxnas_resume(struct platform_device *op)
2341 {
2342 struct ata_host *host = dev_get_drvdata(&op->dev);
2343 int ret;
2344
2345 ret = sata_oxnas_init_controller(host);
2346 if (ret) {
2347 dev_err(&op->dev, "Error initializing hardware\n");
2348 return ret;
2349 }
2350 ata_host_resume(host);
2351 return 0;
2352 }
2353 #endif
2354
2355
2356
2357 static struct of_device_id oxnas_sata_match[] = {
2358 {
2359 .compatible = "plxtech,nas782x-sata",
2360 },
2361 {},
2362 };
2363
2364 MODULE_DEVICE_TABLE(of, oxnas_sata_match);
2365
2366 static struct platform_driver oxnas_sata_driver = {
2367 .driver = {
2368 .name = "oxnas-sata",
2369 .owner = THIS_MODULE,
2370 .of_match_table = oxnas_sata_match,
2371 },
2372 .probe = sata_oxnas_probe,
2373 .remove = sata_oxnas_remove,
2374 #ifdef CONFIG_PM
2375 .suspend = sata_oxnas_suspend,
2376 .resume = sata_oxnas_resume,
2377 #endif
2378 };
2379
2380 module_platform_driver(oxnas_sata_driver);
2381
2382 MODULE_LICENSE("GPL");
2383 MODULE_VERSION("1.0");
2384 MODULE_AUTHOR("Oxford Semiconductor Ltd.");
2385 MODULE_DESCRIPTION("934 SATA core controler");
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