2 * oxnas pinctrl driver based on at91 pinctrl driver
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/version.h>
14 #include <linux/of_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/irqchip/chained_irq.h>
23 #include <linux/gpio.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 /* Since we request GPIOs from ourself */
29 #include <linux/pinctrl/consumer.h>
33 #include <mach/utils.h>
35 #define MAX_NB_GPIO_PER_BANK 32
36 #define MAX_GPIO_BANKS 2
38 struct oxnas_gpio_chip
{
39 struct gpio_chip chip
;
40 struct pinctrl_gpio_range range
;
41 void __iomem
*regbase
; /* GPIOA/B virtual address */
42 void __iomem
*ctrlbase
; /* SYS/SEC_CTRL virtual address */
43 struct irq_domain
*domain
; /* associated irq domain */
46 #define to_oxnas_gpio_chip(c) container_of(c, struct oxnas_gpio_chip, chip)
48 static struct oxnas_gpio_chip
*gpio_chips
[MAX_GPIO_BANKS
];
50 static int gpio_banks
;
52 #define PULL_UP (1 << 0)
53 #define PULL_DOWN (1 << 1)
54 #define DEBOUNCE (1 << 2)
57 * struct oxnas_pmx_func - describes pinmux functions
58 * @name: the name of this specific function
59 * @groups: corresponding pin groups
60 * @ngroups: the number of groups
62 struct oxnas_pmx_func
{
85 OUTPUT_EN_CLEAR
= 0x20,
86 DEBOUNCE_ENABLE
= 0x24,
87 RE_IRQ_ENABLE
= 0x28, /* rising edge */
88 FE_IRQ_ENABLE
= 0x2C, /* falling edge */
89 RE_IRQ_PENDING
= 0x30, /* rising edge */
90 FE_IRQ_PENDING
= 0x34, /* falling edge */
93 PULL_SENSE
= 0x54, /* 1 up, 0 down */
96 DEBOUNCE_MASK
= 0x3FFF0000,
97 /* put hw debounce and soft config at same bit position*/
102 PINMUX_SECONDARY_SEL
= 0x14,
103 PINMUX_TERTIARY_SEL
= 0x8c,
104 PINMUX_QUATERNARY_SEL
= 0x94,
105 PINMUX_DEBUG_SEL
= 0x9c,
106 PINMUX_ALTERNATIVE_SEL
= 0xa4,
107 PINMUX_PULLUP_SEL
= 0xac,
111 * struct oxnas_pmx_pin - describes an pin mux
112 * @bank: the bank of the pin
113 * @pin: the pin number in the @bank
114 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
115 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
117 struct oxnas_pmx_pin
{
125 * struct oxnas_pin_group - describes an pin group
126 * @name: the name of this specific pin group
127 * @pins_conf: the mux mode for each pin in this group. The size of this
128 * array is the same as pins.
129 * @pins: an array of discrete physical pins used in this group, taken
130 * from the driver-local pin enumeration space
131 * @npins: the number of pins in this group array, i.e. the number of
132 * elements in .pins so we can iterate over that array
134 struct oxnas_pin_group
{
136 struct oxnas_pmx_pin
*pins_conf
;
141 struct oxnas_pinctrl
{
143 struct pinctrl_dev
*pctl
;
150 struct oxnas_pmx_func
*functions
;
153 struct oxnas_pin_group
*groups
;
157 static const inline struct oxnas_pin_group
*oxnas_pinctrl_find_group_by_name(
158 const struct oxnas_pinctrl
*info
,
161 const struct oxnas_pin_group
*grp
= NULL
;
164 for (i
= 0; i
< info
->ngroups
; i
++) {
165 if (strcmp(info
->groups
[i
].name
, name
))
168 grp
= &info
->groups
[i
];
169 dev_dbg(info
->dev
, "%s: %d 0:%d\n", name
, grp
->npins
,
177 static int oxnas_get_groups_count(struct pinctrl_dev
*pctldev
)
179 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
181 return info
->ngroups
;
184 static const char *oxnas_get_group_name(struct pinctrl_dev
*pctldev
,
187 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
189 return info
->groups
[selector
].name
;
192 static int oxnas_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
193 const unsigned **pins
,
196 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
198 if (selector
>= info
->ngroups
)
201 *pins
= info
->groups
[selector
].pins
;
202 *npins
= info
->groups
[selector
].npins
;
207 static void oxnas_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
210 seq_printf(s
, "%s", dev_name(pctldev
->dev
));
213 static int oxnas_dt_node_to_map(struct pinctrl_dev
*pctldev
,
214 struct device_node
*np
,
215 struct pinctrl_map
**map
, unsigned *num_maps
)
217 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
218 const struct oxnas_pin_group
*grp
;
219 struct pinctrl_map
*new_map
;
220 struct device_node
*parent
;
225 * first find the group of this node and check if we need create
226 * config maps for pins
228 grp
= oxnas_pinctrl_find_group_by_name(info
, np
->name
);
230 dev_err(info
->dev
, "unable to find group for node %s\n",
235 map_num
+= grp
->npins
;
236 new_map
= devm_kzalloc(pctldev
->dev
, sizeof(*new_map
) * map_num
,
245 parent
= of_get_parent(np
);
247 devm_kfree(pctldev
->dev
, new_map
);
250 new_map
[0].type
= PIN_MAP_TYPE_MUX_GROUP
;
251 new_map
[0].data
.mux
.function
= parent
->name
;
252 new_map
[0].data
.mux
.group
= np
->name
;
255 /* create config map */
257 for (i
= 0; i
< grp
->npins
; i
++) {
258 new_map
[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
259 new_map
[i
].data
.configs
.group_or_pin
=
260 pin_get_name(pctldev
, grp
->pins
[i
]);
261 new_map
[i
].data
.configs
.configs
= &grp
->pins_conf
[i
].conf
;
262 new_map
[i
].data
.configs
.num_configs
= 1;
265 dev_dbg(pctldev
->dev
, "maps: function %s group %s num %d\n",
266 (*map
)->data
.mux
.function
, (*map
)->data
.mux
.group
, map_num
);
271 static void oxnas_dt_free_map(struct pinctrl_dev
*pctldev
,
272 struct pinctrl_map
*map
, unsigned num_maps
)
276 static const struct pinctrl_ops oxnas_pctrl_ops
= {
277 .get_groups_count
= oxnas_get_groups_count
,
278 .get_group_name
= oxnas_get_group_name
,
279 .get_group_pins
= oxnas_get_group_pins
,
280 .pin_dbg_show
= oxnas_pin_dbg_show
,
281 .dt_node_to_map
= oxnas_dt_node_to_map
,
282 .dt_free_map
= oxnas_dt_free_map
,
285 static void __iomem
*pin_to_gpioctrl(struct oxnas_pinctrl
*info
,
288 return gpio_chips
[bank
]->regbase
;
291 static void __iomem
*pin_to_muxctrl(struct oxnas_pinctrl
*info
,
294 return gpio_chips
[bank
]->ctrlbase
;
298 static inline int pin_to_bank(unsigned pin
)
300 return pin
/ MAX_NB_GPIO_PER_BANK
;
303 static unsigned pin_to_mask(unsigned int pin
)
308 static void oxnas_mux_disable_interrupt(void __iomem
*pio
, unsigned mask
)
310 oxnas_register_clear_mask(pio
+ RE_IRQ_ENABLE
, mask
);
311 oxnas_register_clear_mask(pio
+ FE_IRQ_ENABLE
, mask
);
314 static unsigned oxnas_mux_get_pullup(void __iomem
*pio
, unsigned pin
)
316 return (readl_relaxed(pio
+ PULL_ENABLE
) & BIT(pin
)) &&
317 (readl_relaxed(pio
+ PULL_SENSE
) & BIT(pin
));
320 static void oxnas_mux_set_pullup(void __iomem
*pio
, unsigned mask
, bool on
)
323 oxnas_register_set_mask(pio
+ PULL_SENSE
, mask
);
324 oxnas_register_set_mask(pio
+ PULL_ENABLE
, mask
);
326 oxnas_register_clear_mask(pio
+ PULL_ENABLE
, mask
);
330 static bool oxnas_mux_get_pulldown(void __iomem
*pio
, unsigned pin
)
332 return (readl_relaxed(pio
+ PULL_ENABLE
) & BIT(pin
)) &&
333 (!(readl_relaxed(pio
+ PULL_SENSE
) & BIT(pin
)));
336 static void oxnas_mux_set_pulldown(void __iomem
*pio
, unsigned mask
, bool on
)
339 oxnas_register_clear_mask(pio
+ PULL_SENSE
, mask
);
340 oxnas_register_set_mask(pio
+ PULL_ENABLE
, mask
);
342 oxnas_register_clear_mask(pio
+ PULL_ENABLE
, mask
);
346 /* unfortunately debounce control are shared */
347 static bool oxnas_mux_get_debounce(void __iomem
*pio
, unsigned pin
, u32
*div
)
349 *div
= __raw_readl(pio
+ CLOCK_DIV
) & DEBOUNCE_MASK
;
350 return __raw_readl(pio
+ DEBOUNCE_ENABLE
) & BIT(pin
);
353 static void oxnas_mux_set_debounce(void __iomem
*pio
, unsigned mask
,
357 oxnas_register_value_mask(pio
+ CLOCK_DIV
, DEBOUNCE_MASK
, div
);
358 oxnas_register_set_mask(pio
+ DEBOUNCE_ENABLE
, mask
);
360 oxnas_register_clear_mask(pio
+ DEBOUNCE_ENABLE
, mask
);
365 static void oxnas_mux_set_func2(void __iomem
*cio
, unsigned mask
)
367 /* in fact, SECONDARY takes precedence, so clear others is not necessary */
368 oxnas_register_set_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
369 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
370 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
371 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
372 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
375 static void oxnas_mux_set_func3(void __iomem
*cio
, unsigned mask
)
377 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
378 oxnas_register_set_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
379 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
380 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
381 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
384 static void oxnas_mux_set_func4(void __iomem
*cio
, unsigned mask
)
386 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
387 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
388 oxnas_register_set_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
389 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
390 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
393 static void oxnas_mux_set_func_dbg(void __iomem
*cio
, unsigned mask
)
395 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
396 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
397 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
398 oxnas_register_set_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
399 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
402 static void oxnas_mux_set_func_alt(void __iomem
*cio
, unsigned mask
)
404 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
405 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
406 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
407 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
408 oxnas_register_set_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
411 static void oxnas_mux_set_gpio(void __iomem
*cio
, unsigned mask
)
413 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
414 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
415 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
416 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
417 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
420 static enum oxnas_mux
oxnas_mux_get_func(void __iomem
*cio
, unsigned mask
)
422 if (readl_relaxed(cio
+ PINMUX_SECONDARY_SEL
) & mask
)
423 return OXNAS_PINMUX_FUNC2
;
424 if (readl_relaxed(cio
+ PINMUX_TERTIARY_SEL
) & mask
)
425 return OXNAS_PINMUX_FUNC3
;
426 if (readl_relaxed(cio
+ PINMUX_QUATERNARY_SEL
) & mask
)
427 return OXNAS_PINMUX_FUNC4
;
428 if (readl_relaxed(cio
+ PINMUX_DEBUG_SEL
) & mask
)
429 return OXNAS_PINMUX_DEBUG
;
430 if (readl_relaxed(cio
+ PINMUX_ALTERNATIVE_SEL
) & mask
)
431 return OXNAS_PINMUX_ALT
;
432 return OXNAS_PINMUX_GPIO
;
436 static void oxnas_pin_dbg(const struct device
*dev
,
437 const struct oxnas_pmx_pin
*pin
)
441 "MF_%c%d configured as periph%c with conf = 0x%lu\n",
442 pin
->bank
+ 'A', pin
->pin
, pin
->mux
- 1 + 'A',
445 dev_dbg(dev
, "MF_%c%d configured as gpio with conf = 0x%lu\n",
446 pin
->bank
+ 'A', pin
->pin
, pin
->conf
);
450 static int pin_check_config(struct oxnas_pinctrl
*info
, const char *name
,
451 int index
, const struct oxnas_pmx_pin
*pin
)
455 /* check if it's a valid config */
456 if (pin
->bank
>= info
->nbanks
) {
457 dev_err(info
->dev
, "%s: pin conf %d bank_id %d >= nbanks %d\n",
458 name
, index
, pin
->bank
, info
->nbanks
);
462 if (pin
->pin
>= MAX_NB_GPIO_PER_BANK
) {
463 dev_err(info
->dev
, "%s: pin conf %d pin_bank_id %d >= %d\n",
464 name
, index
, pin
->pin
, MAX_NB_GPIO_PER_BANK
);
467 /* gpio always allowed */
473 if (mux
>= info
->nmux
) {
474 dev_err(info
->dev
, "%s: pin conf %d mux_id %d >= nmux %d\n",
475 name
, index
, mux
, info
->nmux
);
479 if (!(info
->mux_mask
[pin
->bank
* info
->nmux
+ mux
] & 1 << pin
->pin
)) {
480 dev_err(info
->dev
, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n",
481 name
, index
, mux
, pin
->bank
+ 'A', pin
->pin
);
488 static void oxnas_mux_gpio_enable(void __iomem
*cio
, void __iomem
*pio
,
489 unsigned mask
, bool input
)
491 oxnas_mux_set_gpio(cio
, mask
);
493 writel_relaxed(mask
, pio
+ OUTPUT_EN_CLEAR
);
495 writel_relaxed(mask
, pio
+ OUTPUT_EN_SET
);
498 static void oxnas_mux_gpio_disable(void __iomem
*cio
, void __iomem
*pio
,
501 /* when switch to other function, gpio is disabled automatically */
505 static int oxnas_pmx_set_mux(struct pinctrl_dev
*pctldev
, unsigned selector
,
508 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
509 const struct oxnas_pmx_pin
*pins_conf
= info
->groups
[group
].pins_conf
;
510 const struct oxnas_pmx_pin
*pin
;
511 uint32_t npins
= info
->groups
[group
].npins
;
517 dev_dbg(info
->dev
, "enable function %s group %s\n",
518 info
->functions
[selector
].name
, info
->groups
[group
].name
);
520 /* first check that all the pins of the group are valid with a valid
522 for (i
= 0; i
< npins
; i
++) {
524 ret
= pin_check_config(info
, info
->groups
[group
].name
, i
, pin
);
529 for (i
= 0; i
< npins
; i
++) {
531 oxnas_pin_dbg(info
->dev
, pin
);
533 pio
= pin_to_gpioctrl(info
, pin
->bank
);
534 cio
= pin_to_muxctrl(info
, pin
->bank
);
536 mask
= pin_to_mask(pin
->pin
);
537 oxnas_mux_disable_interrupt(pio
, mask
);
540 case OXNAS_PINMUX_GPIO
:
541 oxnas_mux_gpio_enable(cio
, pio
, mask
, 1);
543 case OXNAS_PINMUX_FUNC2
:
544 oxnas_mux_set_func2(cio
, mask
);
546 case OXNAS_PINMUX_FUNC3
:
547 oxnas_mux_set_func3(cio
, mask
);
549 case OXNAS_PINMUX_FUNC4
:
550 oxnas_mux_set_func4(cio
, mask
);
552 case OXNAS_PINMUX_DEBUG
:
553 oxnas_mux_set_func_dbg(cio
, mask
);
555 case OXNAS_PINMUX_ALT
:
556 oxnas_mux_set_func_alt(cio
, mask
);
560 oxnas_mux_gpio_disable(cio
, pio
, mask
);
566 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
567 static void oxnas_pmx_disable(struct pinctrl_dev
*pctldev
, unsigned selector
,
570 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
571 const struct oxnas_pmx_pin
*pins_conf
= info
->groups
[group
].pins_conf
;
572 const struct oxnas_pmx_pin
*pin
;
573 uint32_t npins
= info
->groups
[group
].npins
;
579 for (i
= 0; i
< npins
; i
++) {
581 oxnas_pin_dbg(info
->dev
, pin
);
582 pio
= pin_to_gpioctrl(info
, pin
->bank
);
583 cio
= pin_to_muxctrl(info
, pin
->bank
);
584 mask
= pin_to_mask(pin
->pin
);
585 oxnas_mux_gpio_enable(cio
, pio
, mask
, 1);
590 static int oxnas_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
592 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
594 return info
->nfunctions
;
597 static const char *oxnas_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
600 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
602 return info
->functions
[selector
].name
;
605 static int oxnas_pmx_get_groups(struct pinctrl_dev
*pctldev
, unsigned selector
,
606 const char * const **groups
,
607 unsigned * const num_groups
)
609 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
611 *groups
= info
->functions
[selector
].groups
;
612 *num_groups
= info
->functions
[selector
].ngroups
;
617 static int oxnas_gpio_request_enable(struct pinctrl_dev
*pctldev
,
618 struct pinctrl_gpio_range
*range
,
621 struct oxnas_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
622 struct oxnas_gpio_chip
*oxnas_chip
;
623 struct gpio_chip
*chip
;
627 dev_err(npct
->dev
, "invalid range\n");
631 dev_err(npct
->dev
, "missing GPIO chip in range\n");
635 oxnas_chip
= container_of(chip
, struct oxnas_gpio_chip
, chip
);
637 dev_dbg(npct
->dev
, "enable pin %u as GPIO\n", offset
);
639 mask
= 1 << (offset
- chip
->base
);
641 dev_dbg(npct
->dev
, "enable pin %u as MF_%c%d 0x%x\n",
642 offset
, 'A' + range
->id
, offset
- chip
->base
, mask
);
644 oxnas_mux_set_gpio(oxnas_chip
->ctrlbase
, mask
);
649 static void oxnas_gpio_disable_free(struct pinctrl_dev
*pctldev
,
650 struct pinctrl_gpio_range
*range
,
653 struct oxnas_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
655 dev_dbg(npct
->dev
, "disable pin %u as GPIO\n", offset
);
656 /* Set the pin to some default state, GPIO is usually default */
659 static const struct pinmux_ops oxnas_pmx_ops
= {
660 .get_functions_count
= oxnas_pmx_get_funcs_count
,
661 .get_function_name
= oxnas_pmx_get_func_name
,
662 .get_function_groups
= oxnas_pmx_get_groups
,
663 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
664 .set_mux
= oxnas_pmx_set_mux
,
666 .enable
= oxnas_pmx_set_mux
,
668 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
669 .disable
= oxnas_pmx_disable
,
671 .gpio_request_enable
= oxnas_gpio_request_enable
,
672 .gpio_disable_free
= oxnas_gpio_disable_free
,
675 static int oxnas_pinconf_get(struct pinctrl_dev
*pctldev
,
676 unsigned pin_id
, unsigned long *config
)
678 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
683 dev_dbg(info
->dev
, "%s:%d, pin_id=%d, config=0x%lx", __func__
,
684 __LINE__
, pin_id
, *config
);
685 pio
= pin_to_gpioctrl(info
, pin_to_bank(pin_id
));
686 pin
= pin_id
% MAX_NB_GPIO_PER_BANK
;
688 if (oxnas_mux_get_pullup(pio
, pin
))
691 if (oxnas_mux_get_pulldown(pio
, pin
))
692 *config
|= PULL_DOWN
;
694 if (oxnas_mux_get_debounce(pio
, pin
, &div
))
695 *config
|= DEBOUNCE
| div
;
699 static int oxnas_pinconf_set(struct pinctrl_dev
*pctldev
,
700 unsigned pin_id
, unsigned long *configs
,
701 unsigned num_configs
)
703 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
707 unsigned long config
;
709 pio
= pin_to_gpioctrl(info
, pin_to_bank(pin_id
));
710 mask
= pin_to_mask(pin_id
% MAX_NB_GPIO_PER_BANK
);
712 for (i
= 0; i
< num_configs
; i
++) {
716 "%s:%d, pin_id=%d, config=0x%lx",
717 __func__
, __LINE__
, pin_id
, config
);
719 if ((config
& PULL_UP
) && (config
& PULL_DOWN
))
722 oxnas_mux_set_pullup(pio
, mask
, config
& PULL_UP
);
723 oxnas_mux_set_pulldown(pio
, mask
, config
& PULL_DOWN
);
724 oxnas_mux_set_debounce(pio
, mask
, config
& DEBOUNCE
,
725 config
& DEBOUNCE_MASK
);
727 } /* for each config */
732 static void oxnas_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
733 struct seq_file
*s
, unsigned pin_id
)
738 static void oxnas_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
739 struct seq_file
*s
, unsigned group
)
743 static const struct pinconf_ops oxnas_pinconf_ops
= {
744 .pin_config_get
= oxnas_pinconf_get
,
745 .pin_config_set
= oxnas_pinconf_set
,
746 .pin_config_dbg_show
= oxnas_pinconf_dbg_show
,
747 .pin_config_group_dbg_show
= oxnas_pinconf_group_dbg_show
,
750 static struct pinctrl_desc oxnas_pinctrl_desc
= {
751 .pctlops
= &oxnas_pctrl_ops
,
752 .pmxops
= &oxnas_pmx_ops
,
753 .confops
= &oxnas_pinconf_ops
,
754 .owner
= THIS_MODULE
,
757 static const char *gpio_compat
= "plxtech,nas782x-gpio";
759 static void oxnas_pinctrl_child_count(struct oxnas_pinctrl
*info
,
760 struct device_node
*np
)
762 struct device_node
*child
;
764 for_each_child_of_node(np
, child
) {
765 if (of_device_is_compatible(child
, gpio_compat
)) {
769 info
->ngroups
+= of_get_child_count(child
);
774 static int oxnas_pinctrl_mux_mask(struct oxnas_pinctrl
*info
,
775 struct device_node
*np
)
781 list
= of_get_property(np
, "plxtech,mux-mask", &size
);
783 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
787 size
/= sizeof(*list
);
788 if (!size
|| size
% info
->nbanks
) {
789 dev_err(info
->dev
, "wrong mux mask array should be by %d\n",
793 info
->nmux
= size
/ info
->nbanks
;
795 info
->mux_mask
= devm_kzalloc(info
->dev
, sizeof(u32
) * size
, GFP_KERNEL
);
796 if (!info
->mux_mask
) {
797 dev_err(info
->dev
, "could not alloc mux_mask\n");
801 ret
= of_property_read_u32_array(np
, "plxtech,mux-mask",
802 info
->mux_mask
, size
);
804 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
808 static int oxnas_pinctrl_parse_groups(struct device_node
*np
,
809 struct oxnas_pin_group
*grp
,
810 struct oxnas_pinctrl
*info
, u32 index
)
812 struct oxnas_pmx_pin
*pin
;
817 dev_dbg(info
->dev
, "group(%d): %s\n", index
, np
->name
);
819 /* Initialise group */
820 grp
->name
= np
->name
;
823 * the binding format is plxtech,pins = <bank pin mux CONFIG ...>,
824 * do sanity check and calculate pins number
826 list
= of_get_property(np
, "plxtech,pins", &size
);
827 /* we do not check return since it's safe node passed down */
828 size
/= sizeof(*list
);
829 if (!size
|| size
% 4) {
830 dev_err(info
->dev
, "wrong pins number or pins and configs"
831 " should be divisible by 4\n");
835 grp
->npins
= size
/ 4;
836 pin
= grp
->pins_conf
= devm_kzalloc(info
->dev
,
837 grp
->npins
* sizeof(struct oxnas_pmx_pin
),
839 grp
->pins
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(unsigned int),
841 if (!grp
->pins_conf
|| !grp
->pins
)
844 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
845 pin
->bank
= be32_to_cpu(*list
++);
846 pin
->pin
= be32_to_cpu(*list
++);
847 grp
->pins
[j
] = pin
->bank
* MAX_NB_GPIO_PER_BANK
+ pin
->pin
;
848 pin
->mux
= be32_to_cpu(*list
++);
849 pin
->conf
= be32_to_cpu(*list
++);
851 oxnas_pin_dbg(info
->dev
, pin
);
858 static int oxnas_pinctrl_parse_functions(struct device_node
*np
,
859 struct oxnas_pinctrl
*info
, u32 index
)
861 struct device_node
*child
;
862 struct oxnas_pmx_func
*func
;
863 struct oxnas_pin_group
*grp
;
865 static u32 grp_index
;
868 dev_dbg(info
->dev
, "parse function(%d): %s\n", index
, np
->name
);
870 func
= &info
->functions
[index
];
872 /* Initialise function */
873 func
->name
= np
->name
;
874 func
->ngroups
= of_get_child_count(np
);
875 if (func
->ngroups
<= 0) {
876 dev_err(info
->dev
, "no groups defined\n");
879 func
->groups
= devm_kzalloc(info
->dev
,
880 func
->ngroups
* sizeof(char *), GFP_KERNEL
);
884 for_each_child_of_node(np
, child
) {
885 func
->groups
[i
] = child
->name
;
886 grp
= &info
->groups
[grp_index
++];
887 ret
= oxnas_pinctrl_parse_groups(child
, grp
, info
, i
++);
895 static struct of_device_id oxnas_pinctrl_of_match
[] = {
896 { .compatible
= "plxtech,nas782x-pinctrl"},
900 static int oxnas_pinctrl_probe_dt(struct platform_device
*pdev
,
901 struct oxnas_pinctrl
*info
)
906 struct device_node
*np
= pdev
->dev
.of_node
;
907 struct device_node
*child
;
912 info
->dev
= &pdev
->dev
;
914 oxnas_pinctrl_child_count(info
, np
);
916 if (info
->nbanks
< 1) {
917 dev_err(&pdev
->dev
, "you need to specify atleast one gpio-controller\n");
921 ret
= oxnas_pinctrl_mux_mask(info
, np
);
925 dev_dbg(&pdev
->dev
, "nmux = %d\n", info
->nmux
);
927 dev_dbg(&pdev
->dev
, "mux-mask\n");
928 tmp
= info
->mux_mask
;
929 for (i
= 0; i
< info
->nbanks
; i
++)
930 for (j
= 0; j
< info
->nmux
; j
++, tmp
++)
931 dev_dbg(&pdev
->dev
, "%d:%d\t0x%x\n", i
, j
, tmp
[0]);
933 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
934 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
935 info
->functions
= devm_kzalloc(&pdev
->dev
, info
->nfunctions
*
936 sizeof(struct oxnas_pmx_func
),
938 if (!info
->functions
)
941 info
->groups
= devm_kzalloc(&pdev
->dev
, info
->ngroups
*
942 sizeof(struct oxnas_pin_group
),
947 dev_dbg(&pdev
->dev
, "nbanks = %d\n", info
->nbanks
);
948 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
949 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
953 for_each_child_of_node(np
, child
) {
954 if (of_device_is_compatible(child
, gpio_compat
))
956 ret
= oxnas_pinctrl_parse_functions(child
, info
, i
++);
958 dev_err(&pdev
->dev
, "failed to parse function\n");
966 static int oxnas_pinctrl_probe(struct platform_device
*pdev
)
968 struct oxnas_pinctrl
*info
;
969 struct pinctrl_pin_desc
*pdesc
;
972 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
976 ret
= oxnas_pinctrl_probe_dt(pdev
, info
);
981 * We need all the GPIO drivers to probe FIRST, or we will not be able
982 * to obtain references to the struct gpio_chip * for them, and we
983 * need this to proceed.
985 for (i
= 0; i
< info
->nbanks
; i
++) {
986 if (!gpio_chips
[i
]) {
988 "GPIO chip %d not registered yet\n", i
);
989 devm_kfree(&pdev
->dev
, info
);
990 return -EPROBE_DEFER
;
994 oxnas_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
995 oxnas_pinctrl_desc
.npins
= info
->nbanks
* MAX_NB_GPIO_PER_BANK
;
996 oxnas_pinctrl_desc
.pins
= pdesc
=
997 devm_kzalloc(&pdev
->dev
, sizeof(*pdesc
) *
998 oxnas_pinctrl_desc
.npins
, GFP_KERNEL
);
1000 if (!oxnas_pinctrl_desc
.pins
)
1003 for (i
= 0 , k
= 0; i
< info
->nbanks
; i
++) {
1004 for (j
= 0; j
< MAX_NB_GPIO_PER_BANK
; j
++, k
++) {
1006 pdesc
->name
= kasprintf(GFP_KERNEL
, "MF_%c%d", i
+ 'A',
1012 platform_set_drvdata(pdev
, info
);
1013 info
->pctl
= pinctrl_register(&oxnas_pinctrl_desc
, &pdev
->dev
, info
);
1016 dev_err(&pdev
->dev
, "could not register OX820 pinctrl driver\n");
1021 /* We will handle a range of GPIO pins */
1022 for (i
= 0; i
< info
->nbanks
; i
++)
1023 pinctrl_add_gpio_range(info
->pctl
, &gpio_chips
[i
]->range
);
1025 dev_info(&pdev
->dev
, "initialized OX820 pinctrl driver\n");
1033 static int oxnas_pinctrl_remove(struct platform_device
*pdev
)
1035 struct oxnas_pinctrl
*info
= platform_get_drvdata(pdev
);
1037 pinctrl_unregister(info
->pctl
);
1042 static int oxnas_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1045 * Map back to global GPIO space and request muxing, the direction
1046 * parameter does not matter for this controller.
1048 int gpio
= chip
->base
+ offset
;
1049 int bank
= chip
->base
/ chip
->ngpio
;
1051 dev_dbg(chip
->dev
, "%s:%d MF_%c%d(%d)\n", __func__
, __LINE__
,
1052 'A' + bank
, offset
, gpio
);
1054 return pinctrl_request_gpio(gpio
);
1057 static void oxnas_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1059 int gpio
= chip
->base
+ offset
;
1061 pinctrl_free_gpio(gpio
);
1064 static int oxnas_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
1066 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1067 void __iomem
*pio
= oxnas_gpio
->regbase
;
1069 writel_relaxed(BIT(offset
), pio
+ OUTPUT_EN_CLEAR
);
1073 static int oxnas_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1075 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1076 void __iomem
*pio
= oxnas_gpio
->regbase
;
1077 unsigned mask
= 1 << offset
;
1080 pdsr
= readl_relaxed(pio
+ INPUT_VALUE
);
1081 return (pdsr
& mask
) != 0;
1084 static void oxnas_gpio_set(struct gpio_chip
*chip
, unsigned offset
,
1087 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1088 void __iomem
*pio
= oxnas_gpio
->regbase
;
1091 writel_relaxed(BIT(offset
), pio
+ OUTPUT_SET
);
1093 writel_relaxed(BIT(offset
), pio
+ OUTPUT_CLEAR
);
1097 static int oxnas_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
1100 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1101 void __iomem
*pio
= oxnas_gpio
->regbase
;
1104 writel_relaxed(BIT(offset
), pio
+ OUTPUT_SET
);
1106 writel_relaxed(BIT(offset
), pio
+ OUTPUT_CLEAR
);
1108 writel_relaxed(BIT(offset
), pio
+ OUTPUT_EN_SET
);
1113 static int oxnas_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
1115 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1118 if (offset
< chip
->ngpio
)
1119 virq
= irq_create_mapping(oxnas_gpio
->domain
, offset
);
1123 dev_dbg(chip
->dev
, "%s: request IRQ for GPIO %d, return %d\n",
1124 chip
->label
, offset
+ chip
->base
, virq
);
1128 #ifdef CONFIG_DEBUG_FS
1129 static void oxnas_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
1131 enum oxnas_mux mode
;
1133 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1134 void __iomem
*pio
= oxnas_gpio
->regbase
;
1135 void __iomem
*cio
= oxnas_gpio
->ctrlbase
;
1137 for (i
= 0; i
< chip
->ngpio
; i
++) {
1138 unsigned pin
= chip
->base
+ i
;
1139 unsigned mask
= pin_to_mask(pin
);
1140 const char *gpio_label
;
1143 gpio_label
= gpiochip_is_requested(chip
, i
);
1147 mode
= oxnas_mux_get_func(cio
, mask
);
1148 seq_printf(s
, "[%s] GPIO%s%d: ",
1149 gpio_label
, chip
->label
, i
);
1150 if (mode
== OXNAS_PINMUX_GPIO
) {
1151 pdsr
= readl_relaxed(pio
+ INPUT_VALUE
);
1153 seq_printf(s
, "[gpio] %s\n",
1157 seq_printf(s
, "[periph %c]\n",
1163 #define oxnas_gpio_dbg_show NULL
1166 /* Several AIC controller irqs are dispatched through this GPIO handler.
1167 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1168 * oxnas_set_gpio_input() then maybe enable its glitch filter.
1169 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1173 static void gpio_irq_mask(struct irq_data
*d
)
1175 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(d
);
1176 void __iomem
*pio
= oxnas_gpio
->regbase
;
1177 unsigned mask
= 1 << d
->hwirq
;
1178 unsigned type
= irqd_get_trigger_type(d
);
1180 /* FIXME: need proper lock */
1181 if (type
& IRQ_TYPE_EDGE_RISING
)
1182 oxnas_register_clear_mask(pio
+ RE_IRQ_ENABLE
, mask
);
1183 if (type
& IRQ_TYPE_EDGE_FALLING
)
1184 oxnas_register_clear_mask(pio
+ FE_IRQ_ENABLE
, mask
);
1187 static void gpio_irq_unmask(struct irq_data
*d
)
1189 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(d
);
1190 void __iomem
*pio
= oxnas_gpio
->regbase
;
1191 unsigned mask
= 1 << d
->hwirq
;
1192 unsigned type
= irqd_get_trigger_type(d
);
1194 /* FIXME: need proper lock */
1195 if (type
& IRQ_TYPE_EDGE_RISING
)
1196 oxnas_register_set_mask(pio
+ RE_IRQ_ENABLE
, mask
);
1197 if (type
& IRQ_TYPE_EDGE_FALLING
)
1198 oxnas_register_set_mask(pio
+ FE_IRQ_ENABLE
, mask
);
1202 static int gpio_irq_type(struct irq_data
*d
, unsigned type
)
1204 if ((type
& IRQ_TYPE_EDGE_BOTH
) == 0) {
1205 pr_warn("OX820: Unsupported type for irq %d\n",
1206 gpio_to_irq(d
->irq
));
1209 /* seems no way to set trigger type without enable irq, so leave it to unmask time */
1214 static struct irq_chip gpio_irqchip
= {
1216 .irq_disable
= gpio_irq_mask
,
1217 .irq_mask
= gpio_irq_mask
,
1218 .irq_unmask
= gpio_irq_unmask
,
1219 .irq_set_type
= gpio_irq_type
,
1222 static void gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
1224 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1225 struct irq_data
*idata
= irq_desc_get_irq_data(desc
);
1226 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(idata
);
1227 void __iomem
*pio
= oxnas_gpio
->regbase
;
1231 chained_irq_enter(chip
, desc
);
1233 /* TODO: see if it works */
1234 isr
= readl_relaxed(pio
+ IRQ_PENDING
);
1237 /* acks pending interrupts */
1238 writel_relaxed(isr
, pio
+ IRQ_PENDING
);
1240 for_each_set_bit(n
, &isr
, BITS_PER_LONG
) {
1241 generic_handle_irq(irq_find_mapping(oxnas_gpio
->domain
,
1245 chained_irq_exit(chip
, desc
);
1246 /* now it may re-trigger */
1250 * This lock class tells lockdep that GPIO irqs are in a different
1251 * category than their parents, so it won't report false recursion.
1253 static struct lock_class_key gpio_lock_class
;
1255 static int oxnas_gpio_irq_map(struct irq_domain
*h
, unsigned int virq
,
1258 struct oxnas_gpio_chip
*oxnas_gpio
= h
->host_data
;
1260 irq_set_lockdep_class(virq
, &gpio_lock_class
);
1262 irq_set_chip_and_handler(virq
, &gpio_irqchip
, handle_edge_irq
);
1263 set_irq_flags(virq
, IRQF_VALID
);
1264 irq_set_chip_data(virq
, oxnas_gpio
);
1269 static int oxnas_gpio_irq_domain_xlate(struct irq_domain
*d
,
1270 struct device_node
*ctrlr
,
1272 unsigned int intsize
,
1273 irq_hw_number_t
*out_hwirq
,
1274 unsigned int *out_type
)
1276 struct oxnas_gpio_chip
*oxnas_gpio
= d
->host_data
;
1278 int pin
= oxnas_gpio
->chip
.base
+ intspec
[0];
1280 if (WARN_ON(intsize
< 2))
1282 *out_hwirq
= intspec
[0];
1283 *out_type
= intspec
[1] & IRQ_TYPE_SENSE_MASK
;
1285 ret
= gpio_request(pin
, ctrlr
->full_name
);
1289 ret
= gpio_direction_input(pin
);
1296 static struct irq_domain_ops oxnas_gpio_ops
= {
1297 .map
= oxnas_gpio_irq_map
,
1298 .xlate
= oxnas_gpio_irq_domain_xlate
,
1301 static int oxnas_gpio_of_irq_setup(struct device_node
*node
,
1302 struct oxnas_gpio_chip
*oxnas_gpio
,
1305 /* Disable irqs of this controller */
1306 writel_relaxed(0, oxnas_gpio
->regbase
+ RE_IRQ_ENABLE
);
1307 writel_relaxed(0, oxnas_gpio
->regbase
+ FE_IRQ_ENABLE
);
1309 /* Setup irq domain */
1310 oxnas_gpio
->domain
= irq_domain_add_linear(node
, oxnas_gpio
->chip
.ngpio
,
1311 &oxnas_gpio_ops
, oxnas_gpio
);
1312 if (!oxnas_gpio
->domain
)
1313 panic("oxnas_gpio: couldn't allocate irq domain (DT).\n");
1315 irq_set_chip_data(irq
, oxnas_gpio
);
1316 irq_set_chained_handler(irq
, gpio_irq_handler
);
1321 /* This structure is replicated for each GPIO block allocated at probe time */
1322 static struct gpio_chip oxnas_gpio_template
= {
1323 .request
= oxnas_gpio_request
,
1324 .free
= oxnas_gpio_free
,
1325 .direction_input
= oxnas_gpio_direction_input
,
1326 .get
= oxnas_gpio_get
,
1327 .direction_output
= oxnas_gpio_direction_output
,
1328 .set
= oxnas_gpio_set
,
1329 .to_irq
= oxnas_gpio_to_irq
,
1330 .dbg_show
= oxnas_gpio_dbg_show
,
1332 .ngpio
= MAX_NB_GPIO_PER_BANK
,
1335 static struct of_device_id oxnas_gpio_of_match
[] = {
1336 { .compatible
= "plxtech,nas782x-gpio"},
1340 static int oxnas_gpio_probe(struct platform_device
*pdev
)
1342 struct device_node
*np
= pdev
->dev
.of_node
;
1343 struct resource
*res
;
1344 struct oxnas_gpio_chip
*oxnas_chip
= NULL
;
1345 struct gpio_chip
*chip
;
1346 struct pinctrl_gpio_range
*range
;
1349 int alias_idx
= of_alias_get_id(np
, "gpio");
1353 BUG_ON(alias_idx
>= ARRAY_SIZE(gpio_chips
));
1354 if (gpio_chips
[alias_idx
]) {
1359 irq
= platform_get_irq(pdev
, 0);
1365 oxnas_chip
= devm_kzalloc(&pdev
->dev
, sizeof(*oxnas_chip
), GFP_KERNEL
);
1371 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1372 oxnas_chip
->regbase
= devm_ioremap_resource(&pdev
->dev
, res
);
1373 if (IS_ERR(oxnas_chip
->regbase
)) {
1374 ret
= PTR_ERR(oxnas_chip
->regbase
);
1378 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1379 oxnas_chip
->ctrlbase
= devm_ioremap_resource(&pdev
->dev
, res
);
1380 if (IS_ERR(oxnas_chip
->ctrlbase
)) {
1381 ret
= PTR_ERR(oxnas_chip
->ctrlbase
);
1385 oxnas_chip
->chip
= oxnas_gpio_template
;
1387 chip
= &oxnas_chip
->chip
;
1389 chip
->label
= dev_name(&pdev
->dev
);
1390 chip
->dev
= &pdev
->dev
;
1391 chip
->owner
= THIS_MODULE
;
1392 chip
->base
= alias_idx
* MAX_NB_GPIO_PER_BANK
;
1394 if (!of_property_read_u32(np
, "#gpio-lines", &ngpio
)) {
1395 if (ngpio
> MAX_NB_GPIO_PER_BANK
)
1396 pr_err("oxnas_gpio.%d, gpio-nb >= %d failback to %d\n",
1397 alias_idx
, MAX_NB_GPIO_PER_BANK
,
1398 MAX_NB_GPIO_PER_BANK
);
1400 chip
->ngpio
= ngpio
;
1403 names
= devm_kzalloc(&pdev
->dev
, sizeof(char *) * chip
->ngpio
,
1411 for (i
= 0; i
< chip
->ngpio
; i
++)
1412 names
[i
] = kasprintf(GFP_KERNEL
, "MF_%c%d", alias_idx
+ 'A', i
);
1414 chip
->names
= (const char *const *)names
;
1416 range
= &oxnas_chip
->range
;
1417 range
->name
= chip
->label
;
1418 range
->id
= alias_idx
;
1419 range
->pin_base
= range
->base
= range
->id
* MAX_NB_GPIO_PER_BANK
;
1421 range
->npins
= chip
->ngpio
;
1424 ret
= gpiochip_add(chip
);
1428 gpio_chips
[alias_idx
] = oxnas_chip
;
1429 gpio_banks
= max(gpio_banks
, alias_idx
+ 1);
1431 oxnas_gpio_of_irq_setup(np
, oxnas_chip
, irq
);
1433 dev_info(&pdev
->dev
, "at address %p\n", oxnas_chip
->regbase
);
1437 dev_err(&pdev
->dev
, "Failure %i for GPIO %i\n", ret
, alias_idx
);
1442 static struct platform_driver oxnas_gpio_driver
= {
1444 .name
= "gpio-oxnas",
1445 .owner
= THIS_MODULE
,
1446 .of_match_table
= of_match_ptr(oxnas_gpio_of_match
),
1448 .probe
= oxnas_gpio_probe
,
1451 static struct platform_driver oxnas_pinctrl_driver
= {
1453 .name
= "pinctrl-oxnas",
1454 .owner
= THIS_MODULE
,
1455 .of_match_table
= of_match_ptr(oxnas_pinctrl_of_match
),
1457 .probe
= oxnas_pinctrl_probe
,
1458 .remove
= oxnas_pinctrl_remove
,
1461 static int __init
oxnas_pinctrl_init(void)
1465 ret
= platform_driver_register(&oxnas_gpio_driver
);
1468 return platform_driver_register(&oxnas_pinctrl_driver
);
1470 arch_initcall(oxnas_pinctrl_init
);
1472 static void __exit
oxnas_pinctrl_exit(void)
1474 platform_driver_unregister(&oxnas_pinctrl_driver
);
1477 module_exit(oxnas_pinctrl_exit
);
1478 MODULE_AUTHOR("Ma Hajun <mahaijuns@gmail.com>");
1479 MODULE_DESCRIPTION("Plxtech Nas782x pinctrl driver");
1480 MODULE_LICENSE("GPL v2");