2 * oxnas pinctrl driver based on at91 pinctrl driver
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/init.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
22 #include <linux/gpio.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 /* Since we request GPIOs from ourself */
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/spinlock.h>
33 #include <mach/utils.h>
35 #define MAX_NB_GPIO_PER_BANK 32
36 #define MAX_GPIO_BANKS 2
38 struct oxnas_gpio_chip
{
39 struct gpio_chip chip
;
40 struct pinctrl_gpio_range range
;
41 void __iomem
*regbase
; /* GPIOA/B virtual address */
42 void __iomem
*ctrlbase
; /* SYS/SEC_CTRL virtual address */
43 struct irq_domain
*domain
; /* associated irq domain */
47 #define to_oxnas_gpio_chip(c) container_of(c, struct oxnas_gpio_chip, chip)
49 static struct oxnas_gpio_chip
*gpio_chips
[MAX_GPIO_BANKS
];
51 static int gpio_banks
;
53 #define PULL_UP (1 << 0)
54 #define PULL_DOWN (1 << 1)
55 #define DEBOUNCE (1 << 2)
58 * struct oxnas_pmx_func - describes pinmux functions
59 * @name: the name of this specific function
60 * @groups: corresponding pin groups
61 * @ngroups: the number of groups
63 struct oxnas_pmx_func
{
86 OUTPUT_EN_CLEAR
= 0x20,
87 DEBOUNCE_ENABLE
= 0x24,
88 RE_IRQ_ENABLE
= 0x28, /* rising edge */
89 FE_IRQ_ENABLE
= 0x2C, /* falling edge */
90 RE_IRQ_PENDING
= 0x30, /* rising edge */
91 FE_IRQ_PENDING
= 0x34, /* falling edge */
94 PULL_SENSE
= 0x54, /* 1 up, 0 down */
97 DEBOUNCE_MASK
= 0x3FFF0000,
98 /* put hw debounce and soft config at same bit position*/
103 PINMUX_SECONDARY_SEL
= 0x14,
104 PINMUX_TERTIARY_SEL
= 0x8c,
105 PINMUX_QUATERNARY_SEL
= 0x94,
106 PINMUX_DEBUG_SEL
= 0x9c,
107 PINMUX_ALTERNATIVE_SEL
= 0xa4,
108 PINMUX_PULLUP_SEL
= 0xac,
112 * struct oxnas_pmx_pin - describes an pin mux
113 * @bank: the bank of the pin
114 * @pin: the pin number in the @bank
115 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
116 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
118 struct oxnas_pmx_pin
{
126 * struct oxnas_pin_group - describes an pin group
127 * @name: the name of this specific pin group
128 * @pins_conf: the mux mode for each pin in this group. The size of this
129 * array is the same as pins.
130 * @pins: an array of discrete physical pins used in this group, taken
131 * from the driver-local pin enumeration space
132 * @npins: the number of pins in this group array, i.e. the number of
133 * elements in .pins so we can iterate over that array
135 struct oxnas_pin_group
{
137 struct oxnas_pmx_pin
*pins_conf
;
142 struct oxnas_pinctrl
{
144 struct pinctrl_dev
*pctl
;
151 struct oxnas_pmx_func
*functions
;
154 struct oxnas_pin_group
*groups
;
158 static const inline struct oxnas_pin_group
*oxnas_pinctrl_find_group_by_name(
159 const struct oxnas_pinctrl
*info
,
162 const struct oxnas_pin_group
*grp
= NULL
;
165 for (i
= 0; i
< info
->ngroups
; i
++) {
166 if (strcmp(info
->groups
[i
].name
, name
))
169 grp
= &info
->groups
[i
];
170 dev_dbg(info
->dev
, "%s: %d 0:%d\n", name
, grp
->npins
,
178 static int oxnas_get_groups_count(struct pinctrl_dev
*pctldev
)
180 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
182 return info
->ngroups
;
185 static const char *oxnas_get_group_name(struct pinctrl_dev
*pctldev
,
188 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
190 return info
->groups
[selector
].name
;
193 static int oxnas_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
194 const unsigned **pins
,
197 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
199 if (selector
>= info
->ngroups
)
202 *pins
= info
->groups
[selector
].pins
;
203 *npins
= info
->groups
[selector
].npins
;
208 static void oxnas_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
211 seq_printf(s
, "%s", dev_name(pctldev
->dev
));
214 static int oxnas_dt_node_to_map(struct pinctrl_dev
*pctldev
,
215 struct device_node
*np
,
216 struct pinctrl_map
**map
, unsigned *num_maps
)
218 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
219 const struct oxnas_pin_group
*grp
;
220 struct pinctrl_map
*new_map
;
221 struct device_node
*parent
;
226 * first find the group of this node and check if we need create
227 * config maps for pins
229 grp
= oxnas_pinctrl_find_group_by_name(info
, np
->name
);
231 dev_err(info
->dev
, "unable to find group for node %s\n",
236 map_num
+= grp
->npins
;
237 new_map
= devm_kzalloc(pctldev
->dev
, sizeof(*new_map
) * map_num
,
246 parent
= of_get_parent(np
);
248 devm_kfree(pctldev
->dev
, new_map
);
251 new_map
[0].type
= PIN_MAP_TYPE_MUX_GROUP
;
252 new_map
[0].data
.mux
.function
= parent
->name
;
253 new_map
[0].data
.mux
.group
= np
->name
;
256 /* create config map */
258 for (i
= 0; i
< grp
->npins
; i
++) {
259 new_map
[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
260 new_map
[i
].data
.configs
.group_or_pin
=
261 pin_get_name(pctldev
, grp
->pins
[i
]);
262 new_map
[i
].data
.configs
.configs
= &grp
->pins_conf
[i
].conf
;
263 new_map
[i
].data
.configs
.num_configs
= 1;
266 dev_dbg(pctldev
->dev
, "maps: function %s group %s num %d\n",
267 (*map
)->data
.mux
.function
, (*map
)->data
.mux
.group
, map_num
);
272 static void oxnas_dt_free_map(struct pinctrl_dev
*pctldev
,
273 struct pinctrl_map
*map
, unsigned num_maps
)
277 static const struct pinctrl_ops oxnas_pctrl_ops
= {
278 .get_groups_count
= oxnas_get_groups_count
,
279 .get_group_name
= oxnas_get_group_name
,
280 .get_group_pins
= oxnas_get_group_pins
,
281 .pin_dbg_show
= oxnas_pin_dbg_show
,
282 .dt_node_to_map
= oxnas_dt_node_to_map
,
283 .dt_free_map
= oxnas_dt_free_map
,
286 static void __iomem
*pin_to_gpioctrl(struct oxnas_pinctrl
*info
,
289 return gpio_chips
[bank
]->regbase
;
292 static void __iomem
*pin_to_muxctrl(struct oxnas_pinctrl
*info
,
295 return gpio_chips
[bank
]->ctrlbase
;
299 static inline int pin_to_bank(unsigned pin
)
301 return pin
/ MAX_NB_GPIO_PER_BANK
;
304 static unsigned pin_to_mask(unsigned int pin
)
309 static void oxnas_mux_disable_interrupt(void __iomem
*pio
, unsigned mask
)
311 oxnas_register_clear_mask(pio
+ RE_IRQ_ENABLE
, mask
);
312 oxnas_register_clear_mask(pio
+ FE_IRQ_ENABLE
, mask
);
315 static unsigned oxnas_mux_get_pullup(void __iomem
*pio
, unsigned pin
)
317 return (readl_relaxed(pio
+ PULL_ENABLE
) & BIT(pin
)) &&
318 (readl_relaxed(pio
+ PULL_SENSE
) & BIT(pin
));
321 static void oxnas_mux_set_pullup(void __iomem
*pio
, unsigned mask
, bool on
)
324 oxnas_register_set_mask(pio
+ PULL_SENSE
, mask
);
325 oxnas_register_set_mask(pio
+ PULL_ENABLE
, mask
);
327 oxnas_register_clear_mask(pio
+ PULL_ENABLE
, mask
);
331 static bool oxnas_mux_get_pulldown(void __iomem
*pio
, unsigned pin
)
333 return (readl_relaxed(pio
+ PULL_ENABLE
) & BIT(pin
)) &&
334 (!(readl_relaxed(pio
+ PULL_SENSE
) & BIT(pin
)));
337 static void oxnas_mux_set_pulldown(void __iomem
*pio
, unsigned mask
, bool on
)
340 oxnas_register_clear_mask(pio
+ PULL_SENSE
, mask
);
341 oxnas_register_set_mask(pio
+ PULL_ENABLE
, mask
);
343 oxnas_register_clear_mask(pio
+ PULL_ENABLE
, mask
);
347 /* unfortunately debounce control are shared */
348 static bool oxnas_mux_get_debounce(void __iomem
*pio
, unsigned pin
, u32
*div
)
350 *div
= __raw_readl(pio
+ CLOCK_DIV
) & DEBOUNCE_MASK
;
351 return __raw_readl(pio
+ DEBOUNCE_ENABLE
) & BIT(pin
);
354 static void oxnas_mux_set_debounce(void __iomem
*pio
, unsigned mask
,
358 oxnas_register_value_mask(pio
+ CLOCK_DIV
, DEBOUNCE_MASK
, div
);
359 oxnas_register_set_mask(pio
+ DEBOUNCE_ENABLE
, mask
);
361 oxnas_register_clear_mask(pio
+ DEBOUNCE_ENABLE
, mask
);
366 static void oxnas_mux_set_func2(void __iomem
*cio
, unsigned mask
)
368 /* in fact, SECONDARY takes precedence, so clear others is not necessary */
369 oxnas_register_set_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
370 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
371 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
372 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
373 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
376 static void oxnas_mux_set_func3(void __iomem
*cio
, unsigned mask
)
378 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
379 oxnas_register_set_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
380 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
381 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
382 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
385 static void oxnas_mux_set_func4(void __iomem
*cio
, unsigned mask
)
387 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
388 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
389 oxnas_register_set_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
390 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
391 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
394 static void oxnas_mux_set_func_dbg(void __iomem
*cio
, unsigned mask
)
396 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
397 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
398 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
399 oxnas_register_set_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
400 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
403 static void oxnas_mux_set_func_alt(void __iomem
*cio
, unsigned mask
)
405 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
406 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
407 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
408 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
409 oxnas_register_set_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
412 static void oxnas_mux_set_gpio(void __iomem
*cio
, unsigned mask
)
414 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
415 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
416 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
417 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
418 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
421 static enum oxnas_mux
oxnas_mux_get_func(void __iomem
*cio
, unsigned mask
)
423 if (readl_relaxed(cio
+ PINMUX_SECONDARY_SEL
) & mask
)
424 return OXNAS_PINMUX_FUNC2
;
425 if (readl_relaxed(cio
+ PINMUX_TERTIARY_SEL
) & mask
)
426 return OXNAS_PINMUX_FUNC3
;
427 if (readl_relaxed(cio
+ PINMUX_QUATERNARY_SEL
) & mask
)
428 return OXNAS_PINMUX_FUNC4
;
429 if (readl_relaxed(cio
+ PINMUX_DEBUG_SEL
) & mask
)
430 return OXNAS_PINMUX_DEBUG
;
431 if (readl_relaxed(cio
+ PINMUX_ALTERNATIVE_SEL
) & mask
)
432 return OXNAS_PINMUX_ALT
;
433 return OXNAS_PINMUX_GPIO
;
437 static void oxnas_pin_dbg(const struct device
*dev
,
438 const struct oxnas_pmx_pin
*pin
)
442 "MF_%c%d configured as periph%c with conf = 0x%lu\n",
443 pin
->bank
+ 'A', pin
->pin
, pin
->mux
- 1 + 'A',
446 dev_dbg(dev
, "MF_%c%d configured as gpio with conf = 0x%lu\n",
447 pin
->bank
+ 'A', pin
->pin
, pin
->conf
);
451 static int pin_check_config(struct oxnas_pinctrl
*info
, const char *name
,
452 int index
, const struct oxnas_pmx_pin
*pin
)
456 /* check if it's a valid config */
457 if (pin
->bank
>= info
->nbanks
) {
458 dev_err(info
->dev
, "%s: pin conf %d bank_id %d >= nbanks %d\n",
459 name
, index
, pin
->bank
, info
->nbanks
);
463 if (pin
->pin
>= MAX_NB_GPIO_PER_BANK
) {
464 dev_err(info
->dev
, "%s: pin conf %d pin_bank_id %d >= %d\n",
465 name
, index
, pin
->pin
, MAX_NB_GPIO_PER_BANK
);
468 /* gpio always allowed */
474 if (mux
>= info
->nmux
) {
475 dev_err(info
->dev
, "%s: pin conf %d mux_id %d >= nmux %d\n",
476 name
, index
, mux
, info
->nmux
);
480 if (!(info
->mux_mask
[pin
->bank
* info
->nmux
+ mux
] & 1 << pin
->pin
)) {
481 dev_err(info
->dev
, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n",
482 name
, index
, mux
, pin
->bank
+ 'A', pin
->pin
);
489 static void oxnas_mux_gpio_enable(void __iomem
*cio
, void __iomem
*pio
,
490 unsigned mask
, bool input
)
492 oxnas_mux_set_gpio(cio
, mask
);
494 writel_relaxed(mask
, pio
+ OUTPUT_EN_CLEAR
);
496 writel_relaxed(mask
, pio
+ OUTPUT_EN_SET
);
499 static void oxnas_mux_gpio_disable(void __iomem
*cio
, void __iomem
*pio
,
502 /* when switch to other function, gpio is disabled automatically */
506 static int oxnas_pmx_set_mux(struct pinctrl_dev
*pctldev
, unsigned selector
,
509 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
510 const struct oxnas_pmx_pin
*pins_conf
= info
->groups
[group
].pins_conf
;
511 const struct oxnas_pmx_pin
*pin
;
512 uint32_t npins
= info
->groups
[group
].npins
;
518 dev_dbg(info
->dev
, "enable function %s group %s\n",
519 info
->functions
[selector
].name
, info
->groups
[group
].name
);
521 /* first check that all the pins of the group are valid with a valid
523 for (i
= 0; i
< npins
; i
++) {
525 ret
= pin_check_config(info
, info
->groups
[group
].name
, i
, pin
);
530 for (i
= 0; i
< npins
; i
++) {
532 oxnas_pin_dbg(info
->dev
, pin
);
534 pio
= pin_to_gpioctrl(info
, pin
->bank
);
535 cio
= pin_to_muxctrl(info
, pin
->bank
);
537 mask
= pin_to_mask(pin
->pin
);
538 oxnas_mux_disable_interrupt(pio
, mask
);
541 case OXNAS_PINMUX_GPIO
:
542 oxnas_mux_gpio_enable(cio
, pio
, mask
, 1);
544 case OXNAS_PINMUX_FUNC2
:
545 oxnas_mux_set_func2(cio
, mask
);
547 case OXNAS_PINMUX_FUNC3
:
548 oxnas_mux_set_func3(cio
, mask
);
550 case OXNAS_PINMUX_FUNC4
:
551 oxnas_mux_set_func4(cio
, mask
);
553 case OXNAS_PINMUX_DEBUG
:
554 oxnas_mux_set_func_dbg(cio
, mask
);
556 case OXNAS_PINMUX_ALT
:
557 oxnas_mux_set_func_alt(cio
, mask
);
561 oxnas_mux_gpio_disable(cio
, pio
, mask
);
567 static int oxnas_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
569 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
571 return info
->nfunctions
;
574 static const char *oxnas_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
577 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
579 return info
->functions
[selector
].name
;
582 static int oxnas_pmx_get_groups(struct pinctrl_dev
*pctldev
, unsigned selector
,
583 const char * const **groups
,
584 unsigned * const num_groups
)
586 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
588 *groups
= info
->functions
[selector
].groups
;
589 *num_groups
= info
->functions
[selector
].ngroups
;
594 static int oxnas_gpio_request_enable(struct pinctrl_dev
*pctldev
,
595 struct pinctrl_gpio_range
*range
,
598 struct oxnas_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
599 struct oxnas_gpio_chip
*oxnas_chip
;
600 struct gpio_chip
*chip
;
604 dev_err(npct
->dev
, "invalid range\n");
608 dev_err(npct
->dev
, "missing GPIO chip in range\n");
612 oxnas_chip
= container_of(chip
, struct oxnas_gpio_chip
, chip
);
614 dev_dbg(npct
->dev
, "enable pin %u as GPIO\n", offset
);
616 mask
= 1 << (offset
- chip
->base
);
618 dev_dbg(npct
->dev
, "enable pin %u as MF_%c%d 0x%x\n",
619 offset
, 'A' + range
->id
, offset
- chip
->base
, mask
);
621 oxnas_mux_set_gpio(oxnas_chip
->ctrlbase
, mask
);
626 static void oxnas_gpio_disable_free(struct pinctrl_dev
*pctldev
,
627 struct pinctrl_gpio_range
*range
,
630 struct oxnas_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
632 dev_dbg(npct
->dev
, "disable pin %u as GPIO\n", offset
);
633 /* Set the pin to some default state, GPIO is usually default */
636 static const struct pinmux_ops oxnas_pmx_ops
= {
637 .get_functions_count
= oxnas_pmx_get_funcs_count
,
638 .get_function_name
= oxnas_pmx_get_func_name
,
639 .get_function_groups
= oxnas_pmx_get_groups
,
640 .set_mux
= oxnas_pmx_set_mux
,
641 .gpio_request_enable
= oxnas_gpio_request_enable
,
642 .gpio_disable_free
= oxnas_gpio_disable_free
,
645 static int oxnas_pinconf_get(struct pinctrl_dev
*pctldev
,
646 unsigned pin_id
, unsigned long *config
)
648 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
653 dev_dbg(info
->dev
, "%s:%d, pin_id=%d, config=0x%lx", __func__
,
654 __LINE__
, pin_id
, *config
);
655 pio
= pin_to_gpioctrl(info
, pin_to_bank(pin_id
));
656 pin
= pin_id
% MAX_NB_GPIO_PER_BANK
;
658 if (oxnas_mux_get_pullup(pio
, pin
))
661 if (oxnas_mux_get_pulldown(pio
, pin
))
662 *config
|= PULL_DOWN
;
664 if (oxnas_mux_get_debounce(pio
, pin
, &div
))
665 *config
|= DEBOUNCE
| div
;
669 static int oxnas_pinconf_set(struct pinctrl_dev
*pctldev
,
670 unsigned pin_id
, unsigned long *configs
,
671 unsigned num_configs
)
673 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
677 unsigned long config
;
679 pio
= pin_to_gpioctrl(info
, pin_to_bank(pin_id
));
680 mask
= pin_to_mask(pin_id
% MAX_NB_GPIO_PER_BANK
);
682 for (i
= 0; i
< num_configs
; i
++) {
686 "%s:%d, pin_id=%d, config=0x%lx",
687 __func__
, __LINE__
, pin_id
, config
);
689 if ((config
& PULL_UP
) && (config
& PULL_DOWN
))
692 oxnas_mux_set_pullup(pio
, mask
, config
& PULL_UP
);
693 oxnas_mux_set_pulldown(pio
, mask
, config
& PULL_DOWN
);
694 oxnas_mux_set_debounce(pio
, mask
, config
& DEBOUNCE
,
695 config
& DEBOUNCE_MASK
);
697 } /* for each config */
702 static void oxnas_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
703 struct seq_file
*s
, unsigned pin_id
)
708 static void oxnas_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
709 struct seq_file
*s
, unsigned group
)
713 static const struct pinconf_ops oxnas_pinconf_ops
= {
714 .pin_config_get
= oxnas_pinconf_get
,
715 .pin_config_set
= oxnas_pinconf_set
,
716 .pin_config_dbg_show
= oxnas_pinconf_dbg_show
,
717 .pin_config_group_dbg_show
= oxnas_pinconf_group_dbg_show
,
720 static struct pinctrl_desc oxnas_pinctrl_desc
= {
721 .pctlops
= &oxnas_pctrl_ops
,
722 .pmxops
= &oxnas_pmx_ops
,
723 .confops
= &oxnas_pinconf_ops
,
724 .owner
= THIS_MODULE
,
727 static const char *gpio_compat
= "plxtech,nas782x-gpio";
729 static void oxnas_pinctrl_child_count(struct oxnas_pinctrl
*info
,
730 struct device_node
*np
)
732 struct device_node
*child
;
734 for_each_child_of_node(np
, child
) {
735 if (of_device_is_compatible(child
, gpio_compat
)) {
739 info
->ngroups
+= of_get_child_count(child
);
744 static int oxnas_pinctrl_mux_mask(struct oxnas_pinctrl
*info
,
745 struct device_node
*np
)
751 list
= of_get_property(np
, "plxtech,mux-mask", &size
);
753 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
757 size
/= sizeof(*list
);
758 if (!size
|| size
% info
->nbanks
) {
759 dev_err(info
->dev
, "wrong mux mask array should be by %d\n",
763 info
->nmux
= size
/ info
->nbanks
;
765 info
->mux_mask
= devm_kzalloc(info
->dev
, sizeof(u32
) * size
, GFP_KERNEL
);
766 if (!info
->mux_mask
) {
767 dev_err(info
->dev
, "could not alloc mux_mask\n");
771 ret
= of_property_read_u32_array(np
, "plxtech,mux-mask",
772 info
->mux_mask
, size
);
774 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
778 static int oxnas_pinctrl_parse_groups(struct device_node
*np
,
779 struct oxnas_pin_group
*grp
,
780 struct oxnas_pinctrl
*info
, u32 index
)
782 struct oxnas_pmx_pin
*pin
;
787 dev_dbg(info
->dev
, "group(%d): %s\n", index
, np
->name
);
789 /* Initialise group */
790 grp
->name
= np
->name
;
793 * the binding format is plxtech,pins = <bank pin mux CONFIG ...>,
794 * do sanity check and calculate pins number
796 list
= of_get_property(np
, "plxtech,pins", &size
);
797 /* we do not check return since it's safe node passed down */
798 size
/= sizeof(*list
);
799 if (!size
|| size
% 4) {
800 dev_err(info
->dev
, "wrong pins number or pins and configs"
801 " should be divisible by 4\n");
805 grp
->npins
= size
/ 4;
806 pin
= grp
->pins_conf
= devm_kzalloc(info
->dev
,
807 grp
->npins
* sizeof(struct oxnas_pmx_pin
),
809 grp
->pins
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(unsigned int),
811 if (!grp
->pins_conf
|| !grp
->pins
)
814 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
815 pin
->bank
= be32_to_cpu(*list
++);
816 pin
->pin
= be32_to_cpu(*list
++);
817 grp
->pins
[j
] = pin
->bank
* MAX_NB_GPIO_PER_BANK
+ pin
->pin
;
818 pin
->mux
= be32_to_cpu(*list
++);
819 pin
->conf
= be32_to_cpu(*list
++);
821 oxnas_pin_dbg(info
->dev
, pin
);
828 static int oxnas_pinctrl_parse_functions(struct device_node
*np
,
829 struct oxnas_pinctrl
*info
, u32 index
)
831 struct device_node
*child
;
832 struct oxnas_pmx_func
*func
;
833 struct oxnas_pin_group
*grp
;
835 static u32 grp_index
;
838 dev_dbg(info
->dev
, "parse function(%d): %s\n", index
, np
->name
);
840 func
= &info
->functions
[index
];
842 /* Initialise function */
843 func
->name
= np
->name
;
844 func
->ngroups
= of_get_child_count(np
);
845 if (func
->ngroups
<= 0) {
846 dev_err(info
->dev
, "no groups defined\n");
849 func
->groups
= devm_kzalloc(info
->dev
,
850 func
->ngroups
* sizeof(char *), GFP_KERNEL
);
854 for_each_child_of_node(np
, child
) {
855 func
->groups
[i
] = child
->name
;
856 grp
= &info
->groups
[grp_index
++];
857 ret
= oxnas_pinctrl_parse_groups(child
, grp
, info
, i
++);
865 static struct of_device_id oxnas_pinctrl_of_match
[] = {
866 { .compatible
= "plxtech,nas782x-pinctrl"},
870 static int oxnas_pinctrl_probe_dt(struct platform_device
*pdev
,
871 struct oxnas_pinctrl
*info
)
876 struct device_node
*np
= pdev
->dev
.of_node
;
877 struct device_node
*child
;
882 info
->dev
= &pdev
->dev
;
884 oxnas_pinctrl_child_count(info
, np
);
886 if (info
->nbanks
< 1) {
887 dev_err(&pdev
->dev
, "you need to specify atleast one gpio-controller\n");
891 ret
= oxnas_pinctrl_mux_mask(info
, np
);
895 dev_dbg(&pdev
->dev
, "nmux = %d\n", info
->nmux
);
897 dev_dbg(&pdev
->dev
, "mux-mask\n");
898 tmp
= info
->mux_mask
;
899 for (i
= 0; i
< info
->nbanks
; i
++)
900 for (j
= 0; j
< info
->nmux
; j
++, tmp
++)
901 dev_dbg(&pdev
->dev
, "%d:%d\t0x%x\n", i
, j
, tmp
[0]);
903 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
904 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
905 info
->functions
= devm_kzalloc(&pdev
->dev
, info
->nfunctions
*
906 sizeof(struct oxnas_pmx_func
),
908 if (!info
->functions
)
911 info
->groups
= devm_kzalloc(&pdev
->dev
, info
->ngroups
*
912 sizeof(struct oxnas_pin_group
),
917 dev_dbg(&pdev
->dev
, "nbanks = %d\n", info
->nbanks
);
918 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
919 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
923 for_each_child_of_node(np
, child
) {
924 if (of_device_is_compatible(child
, gpio_compat
))
926 ret
= oxnas_pinctrl_parse_functions(child
, info
, i
++);
928 dev_err(&pdev
->dev
, "failed to parse function\n");
936 static int oxnas_pinctrl_probe(struct platform_device
*pdev
)
938 struct oxnas_pinctrl
*info
;
939 struct pinctrl_pin_desc
*pdesc
;
942 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
946 ret
= oxnas_pinctrl_probe_dt(pdev
, info
);
951 * We need all the GPIO drivers to probe FIRST, or we will not be able
952 * to obtain references to the struct gpio_chip * for them, and we
953 * need this to proceed.
955 for (i
= 0; i
< info
->nbanks
; i
++) {
956 if (!gpio_chips
[i
]) {
958 "GPIO chip %d not registered yet\n", i
);
959 devm_kfree(&pdev
->dev
, info
);
960 return -EPROBE_DEFER
;
964 oxnas_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
965 oxnas_pinctrl_desc
.npins
= info
->nbanks
* MAX_NB_GPIO_PER_BANK
;
966 oxnas_pinctrl_desc
.pins
= pdesc
=
967 devm_kzalloc(&pdev
->dev
, sizeof(*pdesc
) *
968 oxnas_pinctrl_desc
.npins
, GFP_KERNEL
);
970 if (!oxnas_pinctrl_desc
.pins
)
973 for (i
= 0 , k
= 0; i
< info
->nbanks
; i
++) {
974 for (j
= 0; j
< MAX_NB_GPIO_PER_BANK
; j
++, k
++) {
976 pdesc
->name
= kasprintf(GFP_KERNEL
, "MF_%c%d", i
+ 'A',
982 platform_set_drvdata(pdev
, info
);
983 info
->pctl
= pinctrl_register(&oxnas_pinctrl_desc
, &pdev
->dev
, info
);
986 dev_err(&pdev
->dev
, "could not register OX820 pinctrl driver\n");
991 /* We will handle a range of GPIO pins */
992 for (i
= 0; i
< info
->nbanks
; i
++)
993 pinctrl_add_gpio_range(info
->pctl
, &gpio_chips
[i
]->range
);
995 dev_info(&pdev
->dev
, "initialized OX820 pinctrl driver\n");
1003 static int oxnas_pinctrl_remove(struct platform_device
*pdev
)
1005 struct oxnas_pinctrl
*info
= platform_get_drvdata(pdev
);
1007 pinctrl_unregister(info
->pctl
);
1012 static int oxnas_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1015 * Map back to global GPIO space and request muxing, the direction
1016 * parameter does not matter for this controller.
1018 int gpio
= chip
->base
+ offset
;
1019 int bank
= chip
->base
/ chip
->ngpio
;
1021 dev_dbg(chip
->dev
, "%s:%d MF_%c%d(%d)\n", __func__
, __LINE__
,
1022 'A' + bank
, offset
, gpio
);
1024 return pinctrl_request_gpio(gpio
);
1027 static void oxnas_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1029 int gpio
= chip
->base
+ offset
;
1031 pinctrl_free_gpio(gpio
);
1034 static int oxnas_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
1036 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1037 void __iomem
*pio
= oxnas_gpio
->regbase
;
1039 writel_relaxed(BIT(offset
), pio
+ OUTPUT_EN_CLEAR
);
1043 static int oxnas_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1045 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1046 void __iomem
*pio
= oxnas_gpio
->regbase
;
1047 unsigned mask
= 1 << offset
;
1050 pdsr
= readl_relaxed(pio
+ INPUT_VALUE
);
1051 return (pdsr
& mask
) != 0;
1054 static void oxnas_gpio_set(struct gpio_chip
*chip
, unsigned offset
,
1057 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1058 void __iomem
*pio
= oxnas_gpio
->regbase
;
1061 writel_relaxed(BIT(offset
), pio
+ OUTPUT_SET
);
1063 writel_relaxed(BIT(offset
), pio
+ OUTPUT_CLEAR
);
1067 static int oxnas_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
1070 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1071 void __iomem
*pio
= oxnas_gpio
->regbase
;
1074 writel_relaxed(BIT(offset
), pio
+ OUTPUT_SET
);
1076 writel_relaxed(BIT(offset
), pio
+ OUTPUT_CLEAR
);
1078 writel_relaxed(BIT(offset
), pio
+ OUTPUT_EN_SET
);
1083 static int oxnas_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
1085 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1088 if (offset
< chip
->ngpio
)
1089 virq
= irq_create_mapping(oxnas_gpio
->domain
, offset
);
1093 dev_dbg(chip
->dev
, "%s: request IRQ for GPIO %d, return %d\n",
1094 chip
->label
, offset
+ chip
->base
, virq
);
1098 #ifdef CONFIG_DEBUG_FS
1099 static void oxnas_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
1101 enum oxnas_mux mode
;
1103 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1104 void __iomem
*pio
= oxnas_gpio
->regbase
;
1105 void __iomem
*cio
= oxnas_gpio
->ctrlbase
;
1107 for (i
= 0; i
< chip
->ngpio
; i
++) {
1108 unsigned pin
= chip
->base
+ i
;
1109 unsigned mask
= pin_to_mask(pin
);
1110 const char *gpio_label
;
1113 gpio_label
= gpiochip_is_requested(chip
, i
);
1117 mode
= oxnas_mux_get_func(cio
, mask
);
1118 seq_printf(s
, "[%s] GPIO%s%d: ",
1119 gpio_label
, chip
->label
, i
);
1120 if (mode
== OXNAS_PINMUX_GPIO
) {
1121 pdsr
= readl_relaxed(pio
+ INPUT_VALUE
);
1123 seq_printf(s
, "[gpio] %s\n",
1127 seq_printf(s
, "[periph %c]\n",
1133 #define oxnas_gpio_dbg_show NULL
1136 /* Several AIC controller irqs are dispatched through this GPIO handler.
1137 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1138 * oxnas_set_gpio_input() then maybe enable its glitch filter.
1139 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1143 static void gpio_irq_mask(struct irq_data
*d
)
1145 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(d
);
1146 void __iomem
*pio
= oxnas_gpio
->regbase
;
1147 unsigned mask
= 1 << d
->hwirq
;
1148 unsigned type
= irqd_get_trigger_type(d
);
1149 unsigned long flags
;
1151 if (!(type
& IRQ_TYPE_EDGE_BOTH
))
1154 spin_lock_irqsave(&oxnas_gpio
->lock
, flags
);
1155 if (type
& IRQ_TYPE_EDGE_RISING
)
1156 oxnas_register_clear_mask(pio
+ RE_IRQ_ENABLE
, mask
);
1157 if (type
& IRQ_TYPE_EDGE_FALLING
)
1158 oxnas_register_clear_mask(pio
+ FE_IRQ_ENABLE
, mask
);
1159 spin_unlock_irqrestore(&oxnas_gpio
->lock
, flags
);
1162 static void gpio_irq_unmask(struct irq_data
*d
)
1164 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(d
);
1165 void __iomem
*pio
= oxnas_gpio
->regbase
;
1166 unsigned mask
= 1 << d
->hwirq
;
1167 unsigned type
= irqd_get_trigger_type(d
);
1168 unsigned long flags
;
1170 if (!(type
& IRQ_TYPE_EDGE_BOTH
))
1173 spin_lock_irqsave(&oxnas_gpio
->lock
, flags
);
1174 if (type
& IRQ_TYPE_EDGE_RISING
)
1175 oxnas_register_set_mask(pio
+ RE_IRQ_ENABLE
, mask
);
1176 if (type
& IRQ_TYPE_EDGE_FALLING
)
1177 oxnas_register_set_mask(pio
+ FE_IRQ_ENABLE
, mask
);
1178 spin_unlock_irqrestore(&oxnas_gpio
->lock
, flags
);
1182 static int gpio_irq_type(struct irq_data
*d
, unsigned type
)
1184 if ((type
& IRQ_TYPE_EDGE_BOTH
) == 0) {
1185 pr_warn("OX820: Unsupported type for irq %d\n",
1186 gpio_to_irq(d
->irq
));
1189 /* seems no way to set trigger type without enable irq, so leave it to unmask time */
1194 static struct irq_chip gpio_irqchip
= {
1196 .irq_disable
= gpio_irq_mask
,
1197 .irq_mask
= gpio_irq_mask
,
1198 .irq_unmask
= gpio_irq_unmask
,
1199 .irq_set_type
= gpio_irq_type
,
1202 static void gpio_irq_handler(struct irq_desc
*desc
)
1204 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1205 struct irq_data
*idata
= irq_desc_get_irq_data(desc
);
1206 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(idata
);
1207 void __iomem
*pio
= oxnas_gpio
->regbase
;
1211 chained_irq_enter(chip
, desc
);
1213 /* TODO: see if it works */
1214 isr
= readl_relaxed(pio
+ IRQ_PENDING
);
1217 /* acks pending interrupts */
1218 writel_relaxed(isr
, pio
+ IRQ_PENDING
);
1220 for_each_set_bit(n
, &isr
, BITS_PER_LONG
) {
1221 generic_handle_irq(irq_find_mapping(oxnas_gpio
->domain
,
1225 chained_irq_exit(chip
, desc
);
1226 /* now it may re-trigger */
1230 * This lock class tells lockdep that GPIO irqs are in a different
1231 * category than their parents, so it won't report false recursion.
1233 static struct lock_class_key gpio_lock_class
;
1235 static int oxnas_gpio_irq_map(struct irq_domain
*h
, unsigned int virq
,
1238 struct oxnas_gpio_chip
*oxnas_gpio
= h
->host_data
;
1240 irq_set_lockdep_class(virq
, &gpio_lock_class
);
1242 irq_set_chip_and_handler(virq
, &gpio_irqchip
, handle_edge_irq
);
1243 irq_set_chip_data(virq
, oxnas_gpio
);
1248 static int oxnas_gpio_irq_domain_xlate(struct irq_domain
*d
,
1249 struct device_node
*ctrlr
,
1251 unsigned int intsize
,
1252 irq_hw_number_t
*out_hwirq
,
1253 unsigned int *out_type
)
1255 struct oxnas_gpio_chip
*oxnas_gpio
= d
->host_data
;
1257 int pin
= oxnas_gpio
->chip
.base
+ intspec
[0];
1259 if (WARN_ON(intsize
< 2))
1261 *out_hwirq
= intspec
[0];
1262 *out_type
= intspec
[1] & IRQ_TYPE_SENSE_MASK
;
1264 ret
= gpio_request(pin
, ctrlr
->full_name
);
1268 ret
= gpio_direction_input(pin
);
1275 static struct irq_domain_ops oxnas_gpio_ops
= {
1276 .map
= oxnas_gpio_irq_map
,
1277 .xlate
= oxnas_gpio_irq_domain_xlate
,
1280 static int oxnas_gpio_of_irq_setup(struct device_node
*node
,
1281 struct oxnas_gpio_chip
*oxnas_gpio
,
1284 /* Disable irqs of this controller */
1285 writel_relaxed(0, oxnas_gpio
->regbase
+ RE_IRQ_ENABLE
);
1286 writel_relaxed(0, oxnas_gpio
->regbase
+ FE_IRQ_ENABLE
);
1288 /* Setup irq domain */
1289 oxnas_gpio
->domain
= irq_domain_add_linear(node
, oxnas_gpio
->chip
.ngpio
,
1290 &oxnas_gpio_ops
, oxnas_gpio
);
1291 if (!oxnas_gpio
->domain
)
1292 panic("oxnas_gpio: couldn't allocate irq domain (DT).\n");
1294 irq_set_chip_data(irq
, oxnas_gpio
);
1295 irq_set_chained_handler(irq
, gpio_irq_handler
);
1300 /* This structure is replicated for each GPIO block allocated at probe time */
1301 static struct gpio_chip oxnas_gpio_template
= {
1302 .request
= oxnas_gpio_request
,
1303 .free
= oxnas_gpio_free
,
1304 .direction_input
= oxnas_gpio_direction_input
,
1305 .get
= oxnas_gpio_get
,
1306 .direction_output
= oxnas_gpio_direction_output
,
1307 .set
= oxnas_gpio_set
,
1308 .to_irq
= oxnas_gpio_to_irq
,
1309 .dbg_show
= oxnas_gpio_dbg_show
,
1311 .ngpio
= MAX_NB_GPIO_PER_BANK
,
1314 static struct of_device_id oxnas_gpio_of_match
[] = {
1315 { .compatible
= "plxtech,nas782x-gpio"},
1319 static int oxnas_gpio_probe(struct platform_device
*pdev
)
1321 struct device_node
*np
= pdev
->dev
.of_node
;
1322 struct resource
*res
;
1323 struct oxnas_gpio_chip
*oxnas_chip
= NULL
;
1324 struct gpio_chip
*chip
;
1325 struct pinctrl_gpio_range
*range
;
1328 int alias_idx
= of_alias_get_id(np
, "gpio");
1332 BUG_ON(alias_idx
>= ARRAY_SIZE(gpio_chips
));
1333 if (gpio_chips
[alias_idx
]) {
1338 irq
= platform_get_irq(pdev
, 0);
1344 oxnas_chip
= devm_kzalloc(&pdev
->dev
, sizeof(*oxnas_chip
), GFP_KERNEL
);
1350 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1351 oxnas_chip
->regbase
= devm_ioremap_resource(&pdev
->dev
, res
);
1352 if (IS_ERR(oxnas_chip
->regbase
)) {
1353 ret
= PTR_ERR(oxnas_chip
->regbase
);
1357 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1358 oxnas_chip
->ctrlbase
= devm_ioremap_resource(&pdev
->dev
, res
);
1359 if (IS_ERR(oxnas_chip
->ctrlbase
)) {
1360 ret
= PTR_ERR(oxnas_chip
->ctrlbase
);
1364 oxnas_chip
->chip
= oxnas_gpio_template
;
1366 spin_lock_init(&oxnas_chip
->lock
);
1368 chip
= &oxnas_chip
->chip
;
1370 chip
->label
= dev_name(&pdev
->dev
);
1371 chip
->dev
= &pdev
->dev
;
1372 chip
->owner
= THIS_MODULE
;
1373 chip
->base
= alias_idx
* MAX_NB_GPIO_PER_BANK
;
1375 if (!of_property_read_u32(np
, "#gpio-lines", &ngpio
)) {
1376 if (ngpio
> MAX_NB_GPIO_PER_BANK
)
1377 pr_err("oxnas_gpio.%d, gpio-nb >= %d failback to %d\n",
1378 alias_idx
, MAX_NB_GPIO_PER_BANK
,
1379 MAX_NB_GPIO_PER_BANK
);
1381 chip
->ngpio
= ngpio
;
1384 names
= devm_kzalloc(&pdev
->dev
, sizeof(char *) * chip
->ngpio
,
1392 for (i
= 0; i
< chip
->ngpio
; i
++)
1393 names
[i
] = kasprintf(GFP_KERNEL
, "MF_%c%d", alias_idx
+ 'A', i
);
1395 chip
->names
= (const char *const *)names
;
1397 range
= &oxnas_chip
->range
;
1398 range
->name
= chip
->label
;
1399 range
->id
= alias_idx
;
1400 range
->pin_base
= range
->base
= range
->id
* MAX_NB_GPIO_PER_BANK
;
1402 range
->npins
= chip
->ngpio
;
1405 ret
= gpiochip_add(chip
);
1409 gpio_chips
[alias_idx
] = oxnas_chip
;
1410 gpio_banks
= max(gpio_banks
, alias_idx
+ 1);
1412 oxnas_gpio_of_irq_setup(np
, oxnas_chip
, irq
);
1414 dev_info(&pdev
->dev
, "at address %p\n", oxnas_chip
->regbase
);
1418 dev_err(&pdev
->dev
, "Failure %i for GPIO %i\n", ret
, alias_idx
);
1423 static struct platform_driver oxnas_gpio_driver
= {
1425 .name
= "gpio-oxnas",
1426 .owner
= THIS_MODULE
,
1427 .of_match_table
= of_match_ptr(oxnas_gpio_of_match
),
1429 .probe
= oxnas_gpio_probe
,
1432 static struct platform_driver oxnas_pinctrl_driver
= {
1434 .name
= "pinctrl-oxnas",
1435 .owner
= THIS_MODULE
,
1436 .of_match_table
= of_match_ptr(oxnas_pinctrl_of_match
),
1438 .probe
= oxnas_pinctrl_probe
,
1439 .remove
= oxnas_pinctrl_remove
,
1442 static int __init
oxnas_pinctrl_init(void)
1446 ret
= platform_driver_register(&oxnas_gpio_driver
);
1449 return platform_driver_register(&oxnas_pinctrl_driver
);
1451 arch_initcall(oxnas_pinctrl_init
);
1453 static void __exit
oxnas_pinctrl_exit(void)
1455 platform_driver_unregister(&oxnas_pinctrl_driver
);
1458 module_exit(oxnas_pinctrl_exit
);
1459 MODULE_AUTHOR("Ma Hajun <mahaijuns@gmail.com>");
1460 MODULE_DESCRIPTION("Plxtech Nas782x pinctrl driver");
1461 MODULE_LICENSE("GPL v2");