2 * drivers/usb/host/ehci-oxnas.c
4 * Tzachi Perelstein <tzachi@marvell.com>
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/usb.h>
18 #include <linux/usb/hcd.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/clk.h>
21 #include <linux/reset.h>
22 #include <mach/hardware.h>
23 #include <mach/utils.h>
33 struct reset_control
*rst_host
;
34 struct reset_control
*rst_phya
;
35 struct reset_control
*rst_phyb
;
38 #define DRIVER_DESC "Oxnas On-Chip EHCI Host Controller"
40 static struct hc_driver __read_mostly oxnas_hc_driver
;
42 static void start_oxnas_usb_ehci(struct oxnas_hcd
*oxnas
)
46 if (oxnas
->use_pllb
) {
48 clk_prepare_enable(oxnas
->refsrc
);
50 clk_prepare_enable(oxnas
->phyref
);
51 /* 600MHz pllb divider for 12MHz */
52 writel(PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0),
53 SEC_CTRL_PLLB_DIV_CTRL
);
56 /* ref 300 divider for 12MHz */
57 writel(REF300_DIV_INT(25) | REF300_DIV_FRAC(0),
61 /* Ensure the USB block is properly reset */
62 reset_control_reset(oxnas
->rst_host
);
63 reset_control_reset(oxnas
->rst_phya
);
64 reset_control_reset(oxnas
->rst_phyb
);
66 /* Force the high speed clock to be generated all the time, via serial
67 programming of the USB HS PHY */
68 writel((2UL << USBHSPHY_TEST_ADD
) |
69 (0xe0UL
<< USBHSPHY_TEST_DIN
), SYS_CTRL_USBHSPHY_CTRL
);
71 writel((1UL << USBHSPHY_TEST_CLK
) |
72 (2UL << USBHSPHY_TEST_ADD
) |
73 (0xe0UL
<< USBHSPHY_TEST_DIN
), SYS_CTRL_USBHSPHY_CTRL
);
75 writel((0xfUL
<< USBHSPHY_TEST_ADD
) |
76 (0xaaUL
<< USBHSPHY_TEST_DIN
), SYS_CTRL_USBHSPHY_CTRL
);
78 writel((1UL << USBHSPHY_TEST_CLK
) |
79 (0xfUL
<< USBHSPHY_TEST_ADD
) |
80 (0xaaUL
<< USBHSPHY_TEST_DIN
), SYS_CTRL_USBHSPHY_CTRL
);
82 if (oxnas
->use_pllb
) /* use pllb clock */
83 writel(USB_CLK_INTERNAL
| USB_INT_CLK_PLLB
, SYS_CTRL_USB_CTRL
);
84 else /* use ref300 derived clock */
85 writel(USB_CLK_INTERNAL
| USB_INT_CLK_REF300
,
88 if (oxnas
->use_phya
) {
89 /* Configure USB PHYA as a host */
90 reg
= readl(SYS_CTRL_USB_CTRL
);
91 reg
&= ~USBAMUX_DEVICE
;
92 writel(reg
, SYS_CTRL_USB_CTRL
);
95 /* Enable the clock to the USB block */
96 clk_prepare_enable(oxnas
->clk
);
99 static void stop_oxnas_usb_ehci(struct oxnas_hcd
*oxnas
)
101 reset_control_assert(oxnas
->rst_host
);
102 reset_control_assert(oxnas
->rst_phya
);
103 reset_control_assert(oxnas
->rst_phyb
);
105 if (oxnas
->use_pllb
) {
106 clk_disable_unprepare(oxnas
->phyref
);
107 clk_disable_unprepare(oxnas
->refsrc
);
109 clk_disable_unprepare(oxnas
->clk
);
112 static int ehci_oxnas_reset(struct usb_hcd
*hcd
)
114 #define txttfill_tuning reserved2[0]
116 struct ehci_hcd
*ehci
;
118 int retval
= ehci_setup(hcd
);
122 ehci
= hcd_to_ehci(hcd
);
123 tmp
= ehci_readl(ehci
, &ehci
->regs
->txfill_tuning
);
125 tmp
|= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes) */
126 tmp
|= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/
127 ehci_writel(ehci
, tmp
, &ehci
->regs
->txfill_tuning
);
129 tmp
= ehci_readl(ehci
, &ehci
->regs
->txttfill_tuning
);
130 tmp
|= 0x2; /* set sheduler overhead to 2 * 6.333us */
131 ehci_writel(ehci
, tmp
, &ehci
->regs
->txttfill_tuning
);
136 static int ehci_oxnas_drv_probe(struct platform_device
*ofdev
)
138 struct device_node
*np
= ofdev
->dev
.of_node
;
140 struct ehci_hcd
*ehci
;
142 struct oxnas_hcd
*oxnas
;
144 struct reset_control
*rstc
;
149 if (!ofdev
->dev
.dma_mask
)
150 ofdev
->dev
.dma_mask
= &ofdev
->dev
.coherent_dma_mask
;
151 if (!ofdev
->dev
.coherent_dma_mask
)
152 ofdev
->dev
.coherent_dma_mask
= DMA_BIT_MASK(32);
154 hcd
= usb_create_hcd(&oxnas_hc_driver
, &ofdev
->dev
,
155 dev_name(&ofdev
->dev
));
159 err
= of_address_to_resource(np
, 0, &res
);
163 hcd
->rsrc_start
= res
.start
;
164 hcd
->rsrc_len
= resource_size(&res
);
166 hcd
->regs
= devm_ioremap_resource(&ofdev
->dev
, &res
);
167 if (IS_ERR(hcd
->regs
)) {
168 dev_err(&ofdev
->dev
, "devm_ioremap_resource failed\n");
169 err
= PTR_ERR(hcd
->regs
);
173 oxnas
= (struct oxnas_hcd
*)hcd_to_ehci(hcd
)->priv
;
175 oxnas
->use_pllb
= of_property_read_bool(np
, "plxtech,ehci_use_pllb");
176 oxnas
->use_phya
= of_property_read_bool(np
, "plxtech,ehci_use_phya");
178 oxnas
->clk
= of_clk_get_by_name(np
, "usb");
179 if (IS_ERR(oxnas
->clk
)) {
180 err
= PTR_ERR(oxnas
->clk
);
184 if (oxnas
->use_pllb
) {
185 oxnas
->refsrc
= of_clk_get_by_name(np
, "refsrc");
186 if (IS_ERR(oxnas
->refsrc
)) {
187 err
= PTR_ERR(oxnas
->refsrc
);
190 oxnas
->phyref
= of_clk_get_by_name(np
, "phyref");
191 if (IS_ERR(oxnas
->refsrc
)) {
192 err
= PTR_ERR(oxnas
->refsrc
);
197 oxnas
->refsrc
= NULL
;
198 oxnas
->phyref
= NULL
;
201 rstc
= devm_reset_control_get(&ofdev
->dev
, "host");
206 oxnas
->rst_host
= rstc
;
208 rstc
= devm_reset_control_get(&ofdev
->dev
, "phya");
213 oxnas
->rst_phya
= rstc
;
215 rstc
= devm_reset_control_get(&ofdev
->dev
, "phyb");
220 oxnas
->rst_phyb
= rstc
;
222 irq
= irq_of_parse_and_map(np
, 0);
224 dev_err(&ofdev
->dev
, "irq_of_parse_and_map failed\n");
230 ehci
= hcd_to_ehci(hcd
);
231 ehci
->caps
= hcd
->regs
;
233 start_oxnas_usb_ehci(oxnas
);
235 err
= usb_add_hcd(hcd
, irq
, IRQF_SHARED
);
242 stop_oxnas_usb_ehci(oxnas
);
246 clk_put(oxnas
->phyref
);
249 clk_put(oxnas
->refsrc
);
260 static int ehci_oxnas_drv_remove(struct platform_device
*pdev
)
262 struct usb_hcd
*hcd
= platform_get_drvdata(pdev
);
263 struct oxnas_hcd
*oxnas
= (struct oxnas_hcd
*)hcd_to_ehci(hcd
)->priv
;
266 if (oxnas
->use_pllb
) {
267 clk_disable_unprepare(oxnas
->phyref
);
268 clk_put(oxnas
->phyref
);
269 clk_disable_unprepare(oxnas
->refsrc
);
270 clk_put(oxnas
->refsrc
);
272 clk_disable_unprepare(oxnas
->clk
);
278 static const struct of_device_id oxnas_ehci_dt_ids
[] = {
279 { .compatible
= "plxtech,nas782x-ehci" },
283 MODULE_DEVICE_TABLE(of
, oxnas_ehci_dt_ids
);
285 static struct platform_driver ehci_oxnas_driver
= {
286 .probe
= ehci_oxnas_drv_probe
,
287 .remove
= ehci_oxnas_drv_remove
,
288 .shutdown
= usb_hcd_platform_shutdown
,
289 .driver
.name
= "oxnas-ehci",
290 .driver
.of_match_table
= oxnas_ehci_dt_ids
,
293 static const struct ehci_driver_overrides oxnas_overrides __initconst
= {
294 .reset
= ehci_oxnas_reset
,
295 .extra_priv_size
= sizeof(struct oxnas_hcd
),
298 static int __init
ehci_oxnas_init(void)
303 ehci_init_driver(&oxnas_hc_driver
, &oxnas_overrides
);
304 return platform_driver_register(&ehci_oxnas_driver
);
306 module_init(ehci_oxnas_init
);
308 static void __exit
ehci_oxnas_cleanup(void)
310 platform_driver_unregister(&ehci_oxnas_driver
);
312 module_exit(ehci_oxnas_cleanup
);
314 MODULE_DESCRIPTION(DRIVER_DESC
);
315 MODULE_ALIAS("platform:oxnas-ehci");
316 MODULE_LICENSE("GPL");