2 * PCIe driver for PLX NAS782X SoCs
4 * Author: Ma Haijun <mahaijuns@gmail.com>
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/mbus.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/slab.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_pci.h>
24 #include <linux/of_platform.h>
25 #include <linux/gpio.h>
26 #include <linux/delay.h>
27 #include <linux/clk.h>
28 #include <linux/phy.h>
29 #include <linux/phy/phy.h>
30 #include <linux/regmap.h>
31 #include <linux/reset.h>
33 #include <linux/sizes.h>
37 #define SYS_CTRL_HCSL_CTRL_REGOFFSET 0x114
39 static inline void oxnas_register_clear_mask(void __iomem
*p
, unsigned mask
)
41 u32 val
= readl_relaxed(p
);
44 writel_relaxed(val
, p
);
47 static inline void oxnas_register_set_mask(void __iomem
*p
, unsigned mask
)
49 u32 val
= readl_relaxed(p
);
52 writel_relaxed(val
, p
);
55 static inline void oxnas_register_value_mask(void __iomem
*p
,
56 unsigned mask
, unsigned new_value
)
58 /* TODO sanity check mask & new_value = new_value */
59 u32 val
= readl_relaxed(p
);
63 writel_relaxed(val
, p
);
66 #define VERSION_ID_MAGIC 0x082510b5
67 #define LINK_UP_TIMEOUT_SECONDS 1
68 #define NUM_CONTROLLERS 1
71 PCIE_DEVICE_TYPE_MASK
= 0x0F,
72 PCIE_DEVICE_TYPE_ENDPOINT
= 0,
73 PCIE_DEVICE_TYPE_LEGACY_ENDPOINT
= 1,
74 PCIE_DEVICE_TYPE_ROOT
= 4,
77 PCIE_READY_ENTR_L23
= BIT(9),
78 PCIE_LINK_UP
= BIT(11),
79 PCIE_OBTRANS
= BIT(12),
82 /* core config registers */
84 PCI_CONFIG_VERSION_DEVICEID
= 0,
85 PCI_CONFIG_COMMAND_STATUS
= 4,
88 /* inbound config registers */
90 IB_ADDR_XLATE_ENABLE
= 0xFC,
93 ENABLE_IN_ADDR_TRANS
= BIT(0),
96 /* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */
98 PCIE_POM0_MEM_ADDR
= 0,
99 PCIE_POM1_MEM_ADDR
= 4,
100 PCIE_IN0_MEM_ADDR
= 8,
101 PCIE_IN1_MEM_ADDR
= 12,
102 PCIE_IN_IO_ADDR
= 16,
103 PCIE_IN_CFG0_ADDR
= 20,
104 PCIE_IN_CFG1_ADDR
= 24,
105 PCIE_IN_MSG_ADDR
= 28,
106 PCIE_IN0_MEM_LIMIT
= 32,
107 PCIE_IN1_MEM_LIMIT
= 36,
108 PCIE_IN_IO_LIMIT
= 40,
109 PCIE_IN_CFG0_LIMIT
= 44,
110 PCIE_IN_CFG1_LIMIT
= 48,
111 PCIE_IN_MSG_LIMIT
= 52,
112 PCIE_AHB_SLAVE_CTRL
= 56,
114 PCIE_SLAVE_BE_SHIFT
= 22,
117 #define PCIE_SLAVE_BE(val) ((val) << PCIE_SLAVE_BE_SHIFT)
118 #define PCIE_SLAVE_BE_MASK PCIE_SLAVE_BE(0xF)
120 struct oxnas_pcie_shared
{
121 /* seems all access are serialized, no lock required */
125 /* Structure representing one PCIe interfaces */
127 void __iomem
*cfgbase
;
129 void __iomem
*inbound
;
130 struct regmap
*sys_ctrl
;
131 unsigned int outbound_offset
;
132 unsigned int pcie_ctrl_offset
;
135 struct platform_device
*pdev
;
138 struct resource pre_mem
; /* prefetchable */
139 struct resource non_mem
; /* non-prefetchable */
140 struct resource busn
; /* max available bus numbers */
141 int card_reset
; /* gpio pin, optional */
142 unsigned hcsl_en
; /* hcsl pci enable bit */
144 struct clk
*busclk
; /* for pcie bus, actually the PLLB */
145 void *private_data
[1];
149 static struct oxnas_pcie_shared pcie_shared
= {
153 static inline struct oxnas_pcie
*sys_to_pcie(struct pci_sys_data
*sys
)
155 return sys
->private_data
;
159 static inline void set_out_lanes(struct oxnas_pcie
*pcie
, unsigned lanes
)
161 regmap_update_bits(pcie
->sys_ctrl
, pcie
->outbound_offset
+ PCIE_AHB_SLAVE_CTRL
,
162 PCIE_SLAVE_BE_MASK
, PCIE_SLAVE_BE(lanes
));
166 static int oxnas_pcie_link_up(struct oxnas_pcie
*pcie
)
171 /* Poll for PCIE link up */
172 end
= jiffies
+ (LINK_UP_TIMEOUT_SECONDS
* HZ
);
173 while (!time_after(jiffies
, end
)) {
174 regmap_read(pcie
->sys_ctrl
, pcie
->pcie_ctrl_offset
, &val
);
175 if (val
& PCIE_LINK_UP
)
181 static void oxnas_pcie_setup_hw(struct oxnas_pcie
*pcie
)
183 /* We won't have any inbound address translation. This allows PCI
184 * devices to access anywhere in the AHB address map. Might be regarded
185 * as a bit dangerous, but let's get things working before we worry
188 oxnas_register_clear_mask(pcie
->inbound
+ IB_ADDR_XLATE_ENABLE
,
189 ENABLE_IN_ADDR_TRANS
);
193 * Program outbound translation windows
195 * Outbound window is what is referred to as "PCI client" region in HRM
197 * Could use the larger alternative address space to get >>64M regions
198 * for graphics cards etc., but will not bother at this point.
200 * IP bug means that AMBA window size must be a power of 2
202 * Set mem0 window for first 16MB of outbound window non-prefetchable
203 * Set mem1 window for second 16MB of outbound window prefetchable
204 * Set io window for next 16MB of outbound window
205 * Set cfg0 for final 1MB of outbound window
207 * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for
208 * 820 that would need them
210 * Probably ideally want no offset between mem0 window start as seen by
211 * ARM and as seen on PCI bus and get Linux to assign memory regions to
212 * PCI devices using the same "PCI client" region start address as seen
216 /* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */
217 regmap_write(pcie
->sys_ctrl
, pcie
->outbound_offset
+ PCIE_IN0_MEM_ADDR
, pcie
->non_mem
.start
);
218 regmap_write(pcie
->sys_ctrl
, pcie
->outbound_offset
+ PCIE_IN0_MEM_LIMIT
, pcie
->non_mem
.end
);
219 regmap_write(pcie
->sys_ctrl
, pcie
->outbound_offset
+ PCIE_POM0_MEM_ADDR
, pcie
->non_mem
.start
);
221 /* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */
222 regmap_write(pcie
->sys_ctrl
, pcie
->outbound_offset
+ PCIE_IN1_MEM_ADDR
, pcie
->pre_mem
.start
);
223 regmap_write(pcie
->sys_ctrl
, pcie
->outbound_offset
+ PCIE_IN1_MEM_LIMIT
, pcie
->pre_mem
.end
);
224 regmap_write(pcie
->sys_ctrl
, pcie
->outbound_offset
+ PCIE_POM1_MEM_ADDR
, pcie
->pre_mem
.start
);
226 /* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/
227 regmap_write(pcie
->sys_ctrl
, pcie
->outbound_offset
+ PCIE_IN_IO_ADDR
, pcie
->io
.start
);
228 regmap_write(pcie
->sys_ctrl
, pcie
->outbound_offset
+ PCIE_IN_IO_LIMIT
, pcie
->io
.end
);
231 /* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/
232 regmap_write(pcie
->sys_ctrl
, pcie
->outbound_offset
+ PCIE_IN_CFG0_ADDR
, pcie
->cfg
.start
);
233 regmap_write(pcie
->sys_ctrl
, pcie
->outbound_offset
+ PCIE_IN_CFG0_LIMIT
, pcie
->cfg
.end
);
236 /* Enable outbound address translation */
237 regmap_write_bits(pcie
->sys_ctrl
, pcie
->pcie_ctrl_offset
, PCIE_OBTRANS
, PCIE_OBTRANS
);
241 * Program PCIe command register for core to:
242 * enable memory space
246 writel_relaxed(7, pcie
->base
+ PCI_CONFIG_COMMAND_STATUS
);
251 static unsigned oxnas_pcie_cfg_to_offset(
252 struct pci_sys_data
*sys
,
253 unsigned char bus_number
,
257 unsigned int function
= PCI_FUNC(devfn
);
258 unsigned int slot
= PCI_SLOT(devfn
);
259 unsigned char bus_number_offset
;
261 bus_number_offset
= bus_number
- sys
->busnr
;
264 * We'll assume for now that the offset, function, slot, bus encoding
265 * should map onto linear, contiguous addresses in PCIe config space,
266 * albeit that the majority will be unused as only slot 0 is valid for
267 * any PCIe bus and most devices have only function 0
269 * Could be that PCIe in fact works by not encoding the slot number into
270 * the config space address as it's known that only slot 0 is valid.
271 * We'll have to experiment if/when we get a PCIe switch connected to
274 return (bus_number_offset
<< 20) | (slot
<< 15) | (function
<< 12) |
278 /* PCI configuration space write function */
279 static int oxnas_pcie_wr_conf(struct pci_bus
*bus
, u32 devfn
,
280 int where
, int size
, u32 val
)
283 struct oxnas_pcie
*pcie
= sys_to_pcie(bus
->sysdata
);
288 /* Only a single device per bus for PCIe point-to-point links */
289 if (PCI_SLOT(devfn
) > 0)
290 return PCIBIOS_DEVICE_NOT_FOUND
;
293 return PCIBIOS_DEVICE_NOT_FOUND
;
295 offset
= oxnas_pcie_cfg_to_offset(bus
->sysdata
, bus
->number
, devfn
,
298 value
= val
<< (8 * (where
& 3));
299 lanes
= (0xf >> (4-size
)) << (where
& 3);
300 /* it race with mem and io write, but the possibility is low, normally
301 * all config writes happens at driver initialize stage, wont interleave
303 * and many pcie cards use dword (4bytes) access mem/io access only,
304 * so not bother to copy that ugly work-around now. */
305 spin_lock_irqsave(&pcie
->lock
, flags
);
306 set_out_lanes(pcie
, lanes
);
307 writel_relaxed(value
, pcie
->cfgbase
+ offset
);
308 set_out_lanes(pcie
, 0xf);
309 spin_unlock_irqrestore(&pcie
->lock
, flags
);
311 return PCIBIOS_SUCCESSFUL
;
314 /* PCI configuration space read function */
315 static int oxnas_pcie_rd_conf(struct pci_bus
*bus
, u32 devfn
, int where
,
318 struct oxnas_pcie
*pcie
= sys_to_pcie(bus
->sysdata
);
321 u32 left_bytes
, right_bytes
;
323 /* Only a single device per bus for PCIe point-to-point links */
324 if (PCI_SLOT(devfn
) > 0) {
326 return PCIBIOS_DEVICE_NOT_FOUND
;
329 if (!pcie
->haslink
) {
331 return PCIBIOS_DEVICE_NOT_FOUND
;
334 offset
= oxnas_pcie_cfg_to_offset(bus
->sysdata
, bus
->number
, devfn
,
336 value
= readl_relaxed(pcie
->cfgbase
+ offset
);
337 left_bytes
= where
& 3;
338 right_bytes
= 4 - left_bytes
- size
;
339 value
<<= right_bytes
* 8;
340 value
>>= (left_bytes
+ right_bytes
) * 8;
343 return PCIBIOS_SUCCESSFUL
;
346 static struct pci_ops oxnas_pcie_ops
= {
347 .read
= oxnas_pcie_rd_conf
,
348 .write
= oxnas_pcie_wr_conf
,
351 static int oxnas_pcie_setup(int nr
, struct pci_sys_data
*sys
)
353 struct oxnas_pcie
*pcie
= sys_to_pcie(sys
);
355 pci_add_resource_offset(&sys
->resources
, &pcie
->non_mem
, sys
->mem_offset
);
356 pci_add_resource_offset(&sys
->resources
, &pcie
->pre_mem
, sys
->mem_offset
);
357 pci_add_resource_offset(&sys
->resources
, &pcie
->io
, sys
->io_offset
);
358 pci_add_resource(&sys
->resources
, &pcie
->busn
);
359 if (sys
->busnr
== 0) { /* default one */
360 sys
->busnr
= pcie
->busn
.start
;
362 /* do not use devm_ioremap_resource, it does not like cfg resource */
363 pcie
->cfgbase
= devm_ioremap(&pcie
->pdev
->dev
, pcie
->cfg
.start
,
364 resource_size(&pcie
->cfg
));
368 oxnas_pcie_setup_hw(pcie
);
373 static void oxnas_pcie_enable(struct device
*dev
, struct oxnas_pcie
*pcie
)
378 memset(&hw
, 0, sizeof(hw
));
379 for (i
= 0; i
< NUM_CONTROLLERS
; i
++)
380 pcie
->private_data
[i
] = pcie
;
382 hw
.nr_controllers
= NUM_CONTROLLERS
;
383 /* I think use stack pointer is a bad idea though it is valid in this case */
384 hw
.private_data
= pcie
->private_data
;
385 hw
.setup
= oxnas_pcie_setup
;
386 hw
.map_irq
= of_irq_parse_and_map_pci
;
387 hw
.ops
= &oxnas_pcie_ops
;
389 /* pass dev to maintain of tree, interrupt mapping rely on this */
390 pci_common_init_dev(dev
, &hw
);
393 static int oxnas_pcie_shared_init(struct platform_device
*pdev
, struct oxnas_pcie
*pcie
)
395 if (++pcie_shared
.refcount
== 1) {
397 phy_power_on(pcie
->phy
);
405 /* maybe we will call it when enter low power state */
406 static void oxnas_pcie_shared_deinit(struct platform_device
*pdev
)
408 if (--pcie_shared
.refcount
== 0) {
409 /* no cleanup needed */;
415 oxnas_pcie_map_registers(struct platform_device
*pdev
,
416 struct device_node
*np
,
417 struct oxnas_pcie
*pcie
)
419 struct resource regs
;
421 u32 outbound_ctrl_offset
;
422 u32 pcie_ctrl_offset
;
424 ret
= of_address_to_resource(np
, 0, ®s
);
426 dev_err(&pdev
->dev
, "failed to parse base register space\n");
430 pcie
->base
= devm_ioremap_resource(&pdev
->dev
, ®s
);
432 dev_err(&pdev
->dev
, "failed to map base register space\n");
436 ret
= of_address_to_resource(np
, 1, ®s
);
438 dev_err(&pdev
->dev
, "failed to parse inbound register space\n");
442 pcie
->inbound
= devm_ioremap_resource(&pdev
->dev
, ®s
);
443 if (!pcie
->inbound
) {
444 dev_err(&pdev
->dev
, "failed to map inbound register space\n");
448 pcie
->phy
= devm_of_phy_get(&pdev
->dev
, np
, NULL
);
449 if (IS_ERR(pcie
->phy
)) {
450 if (PTR_ERR(pcie
->phy
) == -EPROBE_DEFER
) {
451 dev_err(&pdev
->dev
, "failed to probe phy\n");
452 return PTR_ERR(pcie
->phy
);
454 dev_warn(&pdev
->dev
, "phy not attached\n");
458 if (of_property_read_u32(np
, "plxtech,pcie-outbound-offset",
459 &outbound_ctrl_offset
)) {
460 dev_err(&pdev
->dev
, "failed to parse outbound register offset\n");
463 pcie
->outbound_offset
= outbound_ctrl_offset
;
465 if (of_property_read_u32(np
, "plxtech,pcie-ctrl-offset",
466 &pcie_ctrl_offset
)) {
467 dev_err(&pdev
->dev
, "failed to parse pcie-ctrl register offset\n");
470 pcie
->pcie_ctrl_offset
= pcie_ctrl_offset
;
475 static int oxnas_pcie_init_res(struct platform_device
*pdev
,
476 struct oxnas_pcie
*pcie
,
477 struct device_node
*np
)
479 struct of_pci_range range
;
480 struct of_pci_range_parser parser
;
483 if (of_pci_range_parser_init(&parser
, np
))
486 /* Get the I/O and memory ranges from DT */
487 for_each_of_pci_range(&parser
, &range
) {
489 unsigned long restype
= range
.flags
& IORESOURCE_TYPE_BITS
;
490 if (restype
== IORESOURCE_IO
) {
491 of_pci_range_to_resource(&range
, np
, &pcie
->io
);
492 pcie
->io
.name
= "I/O";
494 if (restype
== IORESOURCE_MEM
) {
495 if (range
.flags
& IORESOURCE_PREFETCH
) {
496 of_pci_range_to_resource(&range
, np
, &pcie
->pre_mem
);
497 pcie
->pre_mem
.name
= "PRE MEM";
499 of_pci_range_to_resource(&range
, np
, &pcie
->non_mem
);
500 pcie
->non_mem
.name
= "NON MEM";
505 of_pci_range_to_resource(&range
, np
, &pcie
->cfg
);
508 /* Get the bus range */
509 ret
= of_pci_parse_bus_range(np
, &pcie
->busn
);
512 dev_err(&pdev
->dev
, "failed to parse bus-range property: %d\n",
517 pcie
->card_reset
= of_get_gpio(np
, 0);
518 if (pcie
->card_reset
< 0)
519 dev_info(&pdev
->dev
, "card reset gpio pin not exists\n");
521 if (of_property_read_u32(np
, "plxtech,pcie-hcsl-bit", &pcie
->hcsl_en
))
524 pcie
->clk
= of_clk_get_by_name(np
, "pcie");
525 if (IS_ERR(pcie
->clk
)) {
526 return PTR_ERR(pcie
->clk
);
529 pcie
->busclk
= of_clk_get_by_name(np
, "busclk");
530 if (IS_ERR(pcie
->busclk
)) {
532 return PTR_ERR(pcie
->busclk
);
538 static void oxnas_pcie_init_hw(struct platform_device
*pdev
,
539 struct oxnas_pcie
*pcie
)
544 clk_prepare_enable(pcie
->busclk
);
546 /* reset PCIe cards use hard-wired gpio pin */
547 if (pcie
->card_reset
>= 0 &&
548 !gpio_direction_output(pcie
->card_reset
, 0)) {
551 /* must tri-state the pin to pull it up */
552 gpio_direction_input(pcie
->card_reset
);
557 /* ToDo: use phy power-on port... */
558 regmap_update_bits(pcie
->sys_ctrl
, SYS_CTRL_HCSL_CTRL_REGOFFSET
,
559 BIT(pcie
->hcsl_en
), BIT(pcie
->hcsl_en
));
562 ret
= device_reset(&pdev
->dev
);
564 dev_err(&pdev
->dev
, "core reset failed %d\n", ret
);
568 /* Start PCIe core clocks */
569 clk_prepare_enable(pcie
->clk
);
571 version_id
= readl_relaxed(pcie
->base
+ PCI_CONFIG_VERSION_DEVICEID
);
572 dev_info(&pdev
->dev
, "PCIe version/deviceID 0x%x\n", version_id
);
574 if (version_id
!= VERSION_ID_MAGIC
) {
575 dev_info(&pdev
->dev
, "PCIe controller not found\n");
580 /* allow entry to L23 state */
581 regmap_write_bits(pcie
->sys_ctrl
, pcie
->pcie_ctrl_offset
,
582 PCIE_READY_ENTR_L23
, PCIE_READY_ENTR_L23
);
584 /* Set PCIe core into RootCore mode */
585 regmap_write_bits(pcie
->sys_ctrl
, pcie
->pcie_ctrl_offset
,
586 PCIE_DEVICE_TYPE_MASK
, PCIE_DEVICE_TYPE_ROOT
);
589 /* Bring up the PCI core */
590 regmap_write_bits(pcie
->sys_ctrl
, pcie
->pcie_ctrl_offset
,
591 PCIE_LTSSM
, PCIE_LTSSM
);
595 static int oxnas_pcie_probe(struct platform_device
*pdev
)
597 struct oxnas_pcie
*pcie
;
598 struct device_node
*np
= pdev
->dev
.of_node
;
601 pcie
= devm_kzalloc(&pdev
->dev
, sizeof(struct oxnas_pcie
),
608 spin_lock_init(&pcie
->lock
);
610 pcie
->sys_ctrl
= syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
611 if (IS_ERR(pcie
->sys_ctrl
))
612 return PTR_ERR(pcie
->sys_ctrl
);
614 ret
= oxnas_pcie_init_res(pdev
, pcie
, np
);
617 if (pcie
->card_reset
>= 0) {
618 ret
= gpio_request_one(pcie
->card_reset
, GPIOF_DIR_IN
,
619 dev_name(&pdev
->dev
));
621 dev_err(&pdev
->dev
, "cannot request gpio pin %d\n",
627 ret
= oxnas_pcie_map_registers(pdev
, np
, pcie
);
629 dev_err(&pdev
->dev
, "cannot map registers\n");
633 ret
= oxnas_pcie_shared_init(pdev
, pcie
);
637 /* if hw not found, haslink cleared */
638 oxnas_pcie_init_hw(pdev
, pcie
);
640 if (pcie
->haslink
&& oxnas_pcie_link_up(pcie
)) {
642 dev_info(&pdev
->dev
, "link up\n");
645 dev_info(&pdev
->dev
, "link down\n");
647 /* should we register our controller even when pcie->haslink is 0 ? */
648 /* register the controller with framework */
649 oxnas_pcie_enable(&pdev
->dev
, pcie
);
654 if (pcie
->card_reset
)
655 gpio_free(pcie
->card_reset
);
660 static const struct of_device_id oxnas_pcie_of_match_table
[] = {
661 { .compatible
= "plxtech,nas782x-pcie", },
665 static struct platform_driver oxnas_pcie_driver
= {
667 .name
= "oxnas-pcie",
668 .suppress_bind_attrs
= true,
669 .of_match_table
= oxnas_pcie_of_match_table
,
671 .probe
= oxnas_pcie_probe
,
674 builtin_platform_driver(oxnas_pcie_driver
);