6 compatible = "ralink,mt7620a-soc";
19 compatible = "mips,mips24KEc";
25 bootargs = "console=ttyS0,57600";
30 #interrupt-cells = <1>;
32 compatible = "mti,cpu-interrupt-controller";
35 palmbus: palmbus@10000000 {
36 compatible = "palmbus";
37 reg = <0x10000000 0x200000>;
38 ranges = <0x0 0x10000000 0x1FFFFF>;
44 compatible = "ralink,mt7620-sysc", "syscon";
51 compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
56 interrupt-parent = <&intc>;
60 watchdog: watchdog@120 {
61 compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
69 interrupt-parent = <&intc>;
74 compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
81 #interrupt-cells = <1>;
83 interrupt-parent = <&cpuintc>;
88 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
94 interrupt-parent = <&intc>;
99 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
106 interrupt-parent = <&intc>;
115 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
121 interrupt-parent = <&intc>;
128 ralink,gpio-base = <0>;
129 ralink,register-map = [ 00 04 08 0c
135 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
138 interrupt-parent = <&intc>;
145 ralink,gpio-base = <24>;
146 ralink,register-map = [ 00 04 08 0c
154 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
157 interrupt-parent = <&intc>;
164 ralink,gpio-base = <40>;
165 ralink,register-map = [ 00 04 08 0c
173 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
176 interrupt-parent = <&intc>;
183 ralink,gpio-base = <72>;
184 ralink,register-map = [ 00 04 08 0c
192 compatible = "ralink,rt2880-i2c";
200 #address-cells = <1>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&i2c_pins>;
210 compatible = "mediatek,mt7620-i2s";
218 interrupt-parent = <&intc>;
226 dma-names = "tx", "rx";
232 compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
240 #address-cells = <1>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&spi_pins>;
250 compatible = "ralink,rt2880-spi";
258 #address-cells = <1>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&spi_cs1>;
267 uartlite: uartlite@c00 {
268 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
275 interrupt-parent = <&intc>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&uartlite_pins>;
284 systick: systick@d00 {
285 compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
289 reset-names = "intc";
291 interrupt-parent = <&cpuintc>;
296 compatible = "ralink,mt7620a-pcm";
297 reg = <0x2000 0x800>;
302 interrupt-parent = <&intc>;
309 compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma";
310 reg = <0x2800 0x800>;
315 interrupt-parent = <&intc>;
319 #dma-channels = <16>;
320 #dma-requests = <16>;
327 compatible = "ralink,rt2880-pinmux";
328 pinctrl-names = "default";
329 pinctrl-0 = <&state_default>;
331 state_default: pinctrl0 {
334 pcm_i2s_pins: pcm_i2s {
337 function = "pcm i2s";
341 uartf_gpio_pins: uartf_gpio {
344 function = "gpio uartf";
348 gpio_i2s_pins: gpio_i2s {
351 function = "gpio i2s";
364 groups = "spi refclk";
365 function = "spi refclk";
376 uartlite_pins: uartlite {
379 function = "uartlite";
390 mdio_refclk_pins: mdio_refclk {
411 rgmii1_pins: rgmii1 {
418 rgmii2_pins: rgmii2 {
428 function = "pcie rst";
439 pa_gpio_pins: pa_gpio {
455 compatible = "mediatek,mt7620-usbphy";
458 ralink,sysctl = <&sysc>;
459 /* usb phy reset is only controled by RSTCTRL bit 25 */
460 resets = <&sysc 25>, <&sysc 22>;
461 reset-names = "host", "device";
464 ethernet: ethernet@10100000 {
465 compatible = "mediatek,mt7620-eth";
466 reg = <0x10100000 0x10000>;
468 #address-cells = <1>;
471 interrupt-parent = <&cpuintc>;
474 resets = <&sysc 21>, <&sysc 23>;
475 reset-names = "fe", "esw";
477 mediatek,switch = <&gsw>;
480 compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
487 compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
494 #address-cells = <1>;
502 compatible = "mediatek,mt7620-gsw";
503 reg = <0x10110000 0x8000>;
508 interrupt-parent = <&intc>;
512 sdhci: sdhci@10130000 {
513 compatible = "ralink,mt7620-sdhci";
514 reg = <0x10130000 0x4000>;
516 interrupt-parent = <&intc>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&sdhci_pins>;
525 ehci: ehci@101c0000 {
526 #address-cells = <1>;
528 compatible = "generic-ehci";
529 reg = <0x101c0000 0x1000>;
531 interrupt-parent = <&intc>;
541 #trigger-source-cells = <0>;
545 ohci: ohci@101c1000 {
546 #address-cells = <1>;
548 compatible = "generic-ohci";
549 reg = <0x101c1000 0x1000>;
551 interrupt-parent = <&intc>;
561 #trigger-source-cells = <0>;
565 pcie: pcie@10140000 {
566 compatible = "mediatek,mt7620-pci";
567 reg = <0x10140000 0x100
570 #address-cells = <3>;
574 reset-names = "pcie0";
576 interrupt-parent = <&cpuintc>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&pcie_pins>;
586 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
587 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
593 reg = <0x0000 0 0 0 0>;
595 #address-cells = <3>;
604 wmac: wmac@10180000 {
605 compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
606 reg = <0x10180000 0x40000>;
610 interrupt-parent = <&cpuintc>;
613 ralink,eeprom = "soc_wmac.eeprom";