1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "mt7620a.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/mtd/partitions/uimage.h>
11 compatible = "edimax,ew-7478apc", "ralink,mt7620a-soc";
12 model = "Edimax EW-7478APC";
15 led-boot = &led_power;
16 led-failsafe = &led_power;
17 led-running = &led_power;
18 led-upgrade = &led_power;
22 compatible = "gpio-keys";
26 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
27 linux,code = <KEY_RESTART>;
32 compatible = "gpio-leds";
35 function = LED_FUNCTION_POWER;
36 color = <LED_COLOR_ID_WHITE>;
37 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
41 label = "blue:internet";
42 gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
46 function = LED_FUNCTION_WLAN;
47 color = <LED_COLOR_ID_BLUE>;
48 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
52 function = LED_FUNCTION_USB;
53 color = <LED_COLOR_ID_BLUE>;
54 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
55 trigger-sources = <&ohci_port1>, <&ehci_port1>;
56 linux,default-trigger = "usbport";
66 line-name = "enable USB power";
67 gpios = <5 GPIO_ACTIVE_HIGH>;
76 compatible = "jedec,spi-nor";
78 spi-max-frequency = <10000000>;
81 compatible = "fixed-partitions";
93 reg = <0x30000 0x10000>;
99 reg = <0x40000 0x10000>;
103 compatible = "fixed-layout";
104 #address-cells = <1>;
107 eeprom_factory_0: eeprom@0 {
111 eeprom_factory_8000: eeprom@8000 {
112 reg = <0x8000 0x200>;
115 macaddr_factory_4: macaddr@4 {
123 reg = <0x50000 0x20000>;
128 compatible = "openwrt,uimage", "denx,uimage";
129 openwrt,offset = <FW_EDIMAX_OFFSET>;
130 openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
132 reg = <0x00070000 0x00790000>;
140 groups = "i2c", "uartf", "nd_sd";
146 pinctrl-names = "default";
147 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
149 nvmem-cells = <&macaddr_factory_4>;
150 nvmem-cell-names = "mac-address";
152 mediatek,portmap = "wllll";
156 mediatek,fixed-link = <1000 1 1 1>;
163 phy0: ethernet-phy@0 {
168 phy1: ethernet-phy@1 {
173 phy2: ethernet-phy@2 {
178 phy3: ethernet-phy@3 {
183 phy4: ethernet-phy@4 {
188 phy1f: ethernet-phy@1f {
196 mediatek,ephy-base = /bits/ 8 <12>;
200 nvmem-cells = <&eeprom_factory_0>;
201 nvmem-cell-names = "eeprom";
210 reg = <0x0000 0 0 0 0>;
211 nvmem-cells = <&eeprom_factory_8000>;
212 nvmem-cell-names = "eeprom";
213 ieee80211-freq-limit = <5000000 6000000>;