1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include "mt7620a.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
10 compatible = "head-weblink,hdrm200", "ralink,mt7620a-soc";
11 model = "Head Weblink HDRM200";
14 led-boot = &led_system;
15 led-failsafe = &led_system;
16 led-running = &led_system;
17 led-upgrade = &led_system;
21 bootargs = "console=ttyS1,57600";
25 compatible = "gpio-leds";
28 label = "hdrm200:red:rssi";
29 gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
33 label = "hdrm200:green:system";
34 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
38 label = "hdrm200:green:wifi";
39 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
44 compatible = "gpio-keys";
48 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
49 linux,code = <KEY_WPS_BUTTON>;
54 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
55 linux,code = <KEY_RESTART>;
64 compatible = "jedec,spi-nor";
66 spi-max-frequency = <10000000>;
69 compatible = "fixed-partitions";
81 reg = <0x30000 0x10000>;
85 factory: partition@40000 {
87 reg = <0x40000 0x10000>;
91 firmware: partition@50000 {
92 compatible = "denx,uimage";
94 reg = <0x50000 0xfb0000>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
128 mtd-mac-address = <&factory 0x4>;
132 phy-handle = <&phy4>;
138 phy-handle = <&phy5>;
145 phy4: ethernet-phy@4 {
150 phy5: ethernet-phy@5 {
158 ralink,mtd-eeprom = <&factory 0x0>;
163 groups = "i2c", "uartf", "pa", "spi refclk",
175 compatible = "mediatek,mt76";
176 reg = <0x0000 0 0 0 0>;
177 mediatek,mtd-eeprom = <&factory 0x8000>;
178 ieee80211-freq-limit = <5000000 6000000>;