ramips: mt7620: use DTS to set PHY base address for external PHYs
[openwrt/openwrt.git] / target / linux / ramips / dts / mt7620a_lava_lr-25g001.dts
1 #include "mt7620a.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 / {
7 compatible = "lava,lr-25g001", "ralink,mt7620a-soc";
8 model = "LAVA LR-25G001";
9
10 aliases {
11 led-boot = &led_status;
12 led-failsafe = &led_status;
13 led-running = &led_status;
14 led-upgrade = &led_status;
15 };
16
17 keys {
18 compatible = "gpio-keys";
19
20 wps {
21 label = "wps";
22 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
23 linux,code = <KEY_WPS_BUTTON>;
24 };
25
26 reset {
27 label = "reset";
28 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
29 linux,code = <KEY_RESTART>;
30 };
31 };
32
33 leds {
34 compatible = "gpio-leds";
35
36 led_status: status {
37 label = "green:status";
38 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
39 };
40
41 wifi2g {
42 label = "green:wifi2g";
43 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
44 };
45
46 wifi5g {
47 label = "green:wifi5g";
48 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
49 };
50 };
51
52 gpio_export {
53 compatible = "gpio-export";
54 #size-cells = <0>;
55
56 usbpower {
57 gpio-export,name = "usbpower";
58 gpio-export,output = <1>;
59 gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
60 };
61 };
62 };
63
64 &spi0 {
65 status = "okay";
66
67 flash@0 {
68 compatible = "jedec,spi-nor";
69 reg = <0>;
70 spi-max-frequency = <10000000>;
71
72 partitions {
73 compatible = "fixed-partitions";
74 #address-cells = <1>;
75 #size-cells = <1>;
76
77 partition@0 {
78 label = "jboot";
79 reg = <0x0 0x10000>;
80 read-only;
81 };
82
83 partition@10000 {
84 compatible = "amit,jimage";
85 label = "firmware";
86 reg = <0x10000 0xfe0000>;
87 };
88
89 config: partition@ff0000 {
90 label = "config";
91 reg = <0xff0000 0x10000>;
92 read-only;
93 };
94 };
95 };
96 };
97
98 &ehci {
99 status = "okay";
100 };
101
102 &ohci {
103 status = "okay";
104 };
105
106 &ethernet {
107 pinctrl-names = "default";
108 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
109
110 port@5 {
111 status = "okay";
112 phy-mode = "rgmii";
113 mediatek,fixed-link = <1000 1 1 1>;
114 };
115
116 mdio-bus {
117 status = "okay";
118 mediatek,mdio-mode = <1>;
119
120 phy0: ethernet-phy@0 {
121 reg = <0>;
122 phy-mode = "rgmii";
123 qca,ar8327-initvals = <
124 0x04 0x87300000 /* PORT0 PAD MODE CTRL */
125 0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
126 0x7c 0x0000007e /* PORT0_STATUS */
127 0x94 0x00000000 /* PORT6_STATUS */
128 >;
129 };
130
131 phy1: ethernet-phy@1 {
132 reg = <1>;
133 phy-mode = "rgmii";
134 };
135
136 phy2: ethernet-phy@2 {
137 reg = <2>;
138 phy-mode = "rgmii";
139 };
140
141 phy3: ethernet-phy@3 {
142 reg = <3>;
143 phy-mode = "rgmii";
144 };
145
146 phy4: ethernet-phy@4 {
147 reg = <4>;
148 phy-mode = "rgmii";
149 };
150 };
151 };
152
153 &gsw {
154 mediatek,ephy-base = /bits/ 8 <8>;
155 };
156
157 &pcie {
158 status = "okay";
159 };
160
161 &pcie0 {
162 mt76x0e@0,0 {
163 reg = <0x0000 0 0 0 0>;
164 mtd-mac-address = <&config 0xe07e>;
165 mtd-mac-address-increment = <(2)>;
166 mediatek,mtd-eeprom = <&config 0xe08a>;
167 };
168 };
169
170 &state_default {
171 gpio {
172 groups = "uartf", "i2c";
173 function = "gpio";
174 };
175 };