3 #include <dt-bindings/clock/mt7621-clk.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/mips-gic.h>
6 #include <dt-bindings/reset/mt7621-reset.h>
11 compatible = "mediatek,mt7621-soc";
23 compatible = "mips,mips1004Kc";
29 compatible = "mips,mips1004Kc";
36 #interrupt-cells = <1>;
38 compatible = "mti,cpu-interrupt-controller";
42 bootargs = "console=ttyS0,57600";
45 palmbus: palmbus@1e000000 {
46 compatible = "palmbus";
47 reg = <0x1e000000 0x100000>;
48 ranges = <0x0 0x1e000000 0x0fffff>;
54 compatible = "mediatek,mt7621-sysc", "syscon";
57 ralink,memctl = <&memc>;
58 clock-output-names = "xtal", "cpu", "bus",
59 "50m", "125m", "150m",
65 compatible = "mediatek,mt7621-wdt";
67 mediatek,sysctl = <&sysc>;
72 #interrupt-cells = <2>;
73 compatible = "mediatek,mt7621-gpio";
75 gpio-ranges = <&pinctrl 0 0 95>;
78 interrupt-parent = <&gic>;
79 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
83 compatible = "mediatek,mt7621-i2c";
86 clocks = <&sysc MT7621_CLK_I2C>;
89 resets = <&sysc MT7621_RST_I2C>;
97 pinctrl-names = "default";
98 pinctrl-0 = <&i2c_pins>;
102 compatible = "mediatek,mt7621-i2s";
105 clocks = <&sysc MT7621_CLK_I2S>;
107 resets = <&sysc MT7621_RST_I2S>;
110 interrupt-parent = <&gic>;
111 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
118 dma-names = "tx", "rx";
123 memc: memory-controller@5000 {
124 compatible = "mediatek,mt7621-memc", "syscon";
125 reg = <0x5000 0x1000>;
128 uartlite: uartlite@c00 {
129 compatible = "ns16550a";
132 clocks = <&sysc MT7621_CLK_UART1>;
134 resets = <&sysc MT7621_RST_UART1>;
136 interrupt-parent = <&gic>;
137 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
144 uartlite2: uartlite2@d00 {
145 compatible = "ns16550a";
148 clocks = <&sysc MT7621_CLK_UART2>;
150 resets = <&sysc MT7621_RST_UART2>;
152 interrupt-parent = <&gic>;
153 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&uart2_pins>;
164 uartlite3: uartlite3@e00 {
165 compatible = "ns16550a";
168 clocks = <&sysc MT7621_CLK_UART3>;
170 resets = <&sysc MT7621_RST_UART3>;
172 interrupt-parent = <&gic>;
173 interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&uart3_pins>;
187 compatible = "ralink,mt7621-spi";
190 clocks = <&sysc MT7621_CLK_SPI>;
193 resets = <&sysc MT7621_RST_SPI>;
196 #address-cells = <1>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&spi_pins>;
204 compatible = "ralink,rt3883-gdma";
205 reg = <0x2800 0x800>;
207 resets = <&sysc MT7621_RST_GDMA>;
210 interrupt-parent = <&gic>;
211 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
214 #dma-channels = <16>;
215 #dma-requests = <16>;
221 compatible = "mediatek,mt7621-hsdma";
222 reg = <0x7000 0x1000>;
224 resets = <&sysc MT7621_RST_HSDMA>;
225 reset-names = "hsdma";
227 interrupt-parent = <&gic>;
228 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
239 compatible = "ralink,rt2880-pinmux";
240 pinctrl-names = "default";
241 pinctrl-0 = <&state_default>;
243 state_default: pinctrl0 {
281 rgmii1_pins: rgmii1 {
288 rgmii2_pins: rgmii2 {
329 sdhci: sdhci@1e130000 {
332 compatible = "ralink,mt7620-sdhci";
333 reg = <0x1e130000 0x4000>;
335 interrupt-parent = <&gic>;
336 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&sdhci_pins>;
342 xhci: xhci@1e1c0000 {
343 #address-cells = <1>;
346 compatible = "mediatek,mt8173-xhci";
347 reg = <0x1e1c0000 0x1000
349 reg-names = "mac", "ippc";
351 clocks = <&sysc MT7621_CLK_XTAL>;
352 clock-names = "sys_ck";
354 interrupt-parent = <&gic>;
355 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
358 * Port 1 of both hubs is one usb slot and referenced here.
359 * The binding doesn't allow to address individual hubs.
360 * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
362 xhci_ehci_port1: port@1 {
364 #trigger-source-cells = <0>;
368 * Only the second usb hub has a second port. That port serves
373 #trigger-source-cells = <0>;
377 gic: interrupt-controller@1fbc0000 {
378 compatible = "mti,gic";
379 reg = <0x1fbc0000 0x2000>;
381 interrupt-controller;
382 #interrupt-cells = <3>;
384 mti,reserved-cpu-vectors = <7>;
387 compatible = "mti,gic-timer";
388 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
389 clocks = <&sysc MT7621_CLK_CPU>;
394 compatible = "mti,mips-cpc";
395 reg = <0x1fbf0000 0x8000>;
399 compatible = "mti,mips-cdmm";
400 reg = <0x1fbf8000 0x8000>;
403 nand: nand@1e003000 {
406 compatible = "mediatek,mt7621-nfc";
407 reg = <0x1e003000 0x800
409 reg-names = "nfi", "ecc";
411 clocks = <&sysc MT7621_CLK_NAND>;
412 clock-names = "nfi_clk";
415 crypto: crypto@1e004000 {
416 compatible = "mediatek,mtk-eip93";
417 reg = <0x1e004000 0x1000>;
419 interrupt-parent = <&gic>;
420 interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
423 ethernet: ethernet@1e100000 {
424 compatible = "mediatek,mt7621-eth";
425 reg = <0x1e100000 0x10000>;
427 clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
428 clock-names = "fe", "ethif";
430 #address-cells = <1>;
433 resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
434 reset-names = "fe", "eth";
436 interrupt-parent = <&gic>;
437 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
439 mediatek,ethsys = <&sysc>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
445 compatible = "mediatek,eth-mac";
457 compatible = "mediatek,eth-mac";
464 #address-cells = <1>;
468 compatible = "mediatek,mt7621";
471 resets = <&sysc MT7621_RST_MCM>;
473 interrupt-controller;
474 #interrupt-cells = <1>;
475 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
478 #address-cells = <1>;
527 pcie: pcie@1e140000 {
528 compatible = "mediatek,mt7621-pci";
529 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
530 <0x1e142000 0x100>, /* pcie port 0 RC control registers */
531 <0x1e143000 0x100>, /* pcie port 1 RC control registers */
532 <0x1e144000 0x100>; /* pcie port 2 RC control registers */
533 #address-cells = <3>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&pcie_pins>;
541 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
542 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
546 #interrupt-cells = <1>;
547 interrupt-map-mask = <0xF800 0 0 0>;
548 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
549 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
550 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
552 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
555 reg = <0x0000 0 0 0 0>;
556 #address-cells = <3>;
560 #interrupt-cells = <1>;
561 interrupt-map-mask = <0 0 0 0>;
562 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
563 resets = <&sysc MT7621_RST_PCIE0>;
564 clocks = <&sysc MT7621_CLK_PCIE0>;
565 phys = <&pcie0_phy 1>;
566 phy-names = "pcie-phy0";
570 reg = <0x0800 0 0 0 0>;
571 #address-cells = <3>;
575 #interrupt-cells = <1>;
576 interrupt-map-mask = <0 0 0 0>;
577 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
578 resets = <&sysc MT7621_RST_PCIE1>;
579 clocks = <&sysc MT7621_CLK_PCIE1>;
580 phys = <&pcie0_phy 1>;
581 phy-names = "pcie-phy1";
585 reg = <0x1000 0 0 0 0>;
586 #address-cells = <3>;
590 #interrupt-cells = <1>;
591 interrupt-map-mask = <0 0 0 0>;
592 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
593 resets = <&sysc MT7621_RST_PCIE2>;
594 clocks = <&sysc MT7621_CLK_PCIE2>;
595 phys = <&pcie2_phy 0>;
596 phy-names = "pcie-phy2";
600 pcie0_phy: pcie-phy@1e149000 {
601 compatible = "mediatek,mt7621-pci-phy";
602 reg = <0x1e149000 0x0700>;
603 clocks = <&sysc MT7621_CLK_XTAL>;
607 pcie2_phy: pcie-phy@1e14a000 {
608 compatible = "mediatek,mt7621-pci-phy";
609 reg = <0x1e14a000 0x0700>;
610 clocks = <&sysc MT7621_CLK_XTAL>;