3 #include <dt-bindings/interrupt-controller/mips-gic.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/gpio/gpio.h>
10 compatible = "mediatek,mt7621-soc";
18 compatible = "mips,mips1004Kc";
24 compatible = "mips,mips1004Kc";
31 #interrupt-cells = <1>;
33 compatible = "mti,cpu-interrupt-controller";
41 bootargs = "console=ttyS0,57600";
45 compatible = "mediatek,mt7621-pll", "syscon";
48 clock-output-names = "cpu", "bus";
53 compatible = "fixed-clock";
55 /* FIXME: there should be way to detect this */
56 clock-frequency = <50000000>;
59 palmbus: palmbus@1E000000 {
60 compatible = "palmbus";
61 reg = <0x1E000000 0x100000>;
62 ranges = <0x0 0x1E000000 0x0FFFFF>;
68 compatible = "mtk,mt7621-sysc";
73 compatible = "mediatek,mt7621-wdt";
79 #interrupt-cells = <2>;
80 compatible = "mediatek,mt7621-gpio";
84 interrupt-parent = <&gic>;
85 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
89 compatible = "mediatek,mt7621-i2c";
94 resets = <&rstctrl 16>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&i2c_pins>;
107 compatible = "mediatek,mt7621-i2s";
110 clocks = <&sysclock>;
112 resets = <&rstctrl 17>;
115 interrupt-parent = <&gic>;
116 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
123 dma-names = "tx", "rx";
128 systick: systick@500 {
129 compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
132 resets = <&rstctrl 28>;
133 reset-names = "intc";
135 interrupt-parent = <&gic>;
136 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
140 compatible = "mtk,mt7621-memc";
141 reg = <0x5000 0x1000>;
145 compatible = "mtk,mt7621-cpc";
146 reg = <0x1fbf0000 0x8000>;
150 compatible = "mtk,mt7621-mc";
151 reg = <0x1fbf8000 0x8000>;
154 uartlite: uartlite@c00 {
155 compatible = "ns16550a";
158 clock-frequency = <50000000>;
160 interrupt-parent = <&gic>;
161 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
168 uartlite2: uartlite2@d00 {
169 compatible = "ns16550a";
172 clock-frequency = <50000000>;
174 interrupt-parent = <&gic>;
175 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&uart2_pins>;
186 uartlite3: uartlite3@e00 {
187 compatible = "ns16550a";
190 clock-frequency = <50000000>;
192 interrupt-parent = <&gic>;
193 interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&uart3_pins>;
207 compatible = "ralink,mt7621-spi";
210 clocks = <&pll MT7621_CLK_BUS>;
212 resets = <&rstctrl 18>;
215 #address-cells = <1>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&spi_pins>;
223 compatible = "ralink,rt3883-gdma";
224 reg = <0x2800 0x800>;
226 resets = <&rstctrl 14>;
229 interrupt-parent = <&gic>;
230 interrupts = <0 13 4>;
233 #dma-channels = <16>;
234 #dma-requests = <16>;
240 compatible = "mediatek,mt7621-hsdma";
241 reg = <0x7000 0x1000>;
243 resets = <&rstctrl 5>;
244 reset-names = "hsdma";
246 interrupt-parent = <&gic>;
247 interrupts = <0 11 4>;
258 compatible = "ralink,rt2880-pinmux";
259 pinctrl-names = "default";
260 pinctrl-0 = <&state_default>;
262 state_default: pinctrl0 {
300 rgmii1_pins: rgmii1 {
307 rgmii2_pins: rgmii2 {
349 compatible = "ralink,rt2880-reset";
354 compatible = "ralink,rt2880-clock";
358 sdhci: sdhci@1E130000 {
361 compatible = "ralink,mt7620-sdhci";
362 reg = <0x1E130000 0x4000>;
364 interrupt-parent = <&gic>;
365 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&sdhci_pins>;
371 xhci: xhci@1E1C0000 {
372 #address-cells = <1>;
376 compatible = "mediatek,mt8173-xhci";
377 reg = <0x1e1c0000 0x1000
379 reg-names = "mac", "ippc";
381 clocks = <&sysclock>;
382 clock-names = "sys_ck";
384 interrupt-parent = <&gic>;
385 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
388 * Port 1 of both hubs is one usb slot and referenced here.
389 * The binding doesn't allow to address individual hubs.
390 * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
392 xhci_ehci_port1: port@1 {
394 #trigger-source-cells = <0>;
398 * Only the second usb hub has a second port. That port serves
403 #trigger-source-cells = <0>;
407 gic: interrupt-controller@1fbc0000 {
408 compatible = "mti,gic";
409 reg = <0x1fbc0000 0x2000>;
411 interrupt-controller;
412 #interrupt-cells = <3>;
414 mti,reserved-cpu-vectors = <7>;
417 compatible = "mti,gic-timer";
418 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
419 clocks = <&pll MT7621_CLK_CPU>;
425 compatible = "fixed-clock";
427 clock-frequency = <125000000>;
430 nand: nand@1e003000 {
433 compatible = "mediatek,mt7621-nfc";
434 reg = <0x1e003000 0x800
436 reg-names = "nfi", "ecc";
438 clocks = <&nficlock>;
439 clock-names = "nfi_clk";
442 ethsys: syscon@1e000000 {
443 compatible = "mediatek,mt7621-ethsys",
445 reg = <0x1e000000 0x1000>;
449 ethernet: ethernet@1e100000 {
450 compatible = "mediatek,mt7621-eth";
451 reg = <0x1e100000 0x10000>;
453 clocks = <&sysclock>;
454 clock-names = "ethif";
456 #address-cells = <1>;
459 resets = <&rstctrl 6 &rstctrl 23>;
460 reset-names = "fe", "eth";
462 interrupt-parent = <&gic>;
463 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
465 mediatek,ethsys = <ðsys>;
468 compatible = "mediatek,eth-mac";
480 compatible = "mediatek,eth-mac";
483 phy-mode = "rgmii-rxid";
487 #address-cells = <1>;
491 compatible = "mediatek,mt7621";
492 #address-cells = <1>;
496 resets = <&rstctrl 2>;
500 #address-cells = <1>;
551 compatible = "mediatek,mt7621-gsw";
552 reg = <0x1e110000 0x8000>;
553 interrupt-parent = <&gic>;
554 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
557 pcie: pcie@1e140000 {
558 compatible = "mediatek,mt7621-pci";
559 reg = <0x1e140000 0x100 /* host-pci bridge registers */
560 0x1e142000 0x100 /* pcie port 0 RC control registers */
561 0x1e143000 0x100 /* pcie port 1 RC control registers */
562 0x1e144000 0x100>; /* pcie port 2 RC control registers */
563 #address-cells = <3>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&pcie_pins>;
573 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
574 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
577 interrupt-parent = <&gic>;
578 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
579 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
580 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
584 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
585 reset-names = "pcie0", "pcie1", "pcie2";
586 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
587 clock-names = "pcie0", "pcie1", "pcie2";
588 phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
589 phy-names = "pcie-phy0", "pcie-phy2";
591 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
594 reg = <0x0000 0 0 0 0>;
595 #address-cells = <3>;
598 bus-range = <0x00 0xff>;
602 reg = <0x0800 0 0 0 0>;
603 #address-cells = <3>;
606 bus-range = <0x00 0xff>;
610 reg = <0x1000 0 0 0 0>;
611 #address-cells = <3>;
614 bus-range = <0x00 0xff>;
618 pcie0_phy: pcie-phy@1e149000 {
619 compatible = "mediatek,mt7621-pci-phy";
620 reg = <0x1e149000 0x0700>;
624 pcie2_phy: pcie-phy@1e14a000 {
625 compatible = "mediatek,mt7621-pci-phy";
626 reg = <0x1e14a000 0x0700>;