1 #include <dt-bindings/interrupt-controller/mips-gic.h>
2 #include <dt-bindings/clock/mt7621-clk.h>
7 compatible = "mediatek,mt7621-soc";
15 compatible = "mips,mips1004Kc";
21 compatible = "mips,mips1004Kc";
28 #interrupt-cells = <1>;
30 compatible = "mti,cpu-interrupt-controller";
38 compatible = "mediatek,mt7621-pll", "syscon";
41 clock-output-names = "cpu", "bus";
46 compatible = "fixed-clock";
48 /* FIXME: there should be way to detect this */
49 clock-frequency = <50000000>;
54 palmbus: palmbus@1E000000 {
55 compatible = "palmbus";
56 reg = <0x1E000000 0x100000>;
57 ranges = <0x0 0x1E000000 0x0FFFFF>;
63 compatible = "mtk,mt7621-sysc";
68 compatible = "mediatek,mt7621-wdt";
76 compatible = "mtk,mt7621-gpio";
81 compatible = "mtk,mt7621-gpio-bank";
88 compatible = "mtk,mt7621-gpio-bank";
95 compatible = "mtk,mt7621-gpio-bank";
102 compatible = "mediatek,mt7621-i2c";
105 clocks = <&sysclock>;
107 resets = <&rstctrl 16>;
110 #address-cells = <1>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&i2c_pins>;
120 compatible = "mediatek,mt7621-i2s";
123 clocks = <&sysclock>;
125 resets = <&rstctrl 17>;
128 interrupt-parent = <&gic>;
129 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
136 dma-names = "tx", "rx";
141 systick: systick@d00 {
142 compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
145 resets = <&rstctrl 28>;
146 reset-names = "intc";
148 interrupt-parent = <&gic>;
149 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
153 compatible = "mtk,mt7621-memc";
154 reg = <0x5000 0x1000>;
158 compatible = "mtk,mt7621-cpc";
159 reg = <0x1fbf0000 0x8000>;
163 compatible = "mtk,mt7621-mc";
164 reg = <0x1fbf8000 0x8000>;
167 uartlite: uartlite@c00 {
168 compatible = "ns16550a";
171 clock-frequency = <50000000>;
173 interrupt-parent = <&gic>;
174 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
184 compatible = "ralink,mt7621-spi";
187 clocks = <&pll MT7621_CLK_BUS>;
189 resets = <&rstctrl 18>;
192 #address-cells = <1>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&spi_pins>;
200 compatible = "ralink,rt3883-gdma";
201 reg = <0x2800 0x800>;
203 resets = <&rstctrl 14>;
206 interrupt-parent = <&gic>;
207 interrupts = <0 13 4>;
210 #dma-channels = <16>;
211 #dma-requests = <16>;
217 compatible = "mediatek,mt7621-hsdma";
218 reg = <0x7000 0x1000>;
220 resets = <&rstctrl 5>;
221 reset-names = "hsdma";
223 interrupt-parent = <&gic>;
224 interrupts = <0 11 4>;
235 compatible = "ralink,rt2880-pinmux";
236 pinctrl-names = "default";
237 pinctrl-0 = <&state_default>;
239 state_default: pinctrl0 {
244 ralink,group = "i2c";
245 ralink,function = "i2c";
251 ralink,group = "spi";
252 ralink,function = "spi";
258 ralink,group = "uart1";
259 ralink,function = "uart1";
265 ralink,group = "uart2";
266 ralink,function = "uart2";
272 ralink,group = "uart3";
273 ralink,function = "uart3";
277 rgmii1_pins: rgmii1 {
279 ralink,group = "rgmii1";
280 ralink,function = "rgmii1";
284 rgmii2_pins: rgmii2 {
286 ralink,group = "rgmii2";
287 ralink,function = "rgmii2";
293 ralink,group = "mdio";
294 ralink,function = "mdio";
300 ralink,group = "pcie";
301 ralink,function = "pcie rst";
307 ralink,group = "spi";
308 ralink,function = "nand1";
312 ralink,group = "sdhci";
313 ralink,function = "nand2";
319 ralink,group = "sdhci";
320 ralink,function = "sdhci";
326 compatible = "ralink,rt2880-reset";
331 compatible = "ralink,rt2880-clock";
335 sdhci: sdhci@1E130000 {
338 compatible = "ralink,mt7620-sdhci";
339 reg = <0x1E130000 0x4000>;
341 interrupt-parent = <&gic>;
342 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&sdhci_pins>;
348 xhci: xhci@1E1C0000 {
349 #address-cells = <1>;
353 compatible = "mediatek,mt8173-xhci";
354 reg = <0x1e1c0000 0x1000
356 reg-names = "mac", "ippc";
358 clocks = <&sysclock>;
359 clock-names = "sys_ck";
361 interrupt-parent = <&gic>;
362 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
365 * Port 1 of both hubs is one usb slot and referenced here.
366 * The binding doesn't allow to address individual hubs.
367 * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
369 xhci_ehci_port1: port@1 {
371 #trigger-source-cells = <0>;
375 * Only the second usb hub has a second port. That port serves
380 #trigger-source-cells = <0>;
384 gic: interrupt-controller@1fbc0000 {
385 compatible = "mti,gic";
386 reg = <0x1fbc0000 0x2000>;
388 interrupt-controller;
389 #interrupt-cells = <3>;
391 mti,reserved-cpu-vectors = <7>;
394 compatible = "mti,gic-timer";
395 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
396 clocks = <&pll MT7621_CLK_CPU>;
400 nand: nand@1e003000 {
403 compatible = "mtk,mt7621-nand";
405 reg = <0x1e003000 0x800
409 ethernet: ethernet@1e100000 {
410 compatible = "mediatek,mt7621-eth";
411 reg = <0x1e100000 0x10000>;
413 #address-cells = <1>;
416 resets = <&rstctrl 6 &rstctrl 23>;
417 reset-names = "fe", "eth";
419 interrupt-parent = <&gic>;
420 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
422 mediatek,switch = <&gsw>;
425 #address-cells = <1>;
428 phy1f: ethernet-phy@1f {
435 compatible = "mediatek,mt7623-hnat";
440 resets = <&rstctrl 0>;
441 reset-names = "mtketh";
446 compatible = "mediatek,mt7621-gsw";
447 reg = <0x1e110000 0x8000>;
448 interrupt-parent = <&gic>;
449 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
452 pcie: pcie@1e140000 {
453 compatible = "mediatek,mt7621-pci";
454 reg = <0x1e140000 0x100
457 #address-cells = <3>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&pcie_pins>;
467 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
468 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
471 interrupt-parent = <&gic>;
472 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
473 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
474 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
478 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
479 reset-names = "pcie0", "pcie1", "pcie2";
480 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
481 clock-names = "pcie0", "pcie1", "pcie2";
484 reg = <0x0000 0 0 0 0>;
486 #address-cells = <3>;
493 reg = <0x0800 0 0 0 0>;
495 #address-cells = <3>;
502 reg = <0x1000 0 0 0 0>;
504 #address-cells = <3>;