3 #include <dt-bindings/interrupt-controller/mips-gic.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/gpio/gpio.h>
10 compatible = "mediatek,mt7621-soc";
22 compatible = "mips,mips1004Kc";
28 compatible = "mips,mips1004Kc";
35 #interrupt-cells = <1>;
37 compatible = "mti,cpu-interrupt-controller";
41 bootargs = "console=ttyS0,57600";
45 compatible = "mediatek,mt7621-pll", "syscon";
48 clock-output-names = "cpu", "bus";
53 compatible = "fixed-clock";
55 /* FIXME: there should be way to detect this */
56 clock-frequency = <50000000>;
59 palmbus: palmbus@1e000000 {
60 compatible = "palmbus";
61 reg = <0x1e000000 0x100000>;
62 ranges = <0x0 0x1e000000 0x0fffff>;
68 compatible = "mtk,mt7621-sysc";
73 compatible = "mediatek,mt7621-wdt";
79 #interrupt-cells = <2>;
80 compatible = "mediatek,mt7621-gpio";
84 interrupt-parent = <&gic>;
85 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
89 compatible = "mediatek,mt7621-i2c";
94 resets = <&rstctrl 16>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&i2c_pins>;
107 compatible = "mediatek,mt7621-i2s";
110 clocks = <&sysclock>;
112 resets = <&rstctrl 17>;
115 interrupt-parent = <&gic>;
116 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
123 dma-names = "tx", "rx";
128 systick: systick@500 {
129 compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
132 resets = <&rstctrl 28>;
133 reset-names = "intc";
135 interrupt-parent = <&gic>;
136 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
140 compatible = "mtk,mt7621-memc";
141 reg = <0x5000 0x1000>;
144 uartlite: uartlite@c00 {
145 compatible = "ns16550a";
148 clock-frequency = <50000000>;
150 interrupt-parent = <&gic>;
151 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
158 uartlite2: uartlite2@d00 {
159 compatible = "ns16550a";
162 clock-frequency = <50000000>;
164 interrupt-parent = <&gic>;
165 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&uart2_pins>;
176 uartlite3: uartlite3@e00 {
177 compatible = "ns16550a";
180 clock-frequency = <50000000>;
182 interrupt-parent = <&gic>;
183 interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&uart3_pins>;
197 compatible = "ralink,mt7621-spi";
200 clocks = <&pll MT7621_CLK_BUS>;
202 resets = <&rstctrl 18>;
205 #address-cells = <1>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&spi_pins>;
213 compatible = "ralink,rt3883-gdma";
214 reg = <0x2800 0x800>;
216 resets = <&rstctrl 14>;
219 interrupt-parent = <&gic>;
220 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
223 #dma-channels = <16>;
224 #dma-requests = <16>;
230 compatible = "mediatek,mt7621-hsdma";
231 reg = <0x7000 0x1000>;
233 resets = <&rstctrl 5>;
234 reset-names = "hsdma";
236 interrupt-parent = <&gic>;
237 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
248 compatible = "ralink,rt2880-pinmux";
249 pinctrl-names = "default";
250 pinctrl-0 = <&state_default>;
252 state_default: pinctrl0 {
290 rgmii1_pins: rgmii1 {
297 rgmii2_pins: rgmii2 {
339 compatible = "ralink,rt2880-reset";
344 compatible = "ralink,rt2880-clock";
348 sdhci: sdhci@1e130000 {
351 compatible = "ralink,mt7620-sdhci";
352 reg = <0x1e130000 0x4000>;
354 interrupt-parent = <&gic>;
355 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&sdhci_pins>;
361 xhci: xhci@1e1c0000 {
362 #address-cells = <1>;
365 compatible = "mediatek,mt8173-xhci";
366 reg = <0x1e1c0000 0x1000
368 reg-names = "mac", "ippc";
370 clocks = <&sysclock>;
371 clock-names = "sys_ck";
373 interrupt-parent = <&gic>;
374 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
377 * Port 1 of both hubs is one usb slot and referenced here.
378 * The binding doesn't allow to address individual hubs.
379 * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
381 xhci_ehci_port1: port@1 {
383 #trigger-source-cells = <0>;
387 * Only the second usb hub has a second port. That port serves
392 #trigger-source-cells = <0>;
396 gic: interrupt-controller@1fbc0000 {
397 compatible = "mti,gic";
398 reg = <0x1fbc0000 0x2000>;
400 interrupt-controller;
401 #interrupt-cells = <3>;
403 mti,reserved-cpu-vectors = <7>;
406 compatible = "mti,gic-timer";
407 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
408 clocks = <&pll MT7621_CLK_CPU>;
414 compatible = "fixed-clock";
416 clock-frequency = <125000000>;
420 compatible = "mti,mips-cpc";
421 reg = <0x1fbf0000 0x8000>;
425 compatible = "mti,mips-cdmm";
426 reg = <0x1fbf8000 0x8000>;
429 nand: nand@1e003000 {
432 compatible = "mediatek,mt7621-nfc";
433 reg = <0x1e003000 0x800
435 reg-names = "nfi", "ecc";
437 clocks = <&nficlock>;
438 clock-names = "nfi_clk";
441 ethsys: syscon@1e000000 {
442 compatible = "mediatek,mt7621-ethsys",
444 reg = <0x1e000000 0x1000>;
448 ethernet: ethernet@1e100000 {
449 compatible = "mediatek,mt7621-eth";
450 reg = <0x1e100000 0x10000>;
452 clocks = <&sysclock>;
453 clock-names = "ethif";
455 #address-cells = <1>;
458 resets = <&rstctrl 6 &rstctrl 23>;
459 reset-names = "fe", "eth";
461 interrupt-parent = <&gic>;
462 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
464 mediatek,ethsys = <ðsys>;
467 compatible = "mediatek,eth-mac";
479 compatible = "mediatek,eth-mac";
482 phy-mode = "rgmii-rxid";
486 #address-cells = <1>;
490 compatible = "mediatek,mt7621";
491 #address-cells = <1>;
495 resets = <&rstctrl 2>;
499 #address-cells = <1>;
550 compatible = "mediatek,mt7621-gsw";
551 reg = <0x1e110000 0x8000>;
552 interrupt-parent = <&gic>;
553 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
556 pcie: pcie@1e140000 {
557 compatible = "mediatek,mt7621-pci";
558 reg = <0x1e140000 0x100 /* host-pci bridge registers */
559 0x1e142000 0x100 /* pcie port 0 RC control registers */
560 0x1e143000 0x100 /* pcie port 1 RC control registers */
561 0x1e144000 0x100>; /* pcie port 2 RC control registers */
562 #address-cells = <3>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&pcie_pins>;
572 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
573 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
576 interrupt-parent = <&gic>;
577 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
578 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
579 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
583 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
584 reset-names = "pcie0", "pcie1", "pcie2";
585 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
586 clock-names = "pcie0", "pcie1", "pcie2";
587 phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
588 phy-names = "pcie-phy0", "pcie-phy2";
590 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
593 reg = <0x0000 0 0 0 0>;
594 #address-cells = <3>;
597 bus-range = <0x00 0xff>;
601 reg = <0x0800 0 0 0 0>;
602 #address-cells = <3>;
605 bus-range = <0x00 0xff>;
609 reg = <0x1000 0 0 0 0>;
610 #address-cells = <3>;
613 bus-range = <0x00 0xff>;
617 pcie0_phy: pcie-phy@1e149000 {
618 compatible = "mediatek,mt7621-pci-phy";
619 reg = <0x1e149000 0x0700>;
623 pcie2_phy: pcie-phy@1e14a000 {
624 compatible = "mediatek,mt7621-pci-phy";
625 reg = <0x1e14a000 0x0700>;