3 #include <dt-bindings/interrupt-controller/mips-gic.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/gpio/gpio.h>
10 compatible = "mediatek,mt7621-soc";
22 compatible = "mips,mips1004Kc";
28 compatible = "mips,mips1004Kc";
35 #interrupt-cells = <1>;
37 compatible = "mti,cpu-interrupt-controller";
41 bootargs = "console=ttyS0,57600";
46 compatible = "mediatek,mt7621-pll", "syscon";
49 clock-output-names = "cpu", "bus";
55 compatible = "fixed-clock";
57 /* FIXME: there should be way to detect this */
58 clock-frequency = <50000000>;
61 palmbus: palmbus@1e000000 {
62 compatible = "palmbus";
63 reg = <0x1e000000 0x100000>;
64 ranges = <0x0 0x1e000000 0x0fffff>;
71 compatible = "mtk,mt7621-sysc", "syscon";
73 compatible = "mediatek,mt7621-sysc", "syscon";
75 ralink,memctl = <&memc>;
76 clock-output-names = "xtal", "cpu", "bus",
77 "50m", "125m", "150m",
84 compatible = "mediatek,mt7621-wdt";
90 #interrupt-cells = <2>;
91 compatible = "mediatek,mt7621-gpio";
93 gpio-ranges = <&pinctrl 0 0 95>;
96 interrupt-parent = <&gic>;
97 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
101 compatible = "mediatek,mt7621-i2c";
104 clocks = <&sysclock>;
106 resets = <&rstctrl 16>;
109 #address-cells = <1>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&i2c_pins>;
119 compatible = "mediatek,mt7621-i2s";
122 clocks = <&sysclock>;
124 resets = <&rstctrl 17>;
127 interrupt-parent = <&gic>;
128 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
135 dma-names = "tx", "rx";
140 systick: systick@500 {
141 compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
144 resets = <&rstctrl 28>;
145 reset-names = "intc";
147 interrupt-parent = <&gic>;
148 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
153 compatible = "mtk,mt7621-memc", "syscon";
155 compatible = "mediatek,mt7621-memc", "syscon";
157 reg = <0x5000 0x1000>;
160 uartlite: uartlite@c00 {
161 compatible = "ns16550a";
164 clock-frequency = <50000000>;
166 interrupt-parent = <&gic>;
167 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
174 uartlite2: uartlite2@d00 {
175 compatible = "ns16550a";
178 clock-frequency = <50000000>;
180 interrupt-parent = <&gic>;
181 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&uart2_pins>;
192 uartlite3: uartlite3@e00 {
193 compatible = "ns16550a";
196 clock-frequency = <50000000>;
198 interrupt-parent = <&gic>;
199 interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&uart3_pins>;
213 compatible = "ralink,mt7621-spi";
217 clocks = <&pll MT7621_CLK_BUS>;
219 clocks = <&sysc MT7621_CLK_BUS>;
222 resets = <&rstctrl 18>;
225 #address-cells = <1>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&spi_pins>;
233 compatible = "ralink,rt3883-gdma";
234 reg = <0x2800 0x800>;
236 resets = <&rstctrl 14>;
239 interrupt-parent = <&gic>;
240 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
243 #dma-channels = <16>;
244 #dma-requests = <16>;
250 compatible = "mediatek,mt7621-hsdma";
251 reg = <0x7000 0x1000>;
253 resets = <&rstctrl 5>;
254 reset-names = "hsdma";
256 interrupt-parent = <&gic>;
257 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
268 compatible = "ralink,rt2880-pinmux";
269 pinctrl-names = "default";
270 pinctrl-0 = <&state_default>;
272 state_default: pinctrl0 {
310 rgmii1_pins: rgmii1 {
317 rgmii2_pins: rgmii2 {
359 compatible = "ralink,rt2880-reset";
364 compatible = "ralink,rt2880-clock";
368 sdhci: sdhci@1e130000 {
371 compatible = "ralink,mt7620-sdhci";
372 reg = <0x1e130000 0x4000>;
374 interrupt-parent = <&gic>;
375 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&sdhci_pins>;
381 xhci: xhci@1e1c0000 {
382 #address-cells = <1>;
385 compatible = "mediatek,mt8173-xhci";
386 reg = <0x1e1c0000 0x1000
388 reg-names = "mac", "ippc";
390 clocks = <&sysclock>;
391 clock-names = "sys_ck";
393 interrupt-parent = <&gic>;
394 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
397 * Port 1 of both hubs is one usb slot and referenced here.
398 * The binding doesn't allow to address individual hubs.
399 * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
401 xhci_ehci_port1: port@1 {
403 #trigger-source-cells = <0>;
407 * Only the second usb hub has a second port. That port serves
412 #trigger-source-cells = <0>;
416 gic: interrupt-controller@1fbc0000 {
417 compatible = "mti,gic";
418 reg = <0x1fbc0000 0x2000>;
420 interrupt-controller;
421 #interrupt-cells = <3>;
423 mti,reserved-cpu-vectors = <7>;
426 compatible = "mti,gic-timer";
427 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
429 clocks = <&pll MT7621_CLK_CPU>;
431 clocks = <&sysc MT7621_CLK_CPU>;
438 compatible = "fixed-clock";
440 clock-frequency = <125000000>;
444 compatible = "mti,mips-cpc";
445 reg = <0x1fbf0000 0x8000>;
449 compatible = "mti,mips-cdmm";
450 reg = <0x1fbf8000 0x8000>;
453 nand: nand@1e003000 {
456 compatible = "mediatek,mt7621-nfc";
457 reg = <0x1e003000 0x800
459 reg-names = "nfi", "ecc";
461 clocks = <&nficlock>;
462 clock-names = "nfi_clk";
465 ethernet: ethernet@1e100000 {
466 compatible = "mediatek,mt7621-eth";
467 reg = <0x1e100000 0x10000>;
470 clocks = <&sysclock>;
471 clock-names = "ethif";
473 clocks = <&sysc MT7621_CLK_FE>,
474 <&sysc MT7621_CLK_ETH>;
475 clock-names = "fe", "ethif";
478 #address-cells = <1>;
481 resets = <&rstctrl 6>, <&rstctrl 23>;
482 reset-names = "fe", "eth";
484 interrupt-parent = <&gic>;
485 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
487 mediatek,ethsys = <&sysc>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
493 compatible = "mediatek,eth-mac";
505 compatible = "mediatek,eth-mac";
508 phy-mode = "rgmii-rxid";
512 #address-cells = <1>;
516 compatible = "mediatek,mt7621";
519 resets = <&rstctrl 2>;
521 interrupt-controller;
522 #interrupt-cells = <1>;
523 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
526 #address-cells = <1>;
576 pcie: pcie@1e140000 {
577 compatible = "mediatek,mt7621-pci";
578 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
579 <0x1e142000 0x100>, /* pcie port 0 RC control registers */
580 <0x1e143000 0x100>, /* pcie port 1 RC control registers */
581 <0x1e144000 0x100>; /* pcie port 2 RC control registers */
582 #address-cells = <3>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&pcie_pins>;
591 ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */
592 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
594 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
595 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
601 interrupt-parent = <&gic>;
602 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
603 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
604 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
607 resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>;
608 reset-names = "pcie0", "pcie1", "pcie2";
609 clocks = <&clkctrl 24>, <&clkctrl 25>, <&clkctrl 26>;
610 clock-names = "pcie0", "pcie1", "pcie2";
611 phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
612 phy-names = "pcie-phy0", "pcie-phy2";
614 #interrupt-cells = <1>;
615 interrupt-map-mask = <0xF800 0 0 0>;
616 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
617 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
618 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
621 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
624 reg = <0x0000 0 0 0 0>;
625 #address-cells = <3>;
630 #interrupt-cells = <1>;
631 interrupt-map-mask = <0 0 0 0>;
632 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
633 resets = <&rstctrl 24>;
634 clocks = <&sysc MT7621_CLK_PCIE0>;
635 phys = <&pcie0_phy 1>;
636 phy-names = "pcie-phy0";
641 reg = <0x0800 0 0 0 0>;
642 #address-cells = <3>;
647 #interrupt-cells = <1>;
648 interrupt-map-mask = <0 0 0 0>;
649 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
650 resets = <&rstctrl 25>;
651 clocks = <&sysc MT7621_CLK_PCIE1>;
652 phys = <&pcie0_phy 1>;
653 phy-names = "pcie-phy1";
658 reg = <0x1000 0 0 0 0>;
659 #address-cells = <3>;
664 #interrupt-cells = <1>;
665 interrupt-map-mask = <0 0 0 0>;
666 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
667 resets = <&rstctrl 26>;
668 clocks = <&sysc MT7621_CLK_PCIE2>;
669 phys = <&pcie2_phy 0>;
670 phy-names = "pcie-phy2";
675 pcie0_phy: pcie-phy@1e149000 {
676 compatible = "mediatek,mt7621-pci-phy";
677 reg = <0x1e149000 0x0700>;
679 clocks = <&sysc MT7621_CLK_XTAL>;
684 pcie2_phy: pcie-phy@1e14a000 {
685 compatible = "mediatek,mt7621-pci-phy";
686 reg = <0x1e14a000 0x0700>;
688 clocks = <&sysc MT7621_CLK_XTAL>;