1 #include <dt-bindings/interrupt-controller/mips-gic.h>
6 compatible = "mediatek,mt7621-soc";
10 compatible = "mips,mips1004Kc";
14 compatible = "mips,mips1004Kc";
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
29 cpuclock: cpuclock@0 {
31 compatible = "fixed-clock";
33 /* FIXME: there should be way to detect this */
34 clock-frequency = <880000000>;
37 sysclock: sysclock@0 {
39 compatible = "fixed-clock";
41 /* FIXME: there should be way to detect this */
42 clock-frequency = <50000000>;
47 palmbus: palmbus@1E000000 {
48 compatible = "palmbus";
49 reg = <0x1E000000 0x100000>;
50 ranges = <0x0 0x1E000000 0x0FFFFF>;
56 compatible = "mtk,mt7621-sysc";
61 compatible = "mediatek,mt7621-wdt";
69 compatible = "mtk,mt7621-gpio";
74 compatible = "mtk,mt7621-gpio-bank";
81 compatible = "mtk,mt7621-gpio-bank";
88 compatible = "mtk,mt7621-gpio-bank";
95 compatible = "mediatek,mt7621-i2c";
100 resets = <&rstctrl 16>;
103 #address-cells = <1>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&i2c_pins>;
113 compatible = "mediatek,mt7621-i2s";
116 clocks = <&sysclock>;
118 resets = <&rstctrl 17>;
121 interrupt-parent = <&gic>;
122 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
129 dma-names = "tx", "rx";
134 systick: systick@d00 {
135 compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
138 resets = <&rstctrl 28>;
139 reset-names = "intc";
141 interrupt-parent = <&gic>;
142 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
146 compatible = "mtk,mt7621-memc";
151 compatible = "mtk,mt7621-cpc";
152 reg = <0x1fbf0000 0x8000>;
156 compatible = "mtk,mt7621-mc";
157 reg = <0x1fbf8000 0x8000>;
160 uartlite: uartlite@c00 {
161 compatible = "ns16550a";
164 clocks = <&sysclock>;
165 clock-frequency = <50000000>;
167 interrupt-parent = <&gic>;
168 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
178 compatible = "ralink,mt7621-spi";
181 clocks = <&sysclock>;
183 resets = <&rstctrl 18>;
186 #address-cells = <1>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&spi_pins>;
194 compatible = "ralink,rt3883-gdma";
195 reg = <0x2800 0x800>;
197 resets = <&rstctrl 14>;
200 interrupt-parent = <&gic>;
201 interrupts = <0 13 4>;
204 #dma-channels = <16>;
205 #dma-requests = <16>;
211 compatible = "mediatek,mt7621-hsdma";
212 reg = <0x7000 0x1000>;
214 resets = <&rstctrl 5>;
215 reset-names = "hsdma";
217 interrupt-parent = <&gic>;
218 interrupts = <0 11 4>;
229 compatible = "ralink,rt2880-pinmux";
230 pinctrl-names = "default";
231 pinctrl-0 = <&state_default>;
233 state_default: pinctrl0 {
238 ralink,group = "i2c";
239 ralink,function = "i2c";
245 ralink,group = "spi";
246 ralink,function = "spi";
252 ralink,group = "uart1";
253 ralink,function = "uart1";
259 ralink,group = "uart2";
260 ralink,function = "uart2";
266 ralink,group = "uart3";
267 ralink,function = "uart3";
271 rgmii1_pins: rgmii1 {
273 ralink,group = "rgmii1";
274 ralink,function = "rgmii1";
278 rgmii2_pins: rgmii2 {
280 ralink,group = "rgmii2";
281 ralink,function = "rgmii2";
287 ralink,group = "mdio";
288 ralink,function = "mdio";
294 ralink,group = "pcie";
295 ralink,function = "pcie rst";
301 ralink,group = "spi";
302 ralink,function = "nand1";
306 ralink,group = "sdhci";
307 ralink,function = "nand2";
313 ralink,group = "sdhci";
314 ralink,function = "sdhci";
320 compatible = "ralink,rt2880-reset";
325 compatible = "ralink,rt2880-clock";
329 sdhci: sdhci@1E130000 {
332 compatible = "ralink,mt7620-sdhci";
333 reg = <0x1E130000 0x4000>;
335 interrupt-parent = <&gic>;
336 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
339 xhci: xhci@1E1C0000 {
342 compatible = "mediatek,mt8173-xhci";
343 reg = <0x1e1c0000 0x1000
346 clocks = <&sysclock>;
347 clock-names = "sys_ck";
349 interrupt-parent = <&gic>;
350 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
353 gic: interrupt-controller@1fbc0000 {
354 compatible = "mti,gic";
355 reg = <0x1fbc0000 0x2000>;
357 interrupt-controller;
358 #interrupt-cells = <3>;
360 mti,reserved-cpu-vectors = <7>;
363 compatible = "mti,gic-timer";
364 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
365 clocks = <&cpuclock>;
369 nand: nand@1e003000 {
372 compatible = "mtk,mt7621-nand";
374 reg = <0x1e003000 0x800
376 #address-cells = <1>;
380 ethernet: ethernet@1e100000 {
381 compatible = "mediatek,mt7621-eth";
382 reg = <0x1e100000 0x10000>;
384 #address-cells = <1>;
387 resets = <&rstctrl 6 &rstctrl 23>;
388 reset-names = "fe", "eth";
390 interrupt-parent = <&gic>;
391 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
393 mediatek,switch = <&gsw>;
396 #address-cells = <1>;
399 phy1f: ethernet-phy@1f {
407 compatible = "mediatek,mt7621-gsw";
408 reg = <0x1e110000 0x8000>;
409 interrupt-parent = <&gic>;
410 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
413 pcie: pcie@1e140000 {
414 compatible = "mediatek,mt7621-pci";
415 reg = <0x1e140000 0x100
418 #address-cells = <3>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&pcie_pins>;
428 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
429 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
432 interrupt-parent = <&gic>;
433 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
434 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
435 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
439 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
440 reset-names = "pcie0", "pcie1", "pcie2";
441 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
442 clock-names = "pcie0", "pcie1", "pcie2";
445 reg = <0x0000 0 0 0 0>;
447 #address-cells = <3>;
454 reg = <0x0800 0 0 0 0>;
456 #address-cells = <3>;
463 reg = <0x1000 0 0 0 0>;
465 #address-cells = <3>;